Sealing chip, communication module and communication equipment

Abstract

The invention provides a sealing chip, a communication module and communication equipment, and the sealing chip comprises a bottom plate which comprises a first surface and a second surface, and the first surface is provided with a plurality of spherical pins; the first Flash bare chip and the DDR bare chip are arranged on the second surface, and the first Flash bare chip and the DDR bare chip are electrically connected with the circuit; and the plastic package body wraps the first Flash bare chip, the DDR bare chip and the bottom plate, and the plurality of spherical pins are exposed out of the plastic package body. By sealing the DDR chip and the Flash chip, the PCB can directly call the DDR chip and the Flash chip in the PCB through the sealing chip, so that the storage capacity is improved, the calling of a volatile memory and a nonvolatile memory is ensured, more capacity combinations and storage requirements are met, and the space burden of the PCB is reduced.

Description

Technical Field

[0001] The present application relates to the field of optical communications, and in particular to a packaging structure, a communication module and a communication device. Background Art

[0002] With the increasing demand for miniaturization and reduced manufacturing costs of optical communication equipment, printed circuit boards (PCBs), as circuit networks for connecting electronic components and relaying transmission in optical communication equipment, are also developing towards miniaturization and increasing circuit board density. As an indispensable storage device in optical communication equipment, a large number of double data rate SDRAM (DDR) chips and flash memory chips are required on PCBs. In addition, with the increasing demand for data transmission and storage of optical communication equipment, how to further increase storage capacity and realize more capacity combination requirements on PCB boards with limited space is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a packaged chip, a communication module and a communication device. By sealing a DDR chip and a Flash chip, a PCB can directly call the internal DDR chip and Flash chip through the packaged chip, thereby increasing the storage capacity, realizing more capacity combination requirements, and reducing the PCB space burden.

[0004] In a first aspect, a packaged chip is provided, comprising: a base plate, comprising a first surface and a second surface opposite to each other, a plurality of ball pins being arranged on the first surface, the plurality of ball pins being electrically connected to a circuit in the base plate, and the ball pins being used to connect to a printed circuit board; a first flash memory die Flash and a double data rate synchronous dynamic random access memory DDR die being arranged on the second surface, wherein the first Flash die and the DDR die are electrically connected to the circuit so that the first Flash die is electrically connected to at least one of the plurality of ball pins, and the DDR die is electrically connected to at least one of the plurality of ball pins; and a plastic package body wrapping the first Flash die, the DDR die and the base plate, with the plurality of ball pins exposed from the plastic package body.

[0005] By sealing the DDR chip and the Flash chip together, the PCB can directly call the internal DDR chip and Flash chip through the sealed chip, thereby increasing the storage capacity, ensuring the calling of volatile memory and non-volatile memory, achieving more capacity combinations and storage requirements, and reducing the PCB space burden.

[0006] In combination with the first aspect, in some implementations of the first aspect, the multiple ball pins include a common ball pin. The common ball pin is electrically connected to the DDR die and electrically connected to the first Flash die. The common ball pin is used to transmit a power signal or a ground signal. By designing a common pin in the co-packaged chip, the number of pins of the co-packaged chip is reduced, saving space.

[0007] In combination with the first aspect, in some implementations of the first aspect, where: the multiple ball pins include two functional ball pin groups. Among them, there is a first distance between the ball pins belonging to the same functional ball pin group, and there is a second distance between the ball pins belonging to different functional ball pin groups. The first distance is greater than the second distance; one of the two functional ball pin groups is used to transmit signals including one or more of a power signal, a ground signal, and a configuration signal; the other of the two functional ball pin groups is used to transmit signals including one or more of a control signal, a clock signal, an address signal, and a data signal. Thus, isolation between the pins for transmitting low-speed signals and high-speed signals is achieved, ensuring signal transmission in the ball pins of the co-packaged chip.

[0008] In combination with the first aspect, in some implementations of the first aspect, there is at least one ball pin spacing between the ball pins belonging to different functional ball pin groups. Thus, it is ensured that the first distance is greater than the second distance.

[0009] In combination with the first aspect, in some implementations of the first aspect, multiple ball pins are provided in the two side regions and the central region of the first surface, where: the ball pins located in the side regions are connected to the DDR die and / or the first Flash die; the ball pins located in the central region are connected to the first Flash die and not connected to the DDR die. Thus, compatibility with the original DDR package chip standard is ensured for the co-packaged chip, avoiding mutual interference between the signals transmitted by the DDR die and the signals transmitted by the first Flash chip, as well as problems with the PCB. Among them, the definition of the ball pins in the side regions can be the same as that of the original DDR package chip.

[0010] In combination with the first aspect, in certain implementations of the first aspect, where: the DDR die includes a first DDR sub-die and a second DDR sub-die, there is a gap between the first DDR sub-die and the second DDR sub-die, and the projection of the gap on the first surface overlaps with the central region; pads are provided on one side of the first DDR sub-die and the second DDR sub-die adjacent to the gap, the pads are in contact with the bottom plate, and the pads are electrically connected to the bottom plate. Thus, while ensuring that the ball pins can be set in the central region of the co-packaged chip, by splitting the DDR chip into two sub-chips and arranging the chip pads in the middle region of the chip, the signal transmission distance can be effectively shortened, the lead length can be reduced, signal attenuation can be reduced, and the anti-interference performance of the DDR chip can be improved.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the bottom plate, the DDR die, and the first Flash die are stacked, the DDR die is located between the first Flash die and the bottom plate, and the size of the bottom plate is larger than the sizes of the DDR die and the first Flash die. Thus, by stacking two dies and the bottom plate, the package area can be correspondingly reduced, the compatibility with the package form of the original DDR packaged chip can be achieved, and the supply flexibility can be improved.

[0012] In combination with the first aspect, in certain implementations of the first aspect, a substrate is further included, and the substrate is used for the electrical connection between the first Flash die and the ball pins among the multiple ball pins. The bottom plate, the DDR die, the substrate, and the first Flash die are stacked in sequence, and the size of the bottom plate is larger than the sizes of the substrate, the first Flash die, and the DDR die. Thus, by stacking two dies, the bottom plate, and the substrate, the package area can be correspondingly reduced, the compatibility with the package form of the original DDR packaged chip can be achieved, and the supply flexibility can be improved.

[0013] In combination with the first aspect, in certain implementations of the first aspect, at least one second Flash die is further included, where the second Flash die among the at least one second Flash die is electrically connected to at least one of the multiple ball pins. By providing multiple Flash dies, the storage capacity of the co-packaged chip is further improved, and various storage combination requirements can be achieved.

[0014] In a second aspect, a communication module is provided, including a printed circuit board, a control chip, and the co-packaged chip of the first aspect and any of its possible implementations.

[0015] In a third aspect, a communication device is provided, including the communication module of the second aspect and any of its possible implementations. Description of the Drawings

[0016] Figure 1 It is a schematic diagram of a co-packaged chip provided by an embodiment of the present application.

[0017] Figure 2 It is a schematic diagram of the spherical pin function of a co-packaged chip provided by an embodiment of the present application.

[0018] Figure 3 It is another schematic diagram of the spherical pin function of a co-packaged chip provided by an embodiment of the present application.

[0019] Figure 4 It is another schematic diagram of a co-packaged chip provided by an embodiment of the present application.

[0020] Figure 5 It is another schematic diagram of a co-packaged chip provided by an embodiment of the present application.

[0021] Figure 6 It is a schematic diagram of a communication module provided by an embodiment of the present application.

[0022] Figure 7 It is a schematic diagram of a communication device provided by the present application. Detailed implementation manners

[0023] Next, the technical solutions in the present application will be described in conjunction with the accompanying drawings.

[0024] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0025] The reference to "an embodiment" or "some embodiments" etc. described in this specification means that a specific feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in an embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0026] In the description of the embodiments of the present application, the orientation or positional relationship indicated by terms such as "upper", "lower", "vertical", "horizontal", etc. is defined relative to the orientation or position in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. It can change accordingly with the change of the orientation in which the components in the drawings are placed. Therefore, it should not be construed as a limitation to the present application.

[0027] As used in the embodiments of the present application, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0028] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. An embodiment or design solution described as "exemplary" or "for example" should not be construed as being more preferred or having more advantages than other embodiments or design solutions. The use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner for easy understanding.

[0029] In the embodiments of the present application, the same reference numeral is used to represent the same component or the same part. Additionally, the components in the drawings are not drawn to scale. The dimensions and sizes of the components shown in the drawings are only exemplary and should not be construed as a limitation to the present application.

[0030] It should be understood that in the present application, "electrically connected" can be understood as physical contact and electrical conduction between components, or can also be understood as a form of connection between different components in a circuit structure through an entity line such as a printed circuit board copper pad or a wire that can transmit electrical signals. In the description of the embodiments of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, or can be indirectly connected through an intermediate medium, and can be the internal connection or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0031] As the demand for miniaturization and reduced manufacturing costs of optical communication equipment increases, printed circuit boards (PCBs), as circuit networks for connecting electronic components and relaying transmission in optical communication equipment, are also developing towards miniaturization and increasing circuit board density. As an indispensable storage device in optical communication equipment, a large number of double data rate SDRAM (DDR) chips and flash memory chips are required on PCBs. Among them, DDR chips are a type of synchronous dynamic random access memory. DDR chips can transmit data once during the rising and falling periods of the clock cycle to achieve double the data transmission rate. The data storage time of dynamic random access memory is very short, and data will be lost after power failure. Flash chips are a long-lived non-volatile memory that can still save data after power failure. By arranging DDR chips and Flash chips on PCBs, the data storage and transmission efficiency of optical communication equipment can be guaranteed. However, with the increase in data transmission and storage requirements of optical communication equipment, how to further increase storage capacity and achieve more capacity combination requirements on PCB boards with limited space is a technical problem that needs to be solved urgently.

[0032] In view of this, the embodiments of the present application provide a packaged chip, a communication module and a communication device. By sealing the DDR chip and the Flash chip, the PCB can directly call the internal DDR chip and the Flash chip through the packaged chip, thereby increasing the storage capacity, realizing more capacity combination requirements, and reducing the PCB space burden.

[0033] Figure 1 Schematic diagram of a sealed chip provided in an embodiment of the present application. Figure 1 As shown, the packaged chip includes a base plate 110 , a first Flash die 120 , a DDR die 130 and a plastic package 140 .

[0034] The bottom plate 110 is plate-shaped, and a circuit is arranged in the bottom plate 110. The bottom plate 110 includes a first surface and a second surface opposite to each other. A plurality of ball pins 150 are arranged on the first surface. The plurality of ball pins 150 are electrically connected to the circuit arranged in the bottom plate 110, and the ball pins 150 are used to connect to the PCB board.

[0035] The first Flash die 120 and the DDR die 130 are located above the second surface. Among them, the first Flash die 120 and the DDR die 130 are electrically connected to the circuits in the bottom board 110, so that the first Flash die 120 is electrically connected to at least one of the plurality of ball pins, and the DDR die 130 is electrically connected to at least one of the plurality of ball pins. Among them, a die can refer to a small piece cut by laser on a silicon wafer, and corresponding functional circuits are provided in the die.

[0036] The encapsulant 140 wraps the first Flash die 120, the DDR die 130 and the bottom board 110, and the plurality of ball pins 150 in the bottom board 110 are exposed from the encapsulant. Among them, a plurality of through holes can be provided in one side of the encapsulant 140 that wraps the bottom board 110, and the through holes among the plurality of through holes correspond to the positions of the ball pins among the plurality of ball pins 150, so that the ball pins 150 are exposed from the side of the encapsulant 140 that wraps the bottom board 110.

[0037] It should be understood that this application does not limit the electrical connection manner between the first Flash die 120 and the circuits in the bottom board 110, nor the electrical connection manner between the DDR die 130 and the circuits in the bottom board 110. As a first electrical connection manner between the first Flash die 120 and the bottom board 110, the first Flash die 120 is electrically connected to the circuits in the bottom board 110 through leads. Or, at least one bump can be provided on one side of the first Flash die 120, and the Flash die 120 is electrically connected to the DDR die 130 through at least one bump and is electrically connected to the bottom board 110 through the DDR die 130. That is, the first Flash die 120 can be directly or indirectly electrically connected to the circuits in the bottom board 110. As a first electrical connection manner between the DDR die 130 and the bottom board 110, the DDR die 130 is electrically connected to the circuits in the bottom board 110 through leads. Or, at least one bump is provided on one side of the DDR die 130, and the DDR die 130 is flip-chip mounted on the bottom board 110 through at least one bump. Or, there are also pads or conductive adhesives for electrical connection provided between the DDR die 130 and the bottom edge 110.

[0038] In some implementation manners, such as Figure 1As shown in (a), the base plate 110, the DDR die 130, and the first Flash die 120 are stacked, and the DDR die 130 is located between the first Flash die 120 and the base plate 110. Among them, the size of the base plate 110 is larger than that of the first Flash die 120 and the DDR die 130. That is, the length of the base plate 110 is greater than the lengths of the first Flash die 120 and the DDR die 130. The width of the base plate 110 is greater than the widths of the first Flash die 120 and the DDR die 130. Thus, by stacking the two dies and the base plate, the package area can be correspondingly reduced, the package form of the co-packaged chip and the original DDR packaged chip can be made compatible, and the supply flexibility can be improved.

[0039] In some implementation manners, as Figure 1 shown in (b), the co-packaged chip further includes a substrate 121. The substrate 121 is used for the electrical connection between the first Flash die 120 and the ball-shaped pins among the plurality of ball-shaped pins. Among them, the first Flash die 120 can be wire-bonded to the substrate 121, or at least one bump is provided on one surface of the first Flash die 120, and the first Flash die 120 is flip-chip mounted on the substrate 121 through at least one bump. The substrate 121 is wire-bonded to the base plate 110. The base plate 110, the DDR die 130, the substrate 121, and the first Flash die 120 are stacked in sequence. Among them, the size of the base plate 110 is larger than that of the first Flash die 120, the DDR die 130, and the substrate 121. That is, the length of the base plate 110 is greater than the lengths of the first Flash die 120, the DDR die 130, and the substrate 121. The width of the base plate 110 is greater than the widths of the first Flash die 120, the DDR die 130, and the substrate 121. Thus, by stacking the two dies, the base plate, and the substrate, the package area can be correspondingly reduced, the package form of the co-packaged chip and the original DDR packaged chip can be made compatible, and the supply flexibility can be improved.

[0040] Among them, the package form of the co-packaged chip can be a fine-pitch ball grid array (FBGA package form), and the ball-shaped pins can also be understood as solder balls, and the solder balls are used to realize the mounting connection between the co-packaged chip and the PCB board. Among them, the base plate referred to in the present application can also specifically refer to a ball grid array substrate.

[0041] In the co-packaged chip as Figure 1 shown, by co-packaging the DDR chip and the Flash chip, the PCB can directly call the internal DDR chip and Flash chip through the co-packaged chip, thereby increasing the storage capacity, ensuring the call of the volatile memory and the non-volatile memory, realizing more capacity combinations and storage requirements, and reducing the space burden of the PCB.

[0042] Figure 2 This is a schematic diagram of the ball grid array (BGA) pin functions of a co-packaged chip provided by an embodiment of this application. Figure 2 It specifically shows the specific functions of multiple BGA pins in the co-packaged chip. The pins of the co-packaged chip can be compatible with the packaging form of the original DDR packaged chip. Taking the original DDR packaged chip with 78 BGA pins as an example, the columns where the BGA pins are located are marked from 1 to 9 on the upper side of the co-packaged chip, and the rows where the BGA pins are located are marked from A to N on the left side. The BGA pins in the two side regions of the co-packaged chip have the same functions as the BGA pins of the original DDR packaged chip, which will not be elaborated here one by one.

[0043] Among them, the K, M rows of the 1st column, the M, T rows of the 7th column, and the J, L rows of the 9th column in the co-packaged chip include no-connection (NC) BGA pins. Among them, the NC pins are not connected to the DDR die. Therefore, the above 6 NC BGA pins can be connected to the first Flash die for signal transmission between the PCB and the first Flash die.

[0044] In some implementation manners, multiple BGA pins in the co-packaged chip include shared BGA pins. The shared BGA pins are electrically connected to the DDR die and electrically connected to the first Flash die. The shared pin can specifically be the VSS pin in the T row of the 1st column. That is, the shared BGA pin is used to transmit a power signal (such as the negative pole of the power signal) or a ground signal. In addition, according to the actual design, the shared BGA pin can also be used to transmit other signals, and this application does not limit this. By designing shared pins in the co-packaged chip, the number of pins of the co-packaged chip is reduced, saving space.

[0045] In some implementation manners, multiple BGA pins include two functional BGA pin groups. Among them, there is a first distance between the BGA pins belonging to the same functional BGA pin group, and there is a second distance between the BGA pins belonging to different functional BGA pin groups, and the first distance is greater than the second distance. Among them, the BGA pins in the two functional BGA pin groups can specifically be connected to the DDR die and / or the first Flash die. In the two functional BGA pin groups, the signals transmitted by the first functional BGA pin group include one or more of a power signal, a ground signal, and a configuration signal. The signals transmitted by the second functional BGA pin group include one or more of a control signal, a clock signal, an address signal, and a data signal. Thus, isolation between the pins for transmitting low-speed signals and high-speed signals is achieved, ensuring signal transmission in the BGA pins of the co-packaged chip. In some implementation manners, there is at least one BGA pin between the BGA pins belonging to different functional BGA pin groups, so as to ensure that the first distance is greater than the second distance.

[0046] It should be understood that Figure 2The 78 (6×13) functional ball pins provided in the two-side regions specifically shown are only for illustrative purposes. In addition, the two-side regions of the co-packaged chip may specifically be provided with 96 (6×16) functional ball pins, 112 (6×17) functional ball pins, etc., which are determined according to specific circumstances. In addition, the ball pins may also be redefined according to the actual situation, and the present application does not limit this.

[0047] Figure 3 is a schematic diagram of the functions of the ball pins of another co-packaged chip provided by an embodiment of the present application. Among them, the ball pins in the two-side regions of the co-packaged chip are the same as Figure 2 described and will not be elaborated here. In addition, ball pins are provided in the central region of the co-packaged chip.

[0048] Among them, the ball pins located in the two-side regions are connected to the DDR die and / or the first Flash die. The ball pins located in the central region are connected to the first Flash die, and the ball pins located in the central region are not connected to the DDR die.

[0049] That is, the co-packaged chip preferentially connects the ball pins in the two-side regions to the DDR die, and connects the ball pins in the central region to the first Flash die, so as to ensure the compatibility of the co-packaged chip with the original DDR package chip standard, avoid the mutual interference between the signals transmitted by the DDR die and the signals transmitted by the first Flash chip, and avoid problems with the PCB. Among them, the definition of the ball pins in the two-side regions may be the same as that of the original DDR package chip.

[0050] Figure 3 In (a), (b), and (c) respectively show the situations where the co-packaged chip includes 13, 16, and 17 rows of ball pins. Among them, the ball pins located in the central region can be used to connect to the first Flash die.

[0051] Figure 4 is another schematic diagram of the co-packaged chip provided by an embodiment of the present application. As Figure 4 shown, the co-packaged chip includes a bottom plate 410, a first Flash die 420, a DDR die 430, and a plastic package 440. Among them, the bottom plate 410, the first Flash die 420, the DDR die 430, and the plastic package 440 are similar to Figure 1 the bottom plate 110, the first Flash die 120, the DDR die 130, and the plastic package 140 described and will not be elaborated here.

[0052] Same as Figure 3Corresponding to the situation shown, the DDR die 430 includes a first DDR sub-die 431 and a second DDR sub-die 432. There is a gap between the first DDR sub-die 431 and the second DDR sub-die 432, and the projection of this gap on the first surface overlaps with the central region. On one side of the gap adjacent to the first DDR sub-die 431 and the second DDR sub-die 432, there are pads 433 and 434. The pads 433 and 434 are in contact with the bottom plate 410. The pads 433 and 434 are electrically connected to the bottom plate 410.

[0053] Thus, on the premise of ensuring that the ball pins can be arranged in the central region of the co-packaged chip, by splitting the DDR chip into two sub-chips and arranging the chip pads in the middle region of the chip, the signal transmission distance can be effectively shortened, the lead length can be reduced, the signal attenuation can be decreased, and the anti-interference performance of the DDR chip can be improved.

[0054] Figure 5 It is a schematic diagram of another co-packaged chip provided by an embodiment of the present application. As Figure 5 shown, the co-packaged chip includes a bottom plate 510, a first Flash die 520, a DDR die 530, a plastic package 540, and at least one second Flash die 560. Among them, the bottom plate 510, the first Flash die 520, the DDR die 530, and the plastic package 540 are similar to the bottom plate 110, the first Flash die 120, the DDR die 130, and the plastic package 140 described in Figure 1 and will not be elaborated here.

[0055] As Figure 5 shown, at least one second Flash die can be stacked on the first Flash die 520. In some implementation manners, the second Flash die 560 in at least one second Flash die is connected to the bottom plate 510 through leads, so that the second Flash die is electrically connected to at least one of the multiple ball pins.

[0056] In some implementation manners, a substrate is arranged between two adjacent second Flash dies 560 in at least one second Flash die, and the substrate arranged between two adjacent second Flash dies is connected to the bottom plate 510 through leads, so that the second Flash die is electrically connected to at least one of the multiple ball pins. The specific electrical connection manner is determined according to the actual situation.

[0057] In some implementation manners, the first Flash die and at least one second Flash die can be stacked in a staggered manner. In the first Flash die and at least one second Flash die, the non-overlapping parts of two adjacent dies can be used to arrange pads, which is convenient for lead connection.

[0058] In the co-packaged chip as Figure 5 shown, by setting multiple Flash dies, the storage capacity of the co-packaged chip can be further increased to meet various storage combination requirements.

[0059] Figure 6 is a schematic diagram of a communication module provided by an embodiment of the present application. As Figure 6 shown, the communication module includes a PCB 610, a control chip 620, and a co-packaged chip 630.

[0060] Among them, the control chip 620 and the co-packaged chip 630 are disposed on the PCB. The control chip 620 is connected to the co-packaged chip 630 through the circuit on the PCB to control the data transmission of the co-packaged chip 630. The co-packaged chip 630 may refer to Figures 1 to 5 the co-packaged chip described in

[0061] Among them, the control chip 620 may specifically be an application specific integrated circuit (ASIC), a microcontroller unit (MCU), a control module on chip (CMC), etc., which is determined according to the actual situation. The control chip 620 is used to execute instructions.

[0062] The Flash dies in the co-packaged chip are used to store program codes and data, where the Flash dies may specifically refer to the first Flash die or any second Flash die. The DDR die is used to temporarily store and cache data. Thus, the communication module can provide high-speed read and write capabilities.

[0063] Figure 7 is a schematic diagram of a communication device provided by the present application. As Figure 7 shown, the communication device includes the communication module as Figure 6 described. As Figure 7 shown, the communication device includes a system on chip 710, a co-packaged chip 720, an optical transmission unit 730, a radio frequency transmission unit 740, a network port unit 750, an interface unit 760, a serial port unit 770, etc.

[0064] Among them, the system on chip 710 may include Figure 6 the control chip described in Figure 6The functions described therein are similar and will not be elaborated here. The optical transmission unit 730 is used to transmit and / or receive optical signals. The radio frequency transmission unit 740 is used to transmit and / or receive radio frequency signals. The network interface unit 750 is used for connection to a network interface. The interface unit 760 may refer to a general-purpose input / output (GPIO). The serial port unit 770 is a serial communication interface for data transmission.

[0065] Among them, the communication device referred to in this application may be an optical access device, an optical transmission device, an optical terminal device, etc., and may specifically be an optical modem, a router, an access point, a switch, an optical line terminal (OLT), an optical network unit (ONU), and an optical distribution network (ODN), etc. The applicable network may specifically be a passive optical network (PON), specifically, for example, a next-generation PON (NG-PON), NG-PON1, NG-PON2, a gigabit-capable PON (GPON), a wavelength-division multiplexing (WDM) PON, a time-and wavelength-division multiplexing (TWDM) PON, a point-to-point (P2P) WDMPON (P2P-WDMPON), etc.

[0066] Those of ordinary skill in the art can realize that the units, illustrative logical blocks, and steps of the various examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0067] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0068] It should be understood that "at least one" in the embodiments of the present application means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or a similar expression thereof refers to any combination of these items, including any combination of a single item or multiple items. For example, at least one (item) of a, b, and c can represent: a, or b, or c, or a and b, or a and c, or b and c, or a, b, and c. Where a, b, and c can be single or multiple respectively.

[0069] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0070] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application and should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A co-packaged chip, characterized in that, Comprising: A bottom plate, including opposite first and second surfaces, on which a plurality of spherical pins are provided, the plurality of spherical pins being electrically connected to a circuit in the bottom plate, and the spherical pins being used for connecting to a printed circuit board; A first flash memory die and a double data rate synchronous dynamic random access memory (DDR) die, disposed on the second surface, wherein the first flash memory die and the DDR die are electrically connected to the circuit so that the first flash memory die is electrically connected to at least one of the plurality of spherical pins, and the DDR die is electrically connected to at least one of the plurality of spherical pins; A plastic package body, wrapping the first flash memory die, the DDR die and the bottom plate, and the plurality of spherical pins protruding from the plastic package body.

2. The co-packaged chip according to claim 1, wherein, The plurality of spherical pins include common spherical pins, the common spherical pins being electrically connected to the DDR die and electrically connected to the first flash memory die, and the common spherical pins being used for transmitting a power signal or a ground signal.

3. The co-packaged chip according to claim 1 or 2, characterized in that, Wherein: The plurality of spherical pins include two functional spherical pin groups, wherein there is a first distance between the spherical pins belonging to the same functional spherical pin group, and there is a second distance between the spherical pins belonging to different functional spherical pin groups, and the first distance is greater than the second distance; One of the two functional spherical pin groups is used for transmitting signals including one or more of a power signal, a ground signal, and a configuration signal; The other of the two functional spherical pin groups is used for transmitting signals including one or more of a control signal, a clock signal, an address signal, and a data signal.

4. The co-packaged chip according to claim 3, wherein There is at least one spherical pin between the spherical pins belonging to different functional spherical pin groups.

5. The co-packaged chip according to any one of claims 1 to 4, characterized in that The plurality of spherical pins are provided in two side regions and a central region of the first surface, wherein: The spherical pins located in the two side regions are in communication with the DDR die and / or the first flash memory die; The spherical pins located in the central region are in communication with the first flash memory die and not in communication with the DDR die.

6. The co-packaged chip according to claim 5, wherein Wherein: The DDR die includes a first DDR sub-die and a second DDR sub-die, there is a gap between the first DDR sub-die and the second DDR sub-die, and the projection of the gap on the first surface overlaps with the central region; Pads are provided on one side of the first DDR sub-die and the second DDR sub-die adjacent to the gap, the pads are in contact with the bottom plate, and the pads are electrically connected to the bottom plate.

7. The co-packaged chip according to any one of claims 1 to 6, characterized in that, The bottom plate, the DDR die and the first flash memory die are stacked, the DDR die is located between the first flash memory die and the bottom plate, and the size of the bottom plate is larger than the sizes of the DDR die and the first flash memory die.

8. The co-packaged chip according to any one of claims 1 to 7, characterized in that, Further included is a substrate for electrically connecting the first Flash die to the ball pins among the plurality of ball pins. The base plate, the DDR die, the substrate, and the first Flash die are sequentially stacked, and the size of the base plate is larger than the sizes of the substrate, the first Flash die, and the DDR die.

9. The co-packaged chip according to any one of claims 1 to 8, characterized in that, Further included is at least one second Flash die, wherein the second Flash die among the at least one second Flash die is electrically connected to at least one ball pin among the plurality of ball pins.

10. A communication module, characterized in that, Including the printed circuit board, the control chip, and the co-packaged chip according to any one of claims 1 to 9.

11. A communication device, characterized in that, Including the communication module according to claim 10.

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