Electronic device

Abstract

The invention relates to an electronic device. A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip selection signal to a first memory device and a second memory device mounted on a front surface; and a plurality of second wirings for propagating the second clock signal and the second chip selection signal to a third memory device and a fourth memory device mounted on the rear surface. A plurality of first wirings are disposed in a wiring layer closer to the front surface among the plurality of wiring layers, and a plurality of second wirings are disposed in a wiring layer closer to the rear surface among the plurality of wiring layers.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure (including the specification, drawings, and abstract) of Japanese Patent Application No. 2023-221744 filed on December 27, 2023 is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an electronic device, and more particularly to an electronic device including a control device and a plurality of memory devices mounted on a wiring substrate. Background Art

[0004] A technique is disclosed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2015-35159

[0006] Patent Document 1 discloses an electronic device that can mitigate the influence of signal reflection even when the branch wiring for flyover topology is long. The electronic device includes a mounting substrate on which a plurality of first semiconductor components and a second semiconductor component for controlling the first semiconductor components are mounted. The mounting substrate includes main wiring and branch wiring for electrically connecting the second semiconductor component and the first semiconductor components. Chip resistors are connected in series at an intermediate portion of the branch wiring leading to the first semiconductor components. Summary of the Invention

[0007] In recent years, there has been a need to reduce the size of electronic devices, in other words, to reduce the mounting area of each device in a wiring substrate. In addition, particularly as the speed of electronic devices increases, there is a need to improve the waveform integrity (quality) of each signal propagating in the wiring substrate. As a method for improving waveform integrity, a method of providing a resistor device for attenuating reflected signals has been proposed, for example, as described in Patent Document 1. However, with this resistor device, the mounting area is increased. Therefore, a mechanism is desired that can improve waveform integrity without providing such a resistor device.

[0008] Other objects and novel features will become apparent from the description of this specification and the drawings.

[0009] An electronic device according to an embodiment includes: a wiring substrate having a first surface, a second surface opposite to the first surface, a plurality of wiring layers, and a plurality of wirings; a first memory device and a second memory device mounted on the first surface; a third memory device and a fourth memory device mounted on the second surface; and a control device. The control device is mounted on the first surface and is configured to access each of the first memory device and the second memory device by using a common first clock signal and a common first chip select signal, and is configured to access each of the third memory device and the fourth memory device by using a common second clock signal and a common second chip select signal. The plurality of wirings include: a plurality of first wirings through which the common first clock signal and the common first chip select signal propagate; and a plurality of second wirings through which the common second clock signal and the common second chip select signal propagate. The plurality of first wirings are provided in a wiring layer among the plurality of wiring layers that is closer to the first surface than the second surface, and the plurality of second wirings are provided in a wiring layer among the plurality of wiring layers that is closer to the second surface than the first surface.

[0010] According to one embodiment, the waveform integrity of a signal can be improved by using the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a plan view schematically illustrating an exemplary configuration of an electronic device according to a first embodiment;

[0012] Figure 1B is a plan view schematically illustrating an exemplary configuration of an electronic device according to a first embodiment;

[0013] Figure 2 is a plan view schematically illustrating an exemplary configuration focusing on Figure 1A and Figure 1B partial regions in;

[0014] Figure 3 is a circuit diagram schematically illustrating an exemplary connection between a memory interface and a memory device in Figure 2 ;

[0015] Figure 4A is a cross-sectional view schematically illustrating an exemplary configuration of a clock signal and a chip select signal along line A-A' of Figure 2 ;

[0016] Figure 4B is a cross-sectional view schematically illustrating an exemplary configuration of a clock signal and a chip select signal along line B-B' of Figure 2 ;

[0017] Figure 5 is a cross-sectional view schematically illustrating an exemplary configuration of a clock signal and a chip select signal along line Figure 2Cross-sectional view of an exemplary schematic configuration of a command address signal of line A-A';

[0018] Figure 6 is a diagram showing Figure 4A and Figure 4B Impedance diagram of exemplary impedance characteristics of through-via segments and open-circuit stubs for signal propagation in;

[0019] Figure 7 is a graph showing exemplary calculation results of how a quarter-length of the wavelength "λ" of a propagating signal depends on the Nyquist frequency;

[0020] Figure 8A is a diagram showing Figure 4A Exemplary equivalent configuration circuit diagram of the signal propagation path to column 1 in;

[0021] Figure 8B is a conceptual diagram showing the elimination of Figure 8A Timing diagram of the mechanism for reflected signals in;

[0022] Figure 9 is a diagram showing for Figure 4A Exemplary simulation results waveform diagram of the memory device closer to the control device in, obtained by observing the input waveform of the chip select signal;

[0023] Figure 10 is a diagram showing for Figure 4A Exemplary simulation results waveform diagram of the memory device closer to the control device and the memory device farther from the control device in, obtained by observing the input waveform of the clock signal;

[0024] Figure 11A is a diagram showing along Figure 2 Cross-sectional view of a more detailed exemplary configuration of line A-A';

[0025] Figure 11B is a diagram showing along Figure 2 Cross-sectional view of a more detailed exemplary configuration of line B-B';

[0026] Figure 12 is a diagram showing Figure 4A Cross-sectional view of an extended exemplary configuration of the configuration of;

[0027] Figure 13 is a cross-sectional view of an exemplary schematic configuration of a clock signal, a chip select signal, and a command address signal along line A-A' in an electronic device according to a second embodiment; Figure 2 ;

[0028] Figure 14 is a diagram showing for Figure 13Table of combinations of "n" and "m" that should be avoided due to the wiring length between the control device and the memory device;

[0029] Figure 15A is a diagram for schematically explaining an exemplary problem in a typical electronic device;

[0030] Figure 15B is a diagram for schematically explaining an exemplary problem in a typical electronic device;

[0031] Figure 16 is a diagram showing Figure 15A exemplary waveforms of clock signals input by two memory devices in;

[0032] Figure 17A is a diagram showing Figure 4A exemplary cross-sectional configurations of an electronic device according to a comparative example different from; and

[0033] Figure 17B is a diagram showing Figure 4B exemplary cross-sectional configurations of an electronic device according to a comparative example different from. DETAILED DESCRIPTION

[0034] In the embodiments described below, for convenience, the present invention will be described in multiple parts or embodiments as needed. However, unless otherwise stated, these parts or embodiments are not independent of each other, and one part or embodiment relates to all or part of another part or embodiment as a modified example, detail, or supplementary explanation thereof. In addition, in the embodiments described below, when referring to the number of elements (including the number of parts, values, quantities, ranges, etc.), the number of elements is not limited to a specific number, unless otherwise stated, or unless the number is clearly limited to a specific number in principle. Numbers greater than or less than the specified number are also applicable.

[0035] Furthermore, in the embodiments described below, it goes without saying that components (including element steps) are not always essential, unless otherwise stated, or unless the components are clearly essential in principle. Similarly, in the embodiments described below, when referring to the shape of components, their positional relationships, etc., this includes substantially approximate and similar shapes, etc., unless otherwise stated, or unless they can be clearly excluded in principle. The same applies to the above values and ranges.

[0036] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description is omitted. In addition, unless otherwise specifically required in the following embodiments, the description of the same or similar parts is not repeated in principle.

[0037] (First Embodiment)

[0038] <Overall Overview of the Electronic Device>

[0039] Figure 1A And Figure 1B are plan views showing exemplary schematic configurations of the electronic device according to the first embodiment in each figure. Figure 1A And Figure 1B The illustrated electronic device 10 includes a wiring substrate PCB, a plurality of memory devices ME, and a control device CTL. The electronic device 10 is particularly suitable for signal processing devices or information processing devices that require broadband and large-capacity memory, such as data centers, network base stations, and game terminals.

[0040] The wiring substrate PCB has a front surface (first surface) 20, a rear surface (second surface) 21 opposite to the front surface 20, a plurality of wiring layers, and a plurality of wirings. Figure 1A And Figure 1B respectively show exemplary configurations of the front surface 20 and the rear surface 21 of the wiring substrate PCB. In this specification, the mutually orthogonal directions are assumed to be the X-axis direction, the Y-axis direction, and the Z-axis direction, and the planar direction of the wiring substrate PCB is referred to as the X-axis direction and the Y-axis direction, while the thickness direction of the wiring substrate PCB is referred to as the Z-axis direction.

[0041] Each of the memory devices ME is, for example, a double data rate 5 synchronous dynamic random access memory (DDR5_SDRAM) or the like. In this example, 32 memory devices ME are mounted on each of the front surface 20 and the rear surface 21 of the wiring substrate PCB. The 32 memory devices ME mounted on the front surface 20 are arranged along the outer periphery (three of the four sides) of the wiring substrate PCB in a form of, for example, two rows by 16 columns. The 32 memory devices ME mounted on the rear surface 21 are arranged to face the 32 memory devices ME mounted on the front surface 20 in the Z-axis direction.

[0042] The control device CTL is, for example, a system-on-chip (SoC) or the like including various circuit blocks represented by a processor. In this example, the control device CTL is mounted on the front surface 20 of the wiring substrate PCB and is arranged near the center of the wiring substrate PCB. The control device CTL includes a plurality of memory interfaces for accessing the memory devices ME. In this example, two memory interfaces MIF1 and MIF2 among the memory interfaces are illustrated.

[0043] Figure 2 is a plan view showing an exemplary configuration focusing on Figure 1A And Figure 1B partial area 11 in Figure 2In this case, the memory interface MIF1 is connected, via a plurality of wirings WR1 in the wiring substrate PCB, to two memory devices ME1 and ME2 mounted on the front surface 20 of the wiring substrate PCB and two memory devices ME3 and ME4 mounted on the rear surface 21 facing these memory devices. Similarly, the memory interface MIF2 is connected, via a plurality of wirings WR2 in the wiring substrate PCB, to two memory devices ME5 and ME6 mounted on the front surface 20 of the wiring substrate PCB and two memory devices ME7 and ME8 mounted on the rear surface 21 facing these memory devices.

[0044] The two memory devices ME1 and ME2 are arranged side by side in the X-axis direction. The two memory devices ME5 and ME6 are also arranged side by side in the X-axis direction. The memory device ME1 and the memory device ME5 are arranged side by side in the Y-axis direction in a region closer to the control device CTL. The memory device ME2 and the memory device ME6 are arranged side by side in the Y-axis direction in a region farther from the control device CTL.

[0045] The memory interfaces MIF1 and MIF2 are arranged side by side in the X-axis direction. The memory interface MIF2 and its external terminals are arranged closer to the inside of the control device CTL than the memory interface MIF1 and its external terminals. In other words, the memory interface MIF1 is arranged closer to the outer periphery of the control device CTL than the memory interface MIF2.

[0046] More specifically, as Figure 2 shown, the set of the memory interfaces MIF1 and MIF2 is arranged side by side along Figure 1A the outer periphery of the control device CTL in Figure 1A . In the example of

[0047] Figure 3 , eight sets of the memory interfaces MIF1 and MIF2 are arranged. As described above, since the memory interfaces MIF1 and MIF2 are arranged side by side not in the Y-axis direction but in the X-axis direction, the outer periphery of the control device CTL can be shortened, thereby reducing the size of the control device CTL and thus reducing the size of the electronic device 10. Figure 2 is a circuit diagram illustrating an exemplary connection between the memory interfaces MIF1, MIF2 and the memory devices ME1 to ME8 in

[0048] Each of the memory devices ME1, ME2, ME5, and ME6 installed on the front surface 20 of the wiring substrate configures the memory devices of column 0. Each of the memory devices ME3, ME4, ME7, and ME8 installed on the back surface of the wiring substrate configures the memory devices of column 1. The memory interface MIF1 accesses the memory devices ME1 and ME2 of column 0 by using the common clock signal CK0 and the common chip select signal CS0.

[0049] The memory interface MIF1 accesses the memory devices ME3 and ME4 of column 1 by using the common clock signal CK1 and the common chip select signal CS1 different from the clock signal CK0 and the chip select signal CS0. In addition, the memory interface MIF1 outputs the common command address signal CA to the memory devices ME1 to ME4 of columns 0 and 1.

[0050] When accessing the memory devices ME1 and ME2 of column 0, the memory interface MIF1 inputs / outputs the data signal DQ of the memory device ME1 as the lower data signal DQ-L, and inputs / outputs the data signal DQ of the memory device ME2 as the higher data signal DQ-U. Conversely, when accessing the memory devices ME3 and ME4 of column 1, the memory interface MIF1 inputs / outputs the data signal DQ of the memory device ME3 as the lower data signal DQ-L, and inputs / outputs the data signal DQ of the memory device ME4 as the higher data signal DQ-U.

[0051] Similar to the memory interface MIF1, the memory interface MIF2 accesses the memory devices ME5 and ME6 of column 0 by using the common clock signal CK2 and the common chip select signal CS2. The memory interface MIF2 accesses the memory devices ME7 and ME8 of column 1 by using the common clock signal CK3 and the common chip select signal CS3. In addition, the memory interface MIF2 outputs the common command address signal CA to the memory devices ME5 to ME8 of columns 0 and 1.

[0052] When accessing the memory devices ME5 and ME6 of column 0, the memory interface MIF2 inputs / outputs the data signal DQ of the memory device ME5 as the lower data signal DQ-L, and inputs / outputs the data signal DQ of the memory device ME6 as the higher data signal DQ-U. Conversely, when accessing the memory devices ME7 and ME8 of column 1, the memory interface MIF2 inputs / outputs the data signal DQ of the memory device ME7 as the lower data signal DQ-L, and inputs / outputs the data signal DQ of the memory device ME8 as the higher data signal DQ-U.

[0053] The clock signal CK0 and the chip select signal CS0 are output simultaneously with the clock signal CK2 and the chip select signal CS2. Similarly, the clock signal CK1 and the chip select signal CS1 are output simultaneously with the clock signal CK3 and the chip select signal CS3. Therefore, in the relationship between the memory interface MIF2 and the memory devices ME5 to ME8, the clock signals CK2, CK3 and the chip select signals CS2, CS3 can be the clock signals CK0, CK1 and the chip select signals CS0, CS1, respectively.

[0054] For example, it is assumed here that the data signal DQ[k:0] is 8 bits, in other words, 1 byte. In this case, the control device CTL accesses Figure 1A the memory device ME in column 0 of Figure 1B by using the clock signal CK0 and the chip select signal CS0, thereby inputting / outputting a total of 32 bytes of data signals DQ-L and DQ-U. Similarly, the control device CTL accesses

[0055] <Schematic cross-sectional configuration of an electronic device>

[0056] Figure 4A is a cross-sectional view showing an exemplary schematic configuration of the clock signal and the chip select signal along the line A-A' of Figure 2 . Figure 4B is a cross-sectional view showing an exemplary schematic configuration of the clock signal and the chip select signal along the line B-B' of Figure 2 . The cross-sectional configuration along the line A-A' is divided into two figures for an understandable explanation of the configuration. The same applies to the cross-sectional configuration along the line B-B'.

[0057] In Figure 4A , the control device CTL includes a semiconductor chip CP and a package substrate PKG on which the semiconductor chip CP is mounted. The memory interface MIF1 formed on the semiconductor chip CP is connected to the package substrate PKG through the external terminals of the semiconductor chip CP. The memory interface MIF1 is connected to the external terminal PNc1 of the control device CTL through the internal wiring of the package substrate PKG.

[0058] The wiring substrate PCB includes a plurality of wiring layers sequentially stacked with an insulating layer therebetween in the Z-axis direction, wirings formed in each wiring layer, and a plurality of through-hole wirings VAt1 to VAt3 and VAb1 to VAb3. In this specification, the through-hole wirings are collectively referred to as through-hole wiring VA. In the gap between the front surface 20 and the rear surface 21 of the wiring substrate PCB, the through-hole wiring VA penetrates the wiring layers. The plurality of wirings formed in a predetermined wiring layer include a plurality of wirings WR1t and a plurality of wirings WR1b.

[0059] Through the wiring WR1t, the clock signal CK0 and the chip select signal CS0 propagated from the external terminal PNc1 through the through-hole wiring VAt1 are propagated to the memory devices ME1 and ME2 in column 0. At this time, the through-hole wiring VAt2 connects the wiring WR1t to the external terminal PNm of only the memory device ME1 among the memory devices ME1 and ME3. The through-hole wiring VAt3 connects the wiring WR1t to the external terminal PNm of only the memory device ME2 among the memory devices ME2 and ME4.

[0060] Conversely, through the wiring WR1b, the clock signal CK1 and the chip select signal CS1 propagated from the external terminal PNc1 through the through-hole wiring VAb1 are propagated to the memory devices ME3 and ME4 in column 1. At this time, the through-hole wiring VAb2 connects the wiring WR1b to the external terminal PNm of only the memory device ME3 among the memory devices ME1 and ME3. The through-hole wiring VAb3 connects the wiring WR1b to the external terminal PNm of only the memory device ME4 among the memory devices ME2 and ME4.

[0061] More specifically, the number of wirings WR1t for propagating the pair of clock signal CK0 and chip select signal CS0 is three. The same is true for the number of wirings WR1b. Similarly, the external terminal PNc1, the through-hole wirings VAt1 to VAt3, and the through-hole wirings VAb1 to VAb3 also provide as many signals as the signals.

[0062] Conversely, in Figure 4B the memory interface MIF2 formed on the semiconductor chip CP is connected to the package substrate PKG through the external terminals of the semiconductor chip CP. In addition, the memory interface MIF2 is connected to the external terminal PNc2 of the control device CTL through the internal wiring of the package substrate PKG. The memory interface MIF2 is formed closer to the inside of the semiconductor chip CP than Figure 4A the memory interface MIF1 of Figure 4A Therefore, the external terminal PNc2 is also arranged closer to the inside of the control device CTL than

[0063] In addition to the wiring layers and wirings, the printed circuit board (PCB) further includes a plurality of through-hole wirings VAt4 to VAt6 and VAb4 to VAb6. The plurality of wirings formed in a predetermined wiring layer include a plurality of wirings WR2t and a plurality of wirings WR2b. Through the wiring WR2t, the clock signal CK0 and the chip select signal CS0 propagated from the external terminal PNc2 through the through-hole wiring VAt4 are propagated to the memory devices ME5 and ME6 in column 0. At this time, the through-hole wiring VAt5 connects the wiring WR2t to the external terminal PNm of only the memory device ME5 among the memory devices ME5 and ME7. The through-hole wiring VAt6 connects the wiring WR2t to the external terminal PNm of only the memory device ME6 among the memory devices ME6 and ME8.

[0064] Conversely, through the wiring WR2b, the clock signal CK1 and the chip select signal CS1 propagated from the external terminal PNc2 through the through-hole wiring VAb4 are propagated to the memory devices ME7 and ME8 in column 1. At this time, the through-hole wiring VAb5 connects the wiring WR2b to the external terminal PNm of only the memory device ME7 among the memory devices ME5 and ME7. The through-hole wiring VAb6 connects the wiring WR2b to the external terminal PNm of only the memory device ME8 among the memory devices ME6 and ME8. Note that the specific number of the wiring WR2b etc. is similar to that in Figure 4A the like.

[0065] Figure 5 is a cross-sectional view schematically showing an exemplary configuration of command address signals along line A-A' of Figure 2 . Although not shown, the cross-sectional configuration along line B-B' is similar to that of Figure 5 . In Figure 5 , the memory interface MIF1 formed on the semiconductor chip CP is connected to the package substrate PKG through the external terminals of the semiconductor chip CP. Further, the memory interface MIF1 is connected to the external terminal PNc of the control device CTL through the internal wiring of the package substrate PKG. In addition to the wiring layers and wirings, the printed circuit board (PCB) further includes a plurality of through-hole wirings VA1 to VA3.

[0066] The plurality of wirings formed in a predetermined wiring layer include a plurality of wirings WR1tb. Through the wiring WR1tb, a plurality of command address signals CA propagated from the external terminal PNc through the through-hole wiring VA1 are propagated to the memory devices ME1 to ME4 in columns 0 and 1. At this time, the through-hole wiring VA2 commonly connects the wiring WR1tb to the external terminals PNm of the memory devices ME1 and ME3. The through-hole wiring VA3 commonly connects the wiring WR1tb to the external terminals PNm of the memory devices ME2 and ME4. More specifically, the number of the wiring WR1tb etc. is defined based on the number of the command address signals CA.

[0067] <Details of problems and comparative examples>

[0068] Figure 15A and Figure 15B are diagrams for schematically explaining exemplary problems in a typical electronic device. Figure 15A illustrates Figure 4A simplified components associated with column 0 in the exemplary configuration of Figure 15B illustrates Figure 15A an exemplary signal waveform propagating in the configuration of

[0069] For example, an electronic device such as a next-generation network processor may require broadband and large-capacity memory. Thus, as Figure 15A shown, the wiring WR for propagating control signals is branched into two pairs through via-through wiring VA, thereby connecting the same wiring WR to two memory devices ME1 and ME2. Thus, small-bit memories can be treated like large-bit memories, thereby achieving a wider memory bandwidth. Such a system is also called a flyover system.

[0070] However, by using a flyover system, a reflected signal SG2 reflected at a branch farther from the control device CTL overlaps with the input signal SG1 in the memory device ME1 arranged at a branch closer to the control device CTL, as Figure 15A and Figure 15B shown. Thus, the waveform integrity of the input signal "SG1 + SG2" entering the memory device ME1 arranged at a branch closer to the control device CTL is particularly reduced, and there is a risk of access errors to the memory device ME1 and the like.

[0071] To achieve a larger-capacity memory, two columns of memory devices ME separated by a chip select signal CS can be mounted on both surfaces of a wiring substrate PCB as Figure 4A shown, etc. Such a system is also called Clamshell. However, with recent complex systems, the number of wiring layers tends to be large, and the wiring substrate PCB tends to be thick. Thus, by using a Clamshell configuration, the length of each via-through wiring VA also increases. Thus, the magnitude of the reflected signal SG2 may further increase, and the waveform integrity may be further reduced.

[0072] Thus, as Figure 15AAs shown, a resistor device Rd as a damping resistor can be serially inserted into a wiring near an external terminal PNm of a memory device ME1 disposed at a branch closer to a control device CTL. Thereby, a reflected signal SG2 generated at a branch farther from the control device CTL is attenuated before being input into the memory device ME1 disposed at a branch closer to the control device CTL. However, the resistor device Rd attenuates not only the reflected signal SG2 but also a normal input signal SG1. That is, there is a trade-off relationship between the attenuation of the normal input signal SG1 and the attenuation of the reflected signal SG2.

[0073] The attenuation of the normal input signal SG1 represents power waste. If there are as many resistor devices Rd as signals, as Figure 15A shown, the mounting area in a wiring substrate PCB may increase, and it may be difficult for electronic devices to reduce their size. In addition, the mounted resistor devices Rd may increase the cost of components and the like. Therefore, it is desirable to improve waveform integrity without providing the resistor device Rd. Through-hole wiring VA causes signal reflection due to impedance mismatch and attenuates the transmitted signal as much as the reflection. It is also desirable to minimize signal attenuation as much as possible.

[0074] Figure 16 is a diagram illustrating an exemplary waveform of a clock signal CK input by Figure 15A two memory devices ME1 and ME2 in

[0075] Another problem is that signal reflection is repeated at a branch point by using a flyover system, resulting in waveforms of the clock signal CK input by the memory device ME1 and the clock signal CK input by the memory device ME2 being asymmetrical with each other. This is because the amount and timing of the combined reflected signals are different between the side closer to the control device CTL and the side farther from the control device CTL. Figure 16 For example, in Figure 16 it is desirable that the waveform of the negative-polarity clock signal CK(c) input into the memory device ME1 and the waveform of the positive-polarity clock signal CK(t) input into the memory device ME2 are equal to each other. However, in

[0076] Figure 17A is a cross-sectional view illustrating an exemplary configuration of an electronic device in a comparative example different from Figure 4A Figure 17B is a cross-sectional view illustrating an exemplary configuration of an electronic device in a comparative example different from Figure 4B Figure 17A and Figure 17B ​​Illustrated is an exemplary configuration based on a typical idea. For example, when wiring is led out from a control device CTL mounted on the front surface 20 of a wiring substrate PCB, generally, the wiring led out from the end of the control device CTL is assigned to a wiring layer closer to the front surface, while the wiring led out from the inside of the control device CTL is assigned to a wiring layer closer to the back surface. Thus, the wiring can be configured such that the wiring led out from the end of the control device CTL does not obstruct the wiring led out from its inside.

[0077] Based on this idea, when the memory interfaces MIF1 and MIF2 are arranged as Figure 2 shown, the wiring WR1 led out from the memory interface MIF1 at the end of the device is assigned to a wiring layer closer to the front surface. Conversely, the wiring WR2 led out from the memory interface MIF2 arranged inside the device is assigned to a wiring layer closer to the back surface. That is, the wiring layer to be assigned is defined by the positions of the memory interfaces MIF1 and MIF2.

[0078] Therefore, in the example of Figure 17A , both the wiring WR1t and the wiring WR1b are assigned to the wiring layer 15 closer to the front surface. Similar to the case of Figure 4A , through the wiring WR1t, the clock signal CK0 and the chip select signal CS0 are propagated from the memory interface MIF1 to the memory devices ME1 and ME2 in column 0. Through the wiring WR1b, the clock signal CK1 and the chip select signal CS1 are propagated from the memory interface MIF1 to the memory devices ME3 and ME4 in column 1.

[0079] Conversely, in the example of Figure 17B , both the wiring WR2t and the wiring WR2b are assigned to the wiring layer 16 closer to the back surface. Similar to the case of Figure 4B , through the wiring WR2t, the clock signal CK0 and the chip select signal CS0 are propagated from the memory interface MIF2 to the memory devices ME5 and ME6 in column 0. Through the wiring WR2b, the clock signal CK1 and the chip select signal CS1 are propagated from the memory interface MIF2 to the memory devices ME7 and ME8 in column 1.

[0080] For example, when paying attention to the signal paths of the chip select signals CS0 and CS1 in Figure 17A , the length of the through-hole wiring VA passing through along the signal path is different between the access to column 0 and the access to column 1. Specifically, the through-hole wiring VAt3 for the connection to the memory device ME2 in column 0 includes a through-hole segment SBt1 for signal propagation and an open stub SBo1.

[0081] The through - via segment SBt1 for signal propagation is a through - via segment for propagating a signal to the target memory device ME. The through - via segment SBt1 for signal propagation is formed by the portion between the connection point with the wiring WR1t and the front surface 20 of the wiring substrate PCB. Meanwhile, the open - circuit stub SBo1 is a stub having an open - end. The open - circuit stub SBo1 described here is formed by the portion between the connection point with the wiring WR1t and the back surface 21 of the wiring substrate PCB.

[0082] Similarly, the through - via wiring VAb3 for connection to the memory device ME4 in column 1 also includes a through - via segment SBt2 for signal propagation and an open - circuit stub SBo2. Contrary to the through - via wiring VAt3, the through - via segment SBt2 for signal propagation is formed by the portion between the connection point with the wiring WR1b and the back surface 21 of the wiring substrate PCB. Conversely, the open - circuit stub SBo2 is formed by the portion between the connection point with the wiring WR1b and the front surface 20 of the wiring substrate PCB.

[0083] When accessing column 0, the length of the through - via segment SBt1 for signal propagation is "h1". On the contrary, when accessing column 1, the length of the through - via segment SBt2 for signal propagation is "h2" which is greater than "h1". In other words, when the length of the open - circuit stub SBo1 is "h2", the length of the open - circuit stub SBo2 is "h1" which is less than "h2".

[0084] Similarly, in Figure 17B it is similar to the case of Figure 17A In between the access to column 0 and the access to column 1, the length of the through - via wiring VA along the signal path is different. That is, the length of the through - via segment SBt1 for signal propagation in the through - via wiring VAt6 for accessing column 0 is "h2". On the contrary, the length of the through - via segment SBt2 for signal propagation in the through - via wiring VAb6 for accessing column 1 is "h1" which is less than "h2". This has been described in the exemplary signal paths of the chip - select signals CS0 and CS1. However, the same is true for the signal paths of the clock signals CK0 and CK1.

[0085] As described above, if the length of the through - via wiring VA along the signal path is different between the access to column 0 and the access to column 1, then as Figure 15A and Figure 15BThe waveforms of the reflected signals shown are different between the access to column 1 and the access to column 0. Therefore, the signals reaching the memory devices ME on the front surface and the back surface are asymmetric with respect to each other. This may lead to a reduction in the operating margin when accessing the memory devices ME. This is because the overall operating margin is defined based on the poorer waveform integrity. The reduction in the operating margin may cause errors when accessing the memory devices ME.

[0086] The chip select signal CS is particularly important for the switching between column 0 and column 1, and therefore, it is desirable to increase the operating margin by improving the waveform integrity (such as signal symmetry). This is expected to result in zero errors when accessing the memory devices ME. In addition, the clock signal CK is also important for determining the signal timing, and therefore, it is desirable to improve the waveform integrity such as signal symmetry.

[0087] <Details of the electronic device (embodiment)>

[0088] Using Figure 4A and Figure 4B The exemplary configuration of is beneficial. Figure 4A and Figure 4B The exemplary configuration of is different from that of Figure 17A and Figure 17B in the following two points. The first difference is that, Figure 4A and Figure 4B The wirings WR1t, WR1b, WR2t, and WR2b for propagating the clock signal CK and the chip select signal CS are assigned to the wiring layers by a method different from that of Figure 17A and Figure 17B . The second difference is that, Figure 4A and Figure 4B The distance between two adjacent memory devices ME is determined to be a predetermined value for each column.

[0089] <<Method of assigning to the wiring layer>>

[0090] For the first difference, in the exemplary configuration of Figure 4A , the wiring WR1t from the memory interface MIF1 to the memory devices ME1 and ME2 in column 0 is provided in the wiring layer 15 closer to the front surface of the wiring layer, in other words, the wiring layer is closer to the front surface 20 than the back surface 21. On the contrary, the wiring WR1b from the memory interface MIF1 to the memory devices ME3 and ME4 in column 1 is provided in the wiring layer 16 closer to the back surface of the wiring layer, in other words, the wiring layer closer to the back surface 21 than the front surface 20.

[0091] With Figure 4BThe exemplary configuration is similar. The wiring WR2t from the memory interface MIF2 to the memory devices ME5 and ME6 in column 0 is provided in the wiring layer 15 closer to the front surface. In contrast, the wiring WR2b from the memory interface MIF2 to the memory devices ME7 and ME8 in column 1 is provided in the wiring layer 16 closer to the rear surface. In this way, in Figure 4A and Figure 4B , the wiring layer is determined based on the arrangement of the memory devices ME, rather than the arrangement of the memory interfaces MIF1 and MIF2. In other words, it is determined based on the column, which is different from Figure 17A and Figure 17B .

[0092] Together with this configuration, Figure 4A in the through-hole wirings VAt3 and VAb3 shown, the lengths "h1" of the through-hole segments SBt1 and SBt2 for signal propagation are less than the lengths "h2" of the open stubs SBo1 and SBo2. Similarly, Figure 4B in the through-hole wirings VAt6 and VAb6 shown, the lengths "h1" of the through-hole segments SBt1 and SBt2 for signal propagation are less than the lengths "h2" of the open stubs SBo1 and SBo2.

[0093] That is to say, in Figure 4A and Figure 4B , the through-hole segments SBt1 and SBt2 for signal propagation are configured to be shorter, regardless of whether accessing column 0 or column 1. In this specification, the through-hole segments SBt1 and SBt2 for signal propagation are collectively referred to as the through-hole segments SBt for signal propagation. The open stubs SBo1 and SBo2 are collectively referred to as the open stubs SBo.

[0094] The effects provided by this configuration are the reduction of the load capacitance in the through-hole segments SBt for signal propagation, and thus the reduction of the reflected signal and the improvement of the integrity of the transmitted signal. The clock signal CK and the chip select signal CS only propagate to the memory devices ME mounted on the front surface 20 or the rear surface 21. Therefore, each through-hole wiring VA for signal propagation definitely includes an open stub SBo.

[0095] Figure 6 is the impedance diagram showing the exemplary impedance characteristics of the through-hole segments SBt for signal propagation and the open stubs SBo in Figure 4A and Figure 4B . As Figure 6As shown in the impedance diagram of the Smith chart, the impedance of the open stub SBo is infinite when its length is zero, or zero when its length is one - quarter of the wavelength λ of the propagating signal. The longer the length of the open stub SBo, or the higher the frequency of the propagating signal, the greater the range of clockwise rotation of the characteristic points on the outer periphery of the diagram. The impedance decreases accordingly.

[0096] Conversely, for example, when it is assumed that the input terminal of the memory device ME is terminated at 50Ω through die termination (ODT), the impedance of the via - through segment SBt for signal propagation is 50Ω when its length is zero. Conversely, if the via - through segment SBt for signal propagation has a finite length, the input capacitance of the memory device ME and the coupling capacitance with the printed circuit board PCB act as parallel capacitances and act as a kind of stub. The coupling capacitance increases by increasing the length of the via - through segment SBt for signal propagation. Therefore, by increasing the length of the via - through segment SBt or increasing the frequency of the propagating signal, the characteristic points of the via - through segment BSt for signal propagation rotate clockwise on the constant - conductance circle from the 50Ω point. The impedance decreases accordingly.

[0097] Considering this characteristic, when the length of the open stub SBo is sufficiently less than λ / 4, the relationship of Expression (1) is established for the via - through wiring VA per unit length. Conversely, when the length of the open stub SBo approaches λ / 4 due to an increase in the frequency of the propagating signal, the open stub SBo is converted into a short - circuit stub and rapidly has a large capacitance. Therefore, the relationship of Expression (1) is reversed to the relationship of Expression (2).

[0098] Capacitive load of SBo < Capacitive load of SBt (1)

[0099] Capacitive load of SBo > Capacitive load of SBt (2)

[0100] The conflicting Expressions (1) and (2) indicate that when the length of the open stub SBo is sufficiently less than λ / 4, in the case of a longer open stub SBo and a shorter via - through segment SBt for signal propagation, signal reflection can be reduced, thereby improving signal transmission performance. That is, as Figure 6 shown, when the length of the open stub SBo is sufficiently less than 1 / 4, the impedance of the open stub SBo is sufficiently higher than the impedance of the via - through segment SBt for signal propagation. Therefore, the reflection characteristics at the branch point are mainly defined by the capacitive characteristics of the via - through segment SBt for signal propagation. When the via - through segment SBt for signal propagation is shortened, the impedance can be closer to 50Ω, thereby reducing the reflected signal.

[0101] In this way, considering λ / 4, it is important to shorten the length of the open stub SBo to at least less than λ / 4.Figure 7 This is a diagram showing the exemplary calculation results of how much the quarter - wavelength of the propagation signal λ depends on the Nyquist frequency. It shows the calculation results assuming that the relative dielectric constant ε of the dielectric material for manufacturing the wiring substrate PCB is r 4.0. Note that the Nyquist frequency is equal to the clock frequency in DDR5_SDRAM. When the highest Nyquist frequency applicable to DDR5_SDRAM is 3.6 GHz, the quarter - wavelength of the wavelength λ is approximately 10.4 mm.

[0102] Conversely, the thickness of the wiring substrate PCB is typically about 1.0 to 4.0 mm. Therefore, at a Nyquist frequency of 3.6 GHz, the length of the open - circuit stub SBo is sufficiently less than λ / 4, that is, 10.4 mm. At a Nyquist frequency of 8.0 GHz, the quarter - wavelength of the wavelength λ is 4.7 mm. Even in this case, the length of the open - circuit stub SBo is less than λ / 4, that is, 4.7 mm. That is to say, unless an extremely thick wiring substrate PCB is used, it can be said that Expression (1) holds until the signal propagation speed exceeds about 16 Gbps.

[0103] Therefore, as Figure 4A and Figure 4B shown, it is beneficial to shorten the length of the through - via segment SBt for signal propagation, especially in the electronic device 10 on which memory devices ME such as DDR5_SDRAM are mounted. Therefore, the total load capacity of the through - via wiring VA is minimized, the reflected signal is reduced, and the transmitted signal is increased. Therefore, the waveform integrity can be improved.

[0104] The distance between memory devices

[0105] For the second difference, in the exemplary configuration of Figure 4A , the distance Lm between the memory device ME1 in column 0 and the memory device ME2 is defined based on the propagation delay time given by Expression (3). That is, the distance Lm is defined based on the wiring length of the wiring WR1 corresponding to the propagation delay time given by Expression (3). The term "Tck" in Expression (3) is the period of the clock signal CK. The distance Lm between the memory device ME3 in column 1 and the memory device ME4 is also defined based on the propagation delay time given by Expression (3). Figure 4B The exemplary configuration of Figure 4A is also similar to the configuration of

[0106] Lm = Tck / 2 (3)

[0107] More preferably, the distance Lm between two memory devices ME adjacent to each other is defined based on the propagation delay time given by Expression (4). The term "τ" in Expression (4) va " is the propagation delay time of the through-via segment SBt for signal propagation and is given by Expression (5). The term "ε" in Expression (5) r " is the relative dielectric constant of the dielectric material for manufacturing the wiring substrate PCB. The term "c0" is the speed of light in a vacuum. Note that the distance Lm between the two memory devices ME is also the distance between two through-via wirings VA through which the same signal propagates, such as Figure 4A the distance between the through-via wiring VAt2 and the through-via wiring VAt3 in

[0108] Lm = Tck / 2 - τ va (4)

[0109] τ va =(length of SBt)×√(ε r ) / c0(5)

[0110] By applying such a distance, the reflected signal can be eliminated as described below. However, in practice, it is not easy to completely eliminate the reflected signal. Therefore, it is also beneficial to use a method of allocating to the wiring layer. That is, it is desirable to pre-reduce the reflected signal by the method of allocating to the wiring layer.

[0111] Figure 8A is a circuit diagram showing an exemplary equivalent configuration of the signal propagation path to column 0 in Figure 4A . Figure 8B is a timing diagram conceptually showing the mechanism for eliminating the reflected signal in Figure 8A . In Figure 8A , a transmission line LN3 corresponding to the wiring WR1 for propagating the chip select signal CS is provided between two memory devices ME1 and ME2. The propagation delay time of the transmission line LN3 is defined by Expression (3).

[0112] A branch node N1 at one end of the transmission line LN3 is connected to the receiver RV of the memory device ME1 through a transmission line LN1 corresponding to the through-via segment SBt for signal propagation. In addition, the branch node N1 leads to an open end through a transmission line LN2 corresponding to the open stub SBo. Similarly, a branch node N2 at the other end of the transmission line LN3 is connected to the receiver RV of the memory device ME2 through a transmission line LN4 corresponding to the through-via segment SBt for signal propagation. In addition, the branch node N2 leads to an open end through a transmission line LN5 corresponding to the open stub SBo.

[0113] Figure 8BIt illustrates the clock signal CK, the chip select signal CS and the reflected signals CSr1, CSr2 at the branch node N1, and the chip select signal CS and the reflected signal CSr2 at the branch node N2. The clock signal CK and the chip select signal CS are signals output from the slave control device CTL (not shown). The reflected signal CSr1 is the reflected signal of the chip select signal CS reflected on the branch node N1. The reflected signal CSr2 is the reflected signal of the chip select signal CS reflected on the branch node N2. In this example, for simplicity of explanation, it is assumed that the phase component of the reflection coefficient at the branch nodes N1 and N2 is zero.

[0114] In Figure 8B it, a reflected signal CSr1 having the same phase as the chip select signal CS is generated at the branch node N1. On the contrary, the chip select signal CS passing through the branch node N1 is delayed by "Tck / 2" and reaches the branch node N2. Therefore, a reflected signal CSr2 is also generated at the branch node N2, which is similar to the case of the branch node N1. The reflected signal CSr2 is delayed by "Tck / 2" and returns to the branch node N1.

[0115] After the reflected signal CSr2 reaches the branch node N1, a reflected signal CSr1 having a polarity different from the previous polarity is generated at the branch node N1. The reflected signals CSr1 with different polarities and the reflected signal CSr2 output from the branch node N2 cancel each other out at the branch node N1. In fact, the reflection coefficients at the branch nodes N1 and N2 have a phase component, that is, a reactance component. Therefore, the reflected signal is mainly generated during the rising / falling period of the chip select signal CS and has a different phase from the chip select signal CS. Even in this case, as long as the magnitudes and phases of the reflection coefficients between the two branch nodes N1 and N2 are the same, a mechanism similar to Figure 8B is established.

[0116] As described above, when the expression (3) is satisfied, the reflection of the chip select signal CS operating in the single data rate (SDR) mode can be eliminated at the branch node N1. The SDR mode is an operation mode that regards the period Tck of the clock signal CK as one data unit. Therefore, in the memory device ME1 arranged at the branch closer to the control device CTL, the waveform integrity can be improved, as shown in Figure 15A and Figure 15B shown.

[0117] When a signal is reflected on the via-through wiring VA, strictly speaking, a reflection with zero delay is not caused at the connection point between the wiring and the via-through wiring VA, but a reflection is caused such that the signal returns to the original direction to some extent after entering the via-through wiring VA. Therefore, more strictly speaking, it is necessary to consider the intrusion delay at this time to determine the propagation delay time between the two memory devices ME. The intrusion delay is reflected in the propagation delay time τ in expressions (4) and (5). va above.

[0118] The round-trip delay time in the via-through wiring VA can be approximated by the typical relaxation time given by expression (6), where "e" is the base of the natural logarithm. The delay time per unit length in the via-through wiring VA is generally longer than that of the wiring, and is almost 1.3 to 1.4 times that of the wiring, although strictly speaking it depends on the layout. Therefore, substituting with the ordinary signal delay in expression (6) gives expression (7).

[0119] (Via-through delay) × (1 / e) × 2 (6)

[0120] (Ordinary signal delay) × (1.3 to 1.4) × (2 / e)

[0121] = (Ordinary signal delay) × (0.96 to 1.03) (7)

[0122] As described above, the round-trip delay time in the via-through wiring VA is almost equal to the one-way delay time in the ordinary signal wiring. By reflecting the result, expressions (4) and (5) are provided. If the wiring layer changes, the magnitude of the intrusion delay also changes, and thus the degree of canceling the effect of the reflected signal also changes slightly. However, as described later, the propagation delay time for defining the distance Lm has a certain margin for delay changes, such as 14%. Therefore, it does not particularly cause a big problem. Due to this margin, the distance Lm given by expression (3) instead of expression (4) can be applied.

[0123] <Clock signal>

[0124] By applying the distance Lm between the memory devices ME and / or applying the method of allocating the wiring layer, waveform integrity such as Figure 16 the waveform symmetry of the clock signal CK as shown can be improved. Specifically, when expressions (3) or (4) are established, the round-trip delay time of the clock signal CK between the memory devices ME is equal to the period of the clock signal CK. Therefore, for example, in Figure 4A the memory devices ME1 and ME2 in column 0 as shown, almost equal amounts of reflected signals are combined at a constant timing.

[0125] Therefore, a clock signal CK having a symmetric waveform can be input to memory devices ME1 and ME2 to which a flyover system is applied. In addition, for example, the method of allocating to wiring layers is also applied to Figure 4A Memory device ME1 and memory device ME3 on the front surface 20 and the rear surface 21 to which Clamshell is applied, thereby equalizing the reflection coefficients at branch nodes corresponding to the respective memory devices ME. Therefore, a clock signal CK having almost the same waveform can be input to memory devices ME1 and ME3.

[0126] In this regard, for example, in Figure 4A The length of the through-via segment SBt1 for signal propagation for propagating clock signal CK0 is equal to the length of the through-via segment SBt2 for signal propagation for propagating clock signal CK1. The same applies to the chip select signal CS. Therefore, the length of the through-via segment SBt1 for signal propagation for propagating chip select signal CS0 is equal to the length of the through-via segment SBt2 for signal propagation for propagating chip select signal CS1. That is, wirings WR1t and WR1b for propagating the same type of signal can be arranged symmetrically with respect to the intermediate wiring layer in the wiring substrate PCB.

[0127] <Command address signal>

[0128] As Figure 5 etc. show, the wiring WR1tb for propagating the command address signal CA is commonly connected to memory devices ME1 and ME3 on the front surface 20 and the rear surface 21. This does not result in the effect of reducing the capacitance in the through-via wiring VA, that is, the effect provided by the method of allocating to wiring layers. However, this results in the effect of canceling reflected signals, that is, the effect provided by the distance Lm between the memory devices ME.

[0129] For example, "2N mode" is supported for the command address signal CA in DDR5_SDRAM. The 2N mode is an operation mode in which two cycles "2×Tck" of the clock signal CK are regarded as one unit, as Figure 8B shown. In the 2N mode, the effect of canceling reflected signals is slightly different from the effect of the chip select signal CSm operating in the SDR mode. That is, in the 2N mode, for every two round trips of the command address signal CA between two memory devices ME, the phases of the reflected signals are opposite.

[0130] In Figure 8BIn the example, note that in response to the command address signal CA, the reflected signal CSr2 caused at the first cycle of the clock signal CK and the reflected signal CSr1 caused at the third cycle of the clock signal CK are canceled. Therefore, as long as the reflection continues, for every even number of round trips of the command address signal CA, such as two round trips, four round trips, and six round trips, the phase-inverted reflected signals will cancel each other out. Odd-numbered round trips do not result in cancellation, and thus, the effect of canceling the reflected signal is almost half of the chip select signal CS.

[0131] The margin of error in the command address signal CA is greater than the margins of error in the chip select signal CS and the clock signal CK. In addition, since using the 2N mode increases the timing margin, etc., errors are less likely to occur. Therefore, in particular, by using the 2N mode, the required waveform integrity of the command address signal CA can be fully achieved.

[0132] <Simulation Results>

[0133] Figure 9 is a waveform diagram showing exemplary simulation results for Figure 4A the memory device ME1 closer to the control device in, and the simulation results are obtained by observing the input waveform of the chip select signal CS. Here, assuming a signal propagation speed of 5600 Mbps, the distance Lm between the two memory devices ME1 and ME2 is determined based on Expression (4) and defined as the optimal value. While maintaining the distance Lm between the memory devices ME1 and ME2, the signal propagation speed is changed to 4800 Mbps and 3200 Mbps.

[0134] Therefore, at a signal propagation speed of 4800 Mbps, the distance Lm between the memory devices ME1 and ME2 is approximately 14.3% shorter than the optimal value. Similarly, at a signal propagation speed of 3200 Mbps, the distance Lm between the memory devices ME1 and ME2 is approximately 42.9% shorter than the optimal value.

[0135] In Figure 9 , at 5600 Mbps and 4800 Mbps, the reflected signals are almost removed, and an excellent waveform of the chip select signal CS, i.e., an eye diagram, is provided. On the contrary, at 3200 Mbps, the reflected signals are not canceled and are not clearly observed. However, due to the use of the method of allocating to the wiring layer, the size of the reflected signals is small. It can be found from the simulation results that even if the distance Lm between the memory devices ME1 and ME2 is offset by approximately 14%, excellent effects can be provided. If the optimal value of the distance Lm is defined based on a specific signal propagation speed as described above, this effect may become smaller when the signal propagation speed decreases.

[0136] Figure 10 is a waveform diagram showing exemplary simulation results for a memory device ME1 closer to the control device CTL and a memory device ME2 farther from the control device CTL in Figure 4A , and the simulation results are obtained by observing the input waveform of the clock signal CK. In this case, the evaluation metric is the waveform symmetry as described in Figure 16 .

[0137] At a signal propagation speed of 5600 Mbps, waveforms with sufficient symmetry are provided in the relationship between the clock signal CK entering the memory device ME1 and the clock signal CK entering the memory device ME2. That is, the waveforms of the negative-polarity clock signal CK(c) and the positive-polarity clock signal CK(t) entering the memory device ME1 are equal to the waveforms of the positive-polarity clock signal CK(t) and the negative-polarity clock signal CK(c) entering the memory device ME2.

[0138] Even at a signal propagation speed of 4800 Mbps, waveforms with substantially symmetry are provided. On the contrary, at a signal propagation speed of 3200 Mbps, the waveforms are asymmetric. It can be found from the simulation results that the margin of the distance Lm between the two memory devices ME is about 14%, which is similar to the margin of the chip select signal CS.

[0139] <Detailed cross-sectional configuration of the electronic device (Embodiment)>

[0140] Figure 11A is a cross-sectional view showing a detailed exemplary configuration along the line A-A' of Figure 2 . As shown in Figure 4A , Figure 11A shows that in the wiring layer 15 closer to the front surface 20, there are provided a wiring WR1 for propagating the chip select signal CS0 toward the front surface 20 and a wiring WR1 for propagating the clock signal CK0 toward the front surface 20. On the contrary, in the wiring layer 16 closer to the rear surface 21, there are provided a wiring WR1 for propagating the chip select signal CS1 toward the rear surface 21 and a wiring WR1 for propagating the clock signal CK1 toward the rear surface 21. The external terminal PNc2 of the memory interface MIF2 is closer to the inside of the control device CTL than the external terminal PNc1 of the memory interface MIF1.

[0141] In this case, for example, the lengths of the signal-propagating through-hole segments SBt1k for propagating the clock signal CK0 toward the front surface 20 and the signal-propagating through-hole segments SBt2k for propagating the clock signal CK1 toward the rear surface 21 both have the same value "h1k". Similarly, the lengths of the signal-propagating through-hole segments SBt1s for propagating the chip select signal CS0 toward the front surface 20 and the signal-propagating through-hole segments SBt2s for propagating the chip select signal CS1 toward the rear surface 21 both have the same value "h1s".

[0142] The wirings WR1 through which the command address signals CA[i:0] propagate are connected in a "wired OR" form to all of the memory devices ME1 to ME4 mounted on the front surface 20 and the rear surface 21. A single wiring WR1 is shown here. However, specifically, "i + 1" wirings WR1 are provided. The "i + 1" wirings WR1 can be appropriately distributed in the wiring layer.

[0143] In this example, eight wirings WR1 through which the 8-bit data signal DQ[7:0] propagates to one of the two memory devices ME1 and ME3, and eight wirings WR1 through which the 8-bit data signal DQ[15:8] propagates to one of the two memory devices ME2 and ME4 are provided. The total of 16 wirings WR1 through which the data signal DQ[15:0] propagates can also be appropriately distributed in the wiring layer.

[0144] Figure 11B is a cross-sectional view showing a detailed exemplary configuration along the Figure 2 line B-B'. As Figure 4B shown, in Figure 11B the wiring layer 15 closer to the front surface 20, there are provided the wirings WR2 through which the chip select signal CS0 propagates toward the front surface 20 and the wirings WR2 through which the clock signal CK0 propagates toward the front surface 20. Conversely, in the wiring layer 16 closer to the rear surface 21, there are provided the wirings WR2 through which the chip select signal CS1 propagates toward the rear surface 21 and the wirings WR2 through which the clock signal CK1 propagates toward the rear surface 21. As Figure 4B shown, Figure 11B shows that in the wiring layer 15 closer to the front surface 20, there are provided the wirings WR2 through which the chip select signal CS0 propagates toward the front surface 20 and the wirings WR2 through which the clock signal CK0 propagates toward the front surface 20. Conversely, in the wiring layer 16 closer to the rear surface 21, there are provided the wirings WR2 through which the chip select signal CS1 propagates toward the rear surface 21 and the wirings WR2 through which the clock signal CK1 propagates toward the rear surface 21. The lengths of the signal-propagating through-hole segments are the same asFigure 11A are similar in length.

[0145] With Figure 11A Similar to Figure 11A , the "i + 1" wirings WR2 through which the command address signal CA[i:0] propagates can also be appropriately distributed in the wiring layer. In this example, there are provided 8 wirings WR2 through which the 8-bit data signal DQ[23:16] propagates to one of the two memory devices ME5 and ME7, and 8 wirings WR2 through which the 8-bit data signal DQ[31:24] propagates to one of the two memory devices ME6 and ME8. The total 16 wirings WR2 through which the data signal DQ[31:16] propagates can also be appropriately distributed in the wiring layer.

[0146] <Modified Example>

[0147] Figure 12 is a cross-sectional view of an exemplary configuration of an extended configuration shown in Figure 4A In Figure 12 , an even number of memory devices (here, four memory devices ME including the memory devices ME1 and ME2 including Figure 4A ) are mounted on the front surface 20 of the wiring substrate PCB. The even number of memory devices ME form column 0 and are accessed by using a common clock signal CK0 and a common chip select signal CS0.

[0148] Similarly, an even number of memory devices (here, four memory devices ME including the memory devices ME3 and ME4 including Figure 4A ) are mounted on the back surface 21 of the wiring substrate PCB. The even number of memory devices ME form column 1 and are accessed by using a common clock signal CK1 and a common chip select signal CS1.

[0149] The distance Lm between two adjacent memory devices ME among the even number of memory devices ME mounted on the front surface 20 is defined based on the propagation delay time given by Expression (3) or Expression (4). Similarly, the distance Lm between two adjacent memory devices ME among the even number of memory devices ME mounted on the back surface 21 is also defined based on the propagation delay time given by Expression (3) or Expression (4).

[0150] When using the flyover system as described above, the number of branches can be increased to two or more. In this case, as Figure 12As shown, memory devices ME adjacent to each other can be arranged at equal intervals. However, the number of memory devices ME installed on each surface needs to be an even number. If an odd number of memory devices ME are installed, in some combinations of the memory devices ME, the reflected signals can enhance each other. Note that the bit widths of the data signals DQ in the memory interfaces MIF1 and MIF2 are generally extended in units of 2 n Therefore, even in this regard, the number of memory devices ME installed on each surface can generally be an even number.

[0151] <Principal effects of the first embodiment>

[0152] As described above, in the first embodiment, a method for allocating the routing through which the chip select signal and the clock signal propagate to the wiring layer and the distance between adjacent memory devices is mainly defined. The electronic device according to the first embodiment employs at least one of these two technical elements, or preferably both. Therefore, the waveform integrity of the chip select signal and the clock signal is generally improved. In addition, the waveform integrity can be improved without providing the resistor device described in Patent Document 1. Therefore, the size of the electronic device can be reduced.

[0153] (Second embodiment)

[0154] <Schematic cross-sectional configuration of the electronic device>

[0155] Figure 13 is a cross-sectional view illustrating an exemplary schematic configuration of a clock signal, a chip select signal, and a command address signal along line A-A' in the electronic device according to the second embodiment. Figure 2 The figure illustrates a configuration similar to Figure 13 illustrates a configuration similar to Figure 4A and Figure 5 Similar configurations. Figure 13 Differences from Figure 4A and Figure 5 are that the wiring length LLc between the external terminal PNc for outputting a predetermined control signal from the control device CTL and the via wirings Vat2, VAtb2 for propagating the predetermined control signal to the memory devices ME1, ME3 closer to the control device CTL is defined as a predetermined value.

[0156] Specifically, the wiring length LLc is defined based on the propagation delay time given by Expression (8). That is, the wiring length LLc indicates the wiring length of the wirings WR1t, WR1b, WR1tb corresponding to the propagation delay time. The term "Tck" in Expression (8) is the period of the clock signal CK. The terms "n" and "m" are integers other than negative integers. The term "τ va” is the propagation delay time of the through - via segment SBt for signal propagation described in Expression (5). Note that the term “τ” in Expression (8) va ” can be zero, which is similar to the relationship between Expression (3) and Expression (4).

[0157] LLc = (Tck / 2)(n + m / 6) - τ va (8)

[0158] Figure 14 is a table of combinations of “n” and “m” that should be avoided for the wiring length LLc between the control device CTL and the memory device ME1 shown in Figure 13 . In Figure 14 , the priorities are set in descending order of the impact on waveform integrity. In Figure 14 , it is assumed that the command address signal CA is in the 2N operation mode, and the limitations in the 2N mode are shown. If the command address signal CA operates in the SDR mode, the rules of the chip - select signal CS should be followed.

[0159] In the first embodiment, the reflected signals can specifically affect not only between adjacent memory devices ME but also between the control device CTL and the memory device ME. That is, the through - via wirings VAt1 and VAtb1 also exist closer to the control device CTL, and thus, the reflected signals from the through - via wirings VAt1 and VAtb1 will affect the effect of canceling the reflected signals described in the first embodiment.

[0160] At this time, due to the arrival of the signals that are not eliminated but retained between the memory devices ME, reflected signals from the through - via wirings VAt1 and VAtb1 closer to the control device CTL are caused. Therefore, signals other than the clock signal CK are less affected. Considering this, in Figure 14 , the priorities of signals other than the clock signal CK are set to be lower.

[0161] In this case, even without a branch to the memory device ME, the waveform integrity of the clock signal CK may be affected by the wiring length, more precisely, by the remainder obtained by dividing the delay by half of the clock period. Therefore, the present inventors studied the influence of the wiring delay under a simulation with a resolution of 1 / 6 of half of the period “Tck / 2” of the clock signal CK. Thus, as Figure 14 shows, at “m = 4”, it is observed that the waveform integrity tends to decrease, especially the high - frequency components tend to decrease.

[0162] For example, in Expression (8), "m = 2" and "m = 4" are timings that are symmetric with respect to "3 / 6" corresponding to the center timing of the clock signal CK and represent equivalent conditions. However, for example, in an actual clock driver circuit included in a memory interface, the rising waveform and the falling waveform of the clock signal CK may be asymmetric with respect to each other, and thus, "m = 2" or "m = 4" are conditions to be avoided. That is, the timing in the clock driver circuit under simulation is exactly "m = 4".

[0163] As described in the first embodiment, by applying the distance Lm between the two memory devices ME, a symmetric waveform is provided for the clock signal CK observed at the input terminals of the two memory devices ME. By observing the waveform of the chip select signal CS operating in the SDR mode under simulation, at "n = 0" and "m = 3" where the wiring length LLc is short, only a slight reduction in waveform integrity is observed, as Figure 14 shown.

[0164] In contrast, the command address signal CA operates in the 2N mode, and thus the results are slightly different. As described above, for every two round trips between the two memory devices ME, the reflected signals in the 2N mode are canceled. Here, it is assumed that Figure 13 the wiring length LLc is twice the distance Lm between the two memory devices ME, in other words, the conditions of "n = 2" and "m = 0" in Expression (8) are assumed.

[0165] By using the wiring length LLc, similar to the condition of the chip select signal CS, the condition for canceling the reflected signal in the command address signal CA is also satisfied. That is, in one unit of a round trip of the command address signal CA, the reflected signal is additionally canceled between the control device CTL and the memory device ME1 closer to it. Therefore, the waveform integrity is slightly improved. The same phenomenon is also provided for the signal offset in one unit of a cycle, and thus, the condition for canceling the reflected signal is satisfied at "n = (even number)" and "m = 0". That is, the optimal condition is at "n = (even number) and "m = 0".

[0166] Then, it is assumed that Figure 13The wiring length LLc is equal to the distance Lm between the two memory devices ME of the command address signal CA. In other words, the conditions of "n = 1" and "m = 0" in the expression (8) are assumed. By using the wiring length LLc, between the control device CTL and the memory device ME2 farther away from it, the condition for eliminating the reflected signal is undesirably satisfied. In this case, fewer reflected signals propagate from the memory device ME2 farther away from the control device CTL to the memory device ME1 closer to it. Therefore, in the memory device ME1 closer to it, the effect of eliminating the reflected signal is insufficient, and the waveform integrity may be reduced. The same phenomenon will also be caused in the signal offset within one cell of one cycle.

[0167] As described above, as Figure 14 shown, the conditions to be avoided for the command address signal CA are "n = (odd number)" and "m = 0". Similar to the chip select signal CS, as a result of observing the waveform of the command address signal CA under simulation, a reduction in waveform integrity is observed at half of the distance Lm from the optimal conditions of "n = (even number)" and "m = 0". Therefore, as Figure 14 shown, the additional conditions to be avoided are "n = (even number)" and "m = 3".

[0168] <Main effects of the second embodiment>

[0169] By using the electronic device according to the second embodiment, effects similar to various effects of the first embodiment can be provided. In addition, in the second embodiment, the wiring length between the control device and the memory device closer to it is limited. In this way, the interference phenomenon that cancels the effect of the reflected signal between adjacent memory devices can be suppressed. Therefore, the waveform integrity can be further improved. In addition, since the wiring length of the clock signal CK (which is not directly related to the effect of canceling the reflected signal) is limited, the integrity of the signal waveform can be further improved.

Claims

1. An electronic device, comprising: A wiring substrate having a first surface, a second surface opposite to the first surface, a plurality of wiring layers, and a plurality of wirings; a first memory device mounted on the first surface; a second memory device mounted on the first surface; a third memory device mounted on the second surface; a fourth memory device mounted on the second surface; as well as a control device mounted on the first surface, the control device configured to access each of the first memory device and the second memory device by using a common first clock signal and a common first chip select signal, and the control device configured to access each of the third memory device and the fourth memory device by using a common second clock signal and a common second chip select signal, The plurality of wirings include: a plurality of first wirings through which the common first clock signal and the common first chip select signal are propagated; as well as a plurality of second wirings through which the common second clock signal and the common second chip select signal are propagated, wherein the plurality of first wirings are provided in a wiring layer, among the plurality of wiring layers, which is closer to the first surface than the second surface, and The plurality of second wirings are provided in a wiring layer, among the plurality of wiring layers, which is closer to the second surface than the first surface.

2. The electronic device according to claim 1, Wherein, when it is assumed that each of the period of the common first clock signal and the period of the common second clock signal is “Tck”, and each of the distance between the first memory device and the second memory device and the distance between the third memory device and the fourth memory device is “Lm”, “Lm” is defined based on a propagation delay time “Tck / 2”.

3. The electronic device according to claim 1, in, The wiring substrate includes a plurality of through-via wirings in a gap between the first surface and the second surface, each of the through-via wirings passing through the plurality of wiring layers, The plurality of through-via wirings include: a first through via wiring connecting the first wiring to one of the first memory device and the second memory device; and a second through via wiring connecting the second wiring to one of the third memory device and the fourth memory device, The first through-via wiring comprises: a first through-via section between a connection point with the first wiring and the first surface; and a first open stub between the connection point with the first wiring and the second surface, The second through-via wiring comprises: a second through-via section between a connection point with the second wiring and the second surface; and a second open stub between the connection point with the second wiring and the first surface, wherein the length of the first through-via section is less than the length of the first open-circuit stub, and The length of the second through-via section is smaller than the length of the second open-circuit stub.

4. The electronic device according to claim 3, wherein when it is assumed that each of the period of the common first clock signal and the period of the common second clock signal is “Tck”, each of the distance between the first memory device and the second memory device and the distance between the third memory device and the fourth memory device is “Lm”, and each of the propagation delay time of the first through-via segment and the propagation delay time of the second through-via segment is “τ va ", "Lm" is based on the propagation delay time "Tck / 2-τ va " to define.

5. The electronic device according to claim 3, wherein when a wavelength of a propagation signal propagating through each of the first wiring and the second wiring is assumed to be “λ”, each of the length of the first open stub and the length of the second open stub is smaller than “λ / 4”.

6. The electronic device according to claim 3, wherein when the common first clock signal propagates the first through-via wiring and the common second clock signal propagates the second through-via wiring, the length of the first through-via segment and the length of the second through-via segment are equal to each other, and Wherein when the common first chip select signal propagates the first through-via wiring and the common second chip select signal propagates the second through-via wiring, the length of the first through-via segment and the length of the second through-via segment are equal to each other.

7. The electronic device according to claim 2, wherein the control device is configured to access each of the first memory device, the second memory device, the third memory device, and the fourth memory device by using a common command address signal, and The common command address signal is set to a 2N mode which operates as a unit of two cycles of one of the common first clock signal and the common second clock signal.

8. The electronic device according to claim 7, in, The wiring substrate includes a plurality of through-via wirings in a gap between the first surface and the second surface, each of the through-via wirings passing through the plurality of wiring layers, wherein the plurality of through-via wirings include a third through-via wiring that connects a wiring through which the common command address signal propagates with each of the first memory device and the third memory device, and Wherein, when it is assumed that each of the periods of the common first clock signal and the common second clock signal is "Tck", the wiring length between the external terminal outputting the common command address signal from the control device and the third through-via wiring is configured as "LLc", and "n" is an even number, "LLc" is defined based on the propagation delay time "(Tck / 2)×n".

9. The electronic device according to claim 2, wherein an even number of memory devices are mounted on the first surface, the even number of memory devices including the first memory device and the second memory device and configured to be accessed by using the common first clock signal and the common first chip select signal, wherein an even number of memory devices are mounted on the second surface, the even number of memory devices including the third memory device and the fourth memory device and configured to be accessed by using the common second clock signal and the common second chip select signal, and Wherein, when it is assumed that the distance between two adjacent memory devices among the even-numbered memory devices mounted on the first surface is “Lm”, and it is assumed that the distance between two adjacent memory devices among the even-numbered memory devices mounted on the second surface is “Lm”, “Lm” is defined based on the propagation delay time “Tck / 2”.

10. The electronic device according to claim 1, further comprising: a fifth memory device and a sixth memory device mounted on the first surface; as well as a seventh memory device and an eighth memory device mounted on the second surface, The control device comprises: a first memory interface configured to access each of the first memory device and the second memory device by using the common first clock signal and the common first chip select signal, and configured to access each of the third memory device and the fourth memory device by using the common second clock signal and the common second chip select signal; as well as a second memory interface configured to access each of the fifth memory device and the sixth memory device by using the common third clock signal and the common third chip select signal, and configured to access each of the seventh memory device and the eighth memory device by using the common fourth clock signal and the common fourth chip select signal, and The external terminal of the second memory interface is closer to the interior of the control device than the external terminal of the first memory interface.

11. An electronic device, comprising: A wiring substrate having a first surface, a second surface opposite to the first surface, a plurality of wiring layers, and a plurality of wirings; a first memory device mounted on the first surface; a second memory device mounted on the first surface; as well as a control device mounted on the first surface or the second surface, the control device being configured to access each of the first memory device and the second memory device by using a common clock signal and a common chip select signal, Wherein when it is assumed that each of the cycles of the common first clock signal and the common second clock signal is “Tck” and the distance between the first memory device and the second memory device is “Lm”, “Lm” is defined based on a propagation delay time “Tck / 2”.

12. The electronic device according to claim 11, The wiring substrate comprises: a plurality of first wirings which are some of the plurality of wirings and are configured to propagate the common clock signal and the common chip select signal; as well as a first through-via wiring arranged to penetrate the plurality of wiring layers between the first surface and the second surface and configured to connect the first wiring to one of the first memory device and the second memory device, and The first through-via wiring comprises: a first through-via section between a connection point with the first wiring and the first surface; as well as A first open stub is provided between the connection point with the first wiring and the second surface.

13. The electronic device according to claim 12, Wherein, when assuming that the propagation delay time of the first through-via segment is "τ va ", "Lm" is based on the propagation delay time "Tck / 2-τ va " to define.

14. The electronic device according to claim 12, The length of the first through-via section is smaller than the length of the first open-circuit stub.

15. The electronic device according to claim 14, Wherein when it is assumed that the wavelength of a propagation signal propagating through the first wiring is "λ", the length of the first open-circuited stub is smaller than "λ / 4".

Images