IGBT structure

Abstract

The invention provides an IGBT structure which comprises a drift region, a CS layer, a P-type base region and a trench gate, the CS layer is located between the P-type base region and the drift region, the trench gate penetrates through the P-type base region, and the bottom of the trench gate is located on the CS layer; the groove gate is made of polycrystalline silicon; an N-type injection region and a P-type injection region are arranged at the bottom and the periphery of the bottom of the trench gate; the concentration of the N-type injection region is equal to that of the P-type injection region, and the N-type injection region is larger than and comprises the P-type injection region; or, the concentration of the N-type injection region is equal to that of the P-type injection region, and the P-type injection region is larger than and contains the N-type injection region. The invention can reduce the grid oscillation effect.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to an IGBT structure. Background Art

[0002] As a MOSFET-controlled bipolar junction transistor, an IGBT (Insulated Gate Bipolar Transistor) combines the advantages of high frequency of power MOSFET and low on-state voltage drop of BJT, so it is widely used in the medium and low power, medium and low frequency markets. With the rapid development of the electronics industry, higher requirements are currently put forward for IGBTs, requiring high breakdown voltage, low switching loss, and high switching reliability while having low on-state conduction.

[0003] Figure 1 As shown in the figure, it is the structure diagram of the current mainstream CS-IGBT (Carrier Storage IGBT). Although it greatly reduces the on-state voltage drop of the device without increasing the dose of the back collector, after adopting the CS layer, a potential barrier will be formed, which blocks the holes from being drawn away by the emitter during conduction. Therefore, the holes will accumulate at the bottom of the trench, eventually leading to a relatively serious gate oscillation effect when the device is in the on state.

[0004] Therefore, how to reduce the gate oscillation effect is a problem that needs to be solved currently. Summary of the Invention

[0005] The object of the present invention is to propose an IGBT structure that can reduce the gate oscillation effect.

[0006] To achieve the above object, the present invention provides an IGBT structure, including:

[0007] A drift region, a CS layer, a P-type base region, and a trench gate. The CS layer is located between the P-type base region and the drift region, and the trench gate passes through the P-type base region and the bottom is located in the CS layer;

[0008] The material of the trench gate is polysilicon;

[0009] An N-type implantation region and a P-type implantation region are provided at the bottom and the outer periphery of the bottom of the trench gate;

[0010] The concentration of the N-type implantation region is equal to the concentration of the P-type implantation region, and the N-type implantation region is larger than and includes the P-type implantation region; or,

[0011] The concentration of the N-type implantation region is equal to the concentration of the P-type implantation region, and the P-type implantation region is larger than and includes the N-type implantation region.

[0012] In an alternative embodiment, the IGBT structure from bottom to top is: a P-type collector region, an N-type buffer region, the drift region, the CS layer, and the P-type base region.

[0013] In an alternative embodiment, the top surfaces of the N-type implantation region and the P-type implantation region are higher than or lower than the top surface of the CS layer.

[0014] In an alternative embodiment, the bottom surfaces of the N-type implantation region and the P-type implantation region are higher than or lower than the bottom surface of the CS layer.

[0015] In an alternative embodiment, the trench gates are arranged periodically with longitudinal discontinuities.

[0016] In an alternative embodiment, N-type highly doped regions are provided on both sides of the top of the trench gate.

[0017] In an alternative embodiment, the P-type implantation region is externally connected to the collector region.

[0018] In an alternative embodiment, the CS layer is a high N-type implantation dose layer, and the drift region is N-type.

[0019] The beneficial effects of the present invention are as follows:

[0020] In the present invention, an N-type implantation region and a P-type implantation region are formed at the bottom of the trench gate, thereby forming a depletion layer, which can clamp the potential at the bottom of the trench gate in the off state of the IGBT. Compared with the traditional IGBT, the rate of change of the potential at the bottom of the trench gate during turn-on is reduced, and the gate switching oscillation effect of the device is weakened. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By describing the exemplary embodiments of the present invention in more detail in conjunction with the drawings, the above and other objects, features, and advantages of the present invention will become more apparent. In the exemplary embodiments of the present invention, the same reference numerals generally represent the same components.

[0022] Figure 1 FIG. is a schematic diagram of an IGBT structure in the prior art.

[0023] Figure 2 FIG. is a schematic diagram of an IGBT structure in an embodiment of the present invention.

[0024] Figure 3 FIG. is a schematic diagram of the formation of a depletion layer in an IGBT structure in an embodiment of the present invention.

[0025] Figure 4 FIG. is a flowchart of the manufacturing process of an IGBT structure in an embodiment of the present invention.

[0026] Figures 5 to 9 FIG. is a schematic diagram of the structure corresponding to different steps in the manufacturing process of an IGBT structure in an embodiment of the present invention.

[0027] Figure 10 FIG. is a schematic diagram of an IGBT structure in another embodiment of the present invention.

[0028] Description of reference numerals:

[0029] 1-collector region; 2-N-type buffer region; 3-drift region; 4-CS layer; 5-P-type base region; 6-N-type injection region; 7-P-type injection region; 8-trench gate; 9-N-type high-doping region; 10-trench; 11-sacrificial oxide layer. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0031] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0032] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0034] Embodiment 1

[0035] Referring to Figures 2 to 9 , this embodiment provides an IGBT structure, including:

[0036] A drift region 3, a CS layer 4, a P-type base region 5, and a trench gate 8. The CS layer 4 is located between the P-type base region 5 and the drift region 3. The trench gate 8 passes through the P-type base region 5 and its bottom is located in the CS layer 4;

[0037] The material of the trench gate 8 is polysilicon;

[0038] An N-type implantation region 6 and a P-type implantation region 7 are provided at the bottom and the outer periphery of the bottom of the trench gate 8;

[0039] The concentration of the N-type implantation region 6 is equal to the concentration of the P-type implantation region 7, and the N-type implantation region 6 is larger than and includes the P-type implantation region 7.

[0040] In this embodiment, the IGBT structure from bottom to top is: a P-type collector region 1, an N-type buffer region 2, the drift region 3, the CS layer 4, and the P-type base region 5. The CS layer 4 is a high N-type implantation dose layer, and the drift region 3 is N-type. N-type highly doped regions 9 are provided on both sides of the top of the trench gate 8.

[0041] In this embodiment, the P-type implantation region 7 is externally connected to the collector region 1.

[0042] In this embodiment, the top surfaces of the N-type implantation region 6 and the P-type implantation region 7 are higher than or lower than the top surface of the CS layer 4. The bottom surfaces of the N-type implantation region 6 and the P-type implantation region 7 are higher than or lower than the bottom surface of the CS layer 4.

[0043] In this embodiment, the trench gates 8 are arranged longitudinally at intervals periodically. The longitudinal length of the trench gate 8 is considered in a trade-off according to the short-circuit capability of the device.

[0044] Referring to Figures 4 to 9 , the manufacturing method of this IGBT structure is:

[0045] CS layer implantation is performed on the drift layer, and then a trench 10 is etched, and a sacrificial oxide layer 11 is formed in the trench 10. In the general implantation process, an N-type implantation region 6 and a P-type implantation region 7 are formed at the bottom of the trench 10, where Figure 8 The uppermost red region refers to the N-type region formed when the N-type implantation region and the P-type implantation region are formed by general implantation. The sacrificial oxide layer is removed, gate oxide and polysilicon are formed, P-type implantation forms a P-type base region 8, an N-type highly doped region 9 is formed on the outer periphery of the trench gate 8, IDL is formed, CT holes are etched and a P-type highly doped region is formed, and finally metal deposition and etching are performed.

[0046] In this embodiment, the highly doped N-type implantation region 6 at the bottom of the trench cooperates with the CS layer 4 to form a hole barrier with the drift region 3, preventing holes from being drawn away and further reducing the on-state voltage drop.

[0047] The highly doped N-type implantation region 6 at the bottom of the trench isolates the accumulation of holes at the bottom of the gate, reduces the potential change gradient at the bottom of the trench when the device is turned on, and reduces the switching oscillation effect of the device gate.

[0048] A depletion layer is formed at the bottom of the trench gate, which can clamp the potential at the bottom of the trench gate in the off state of the IGBT. Compared with the traditional IGBT, the potential change rate at the bottom of the trench gate is reduced when it is turned on, and the switching oscillation effect of the device gate is weakened.

[0049] By using N and P-type implantations, the size of the depletion layer can be adjusted by adjusting the energy and dose of N and P-type implantations, thereby controlling Cgd (Cgd is the equivalent capacitance between the gate and the drain of the IGBT and the potential at the bottom of the trench gate when the IGBT is turned off), and finally optimizing the switching loss and waveform.

[0050] The N-type implantation region and the P-type implantation region are formed by general implantation after the formation of the sacrificial oxide layer, without the formation of an additional oxidation barrier layer and an additional photomask. In addition, the push junction of the N-type implantation region and the P-type implantation region is compatible with the gate oxide and its subsequent thermal processes without additional thermal processes.

[0051] Although adding an N-type implantation region will cause the reverse voltage of the device to weaken, since a P-type implantation region is added at the bottom of the gate at the same time, this causes the P-type implantation regions to deplete each other during reverse voltage withstand, further improving and making up for the reduction of the reverse voltage withstand of the device caused by the N-type region.

[0052] The trench gates are arranged intermittently to ensure that the P-type region at the bottom of the trench gates is grounded externally while optimizing the short-circuit capability of the device.

[0053] Embodiment 2

[0054] Referring to Figure 10 , this embodiment provides an IGBT structure, including:

[0055] A drift region 3, a CS layer 4, a P-type base region 5, and a trench gate 8. The CS layer 4 is located between the P-type base region 5 and the drift region 3. The trench gate 8 penetrates through the P-type base region 5 and its bottom is located at the CS layer 4.

[0056] The material of the trench gate 4 is polysilicon.

[0057] An N-type implantation region 6 and a P-type implantation region 7 are provided at the bottom and the outer periphery of the bottom of the trench gate 4.

[0058] The concentration of the N-type implantation region 6 is equal to that of the P-type implantation region 7, and the P-type implantation region 7 is larger than and includes the N-type implantation region 6.

[0059] The difference between this embodiment and Embodiment 1 is that the P-type implantation region 7 is larger than and includes the N-type implantation region 6, and other structures are the same as those in Embodiment 1.

[0060] In this embodiment, a depletion layer is formed at the bottom of the trench gate, which can clamp the potential at the bottom of the trench gate in the IGBT off state. Compared with the traditional IGBT, the change rate of the potential at the bottom of the trench gate during turn-on is reduced, and the gate switching oscillation effect of the device is weakened.

[0061] By using N and P-type implantations, the size of the depletion layer can be adjusted by adjusting the energy and dose of the N and P-type implantations, thereby controlling C gd And the potential at the bottom of the trench gate when the IGBT is turned off, and finally optimize the switching loss and waveform.

[0062] The N-type implantation region and the P-type implantation region are formed by general implantation after the sacrificial oxide layer is formed, without the formation of an additional oxidation barrier layer and an additional photomask. In addition, the push junction of the N-type implantation region and the P-type implantation region is compatible with the gate oxide and its subsequent thermal processes without additional thermal processes.

[0063] By adopting the form that the P-type implantation region includes the N-type implantation region, the breakdown voltage of the device can be greatly improved during reverse voltage withstand, so the reverse design window of the device is increased, and the implantation dose and energy of the carrier storage layer can be further optimized or the thickness of the device drift region can be reduced, finally reducing the on-state voltage drop of the device and optimizing the switching loss.

[0064] In the prior art, as Figure 1 shown, the depth of the CS layer does not exceed the bottom of the trench (the trench depth is set). In the above two embodiments, P and N implantations are formed at the bottom of the trench, which can make the depth of the CS layer deeper and improve the breakdown voltage and reliability of the device.

[0065] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art according to the above disclosure are within the protection scope of the claims.

Claims

1. An IGBT structure, characterized in that: include: A drift region, a CS layer, a P-type base region and a trench gate, wherein the CS layer is located between the P-type base region and the drift region, and the trench gate passes through the P-type base region, with the bottom thereof being located in the CS layer; The material of the groove gate is polysilicon; The bottom and periphery of the bottom of the trench gate are provided with an N-type implantation region and a P-type implantation region; The concentration of the N-type implantation region is equal to the concentration of the P-type implantation region, and the N-type implantation region is larger than and includes the P-type implantation region; or, The concentration of the N-type implantation region is equal to the concentration of the P-type implantation region, and the P-type implantation region is larger than and includes the N-type implantation region.

2. The IGBT structure according to claim 1, characterized in that: The IGBT structure is, from bottom to top, a P-type collector region, an N-type buffer region, the drift region, the CS layer, and the P-type base region.

3. The IGBT structure according to claim 1, characterized in that: Top surfaces of the N-type implantation region and the P-type implantation region are higher or lower than a top surface of the CS layer.

4. The IGBT structure according to claim 1, characterized in that: The bottom surfaces of the N-type implantation region and the P-type implantation region are higher or lower than the bottom surface of the CS layer.

5. The IGBT structure according to claim 1, characterized in that: The groove gates are arranged intermittently and periodically in the longitudinal direction.

6. The IGBT structure according to claim 1, characterized in that: N-type high-doping regions are arranged on both sides of the top of the groove gate.

7. The IGBT structure according to claim 2, characterized in that: The P-type injection region is externally connected to the collector region.

8. The IGBT structure according to claim 1, characterized in that: The CS layer is a high N-type implantation dose layer, and the drift region is N-type.

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