Enhanced GaN HEMT device and manufacturing method
By forming a mask layer on the AlGaN barrier layer and depositing a PGaN top cover layer in an enhanced GaN HEMT device, the problems of large on-resistance and low breakdown voltage are solved, and higher device performance and service life are achieved.
Patent Information
- Application Number
- CN202311819688.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2025-06-27
AI Technical Summary
The existing enhanced GaN HEMT devices have large on-resistance and low breakdown voltage, resulting in poor device performance.
By forming a mask layer on the AlGaN barrier layer and depositing a PGaN top cover layer at the mask opening, damage to the AlGaN barrier layer by dry etching is avoided, device on resistance is reduced, and a passivation layer is formed on the AlGaN barrier layer to reduce interface leakage current.
It effectively reduces the on-resistance of the device, improves the breakdown voltage and service life, and enhances the performance of the device.
Smart Images
Figure CN120224714A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductors, and relates to an enhanced GaN HEMT device and a manufacturing method thereof. Background Art
[0002] Silicon materials have always been the main semiconductor materials used in power electronic devices. With the continuous in-depth research, all aspects of the performance of silicon materials have tended to a theoretical limit determined by material characteristics with the gradual improvement of its structural design and manufacturing process. Gallium nitride (GaN) materials have characteristics such as a large bandgap, a high breakdown field strength, and a large electron saturation drift velocity. As an important part of the third-generation semiconductors, they have been widely used in mobile phone fast charging at present and will gradually penetrate into fields such as industrial power supplies, motor drives, and new energy vehicles in the future.
[0003] Gallium nitride high electron mobility transistor (GaN HEMT), as a representative of wide-bandgap power semiconductor devices, has great potential in high-frequency power applications. The AlGaN / GaN heterojunction is the basic structure of GaN HEMT devices. Due to the unique spontaneous polarization and piezoelectric polarization effects of GaN materials, a high-concentration two-dimensional electron gas (2DEG) naturally exists at the channel of GaN HEMT devices, and its threshold voltage (Vth) is negative, which is a normally-on (depletion-type) device; currently, there are methods such as P-type gates, polarization cancellation, negative ion implantation, recessed gates, and Cascode cascades to deplete the 2DEG at the AlGaN / GaN heterojunction to achieve a normally-off (enhanced-type) device. Among them, the P-type gate technology is the main method to realize enhanced GaN HEMT devices, which has the advantages of strong process controllability and the ability to be mass-produced repeatedly. As Figures 1 to 2 shown, it shows a schematic diagram of a manufacturing method of an enhanced GaN HEMT device, including the following steps: (1) As Figure 1 shown, the GaN channel layer 4 and the AlGaN barrier layer 5 form an AlGaN / GaN heterojunction, and a PGaN material layer 11 is formed on the AlGaN barrier layer 5; (2) As Figure 2 shown, the PGaN material layer 11 is etched by chlorine-based or fluorine-based inductively coupled plasma to form a PGaN top layer 10. Dry etching will damage the surface of the AlGaN barrier layer 5 and the side of the PGaN top layer 10, introducing additional surface state defects such as nitrogen vacancies, thereby increasing the on-resistance of the device, increasing gate leakage, and reducing the breakdown voltage and service life.
[0004] Therefore, how to provide an enhanced GaN HEMT device and a manufacturing method thereof to reduce the on-resistance of the device, improve the breakdown voltage and service life of the device has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an enhanced GaN HEMT device and a manufacturing method thereof, which are used to solve the problems of large on-resistance and low breakdown voltage of the enhanced GaN HEMT device in the prior art.
[0006] To achieve the above purpose and other related purposes, the present invention provides a manufacturing method of an enhanced GaN HEMT device, including the following steps:
[0007] Provide a substrate, form a GaN channel layer and an AlGaN barrier layer stacked from bottom to top on the substrate, and form a mask layer on the AlGaN barrier layer;
[0008] Pattern the mask layer to form a mask opening, the mask opening defines the position of the PGaN cap layer, wherein the mask opening exposes the AlGaN barrier layer;
[0009] Form the PGaN cap layer in the mask opening.
[0010] Optionally, before forming the mask layer, it further includes the step of forming a passivation layer, the mask layer is formed on the upper surface of the passivation layer, wherein the mask opening also penetrates the passivation layer to expose the AlGaN barrier layer.
[0011] Optionally, the passivation layer includes an Al2O3 layer, and the mask layer includes a SiO2 layer or a SiN layer.
[0012] Optionally, the step of patterning the mask layer to form the mask opening includes:
[0013] Form a photoresist layer on the mask layer, pattern the photoresist layer to define the position of the mask opening;
[0014] Use a buffered oxide etchant to etch the mask layer to form the mask opening;
[0015] Use a hydrochloric acid solution to etch the passivation layer so that the mask opening exposes the AlGaN barrier layer.
[0016] Optionally, the method of forming the GaN channel layer and the AlGaN barrier layer includes metal organic chemical vapor deposition, the method of forming the passivation layer includes atomic layer deposition, and the method of forming the mask layer includes magnetron sputtering.
[0017] Optionally, the method of forming the PGaN cap layer includes metal organic chemical vapor deposition, and the temperature range for forming the PGaN cap layer is 900 - 1100 °C.
[0018] Optionally, before forming the GaN channel layer on the substrate, the steps of forming a nucleation layer and a buffer layer are further included, and the GaN channel layer is formed on the upper surface of the buffer layer.
[0019] Optionally, the nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN layer.
[0020] The present invention further provides an enhancement-mode GaN HEMT device, including:
[0021] A substrate;
[0022] A GaN channel layer located above the substrate;
[0023] An AlGaN barrier layer located above the GaN channel layer;
[0024] A PGaN cap layer located above the AlGaN barrier layer;
[0025] A passivation layer located above the AlGaN barrier layer, and in the horizontal direction, the passivation layer is located on both sides of the PGaN cap layer.
[0026] Optionally, the passivation layer includes an Al2O3 layer, and the thickness range of the passivation layer is 0.5 - 15 nm.
[0027] As described above, in the enhancement-mode GaN HEMT device and manufacturing method of the present invention, after forming the mask opening, depositing to form the PGaN cap layer suppresses the side leakage channel of the PGaN cap layer, improves the gate breakdown voltage, and avoids the damage to the AlGaN barrier layer caused by dry etching, reduces the trap concentration in the AlGaN barrier layer, and reduces the on-resistance of the device; in addition, a passivation layer is formed on the AlGaN barrier layer, which can reduce the interface leakage current and improve the off-state drain breakdown voltage. Description of the Drawings
[0028] Figure 1 It shows a schematic diagram of forming a PGaN material layer on an AlGaN barrier layer in a manufacturing method of an enhancement-mode GaN HEMT device.
[0029] Figure 2 It shows a schematic diagram of etching the PGaN material layer to form a PGaN cap layer in a manufacturing method of an enhancement-mode GaN HEMT device.
[0030] Figure 3 It shows a process flow chart of the manufacturing method of the enhancement-mode GaN HEMT device of the present invention.
[0031] Figure 4Schematic diagram showing the sequential formation of a nucleation layer, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a passivation layer, and a mask layer on a substrate in the manufacturing method of the enhanced GaN HEMT device of the present invention.
[0032] Figure 5 Schematic diagram showing the formation and patterning of a photoresist layer on the mask layer in the manufacturing method of the enhanced GaN HEMT device of the present invention.
[0033] Figure 6 Schematic diagram showing the formation of a mask opening in the manufacturing method of the enhanced GaN HEMT device of the present invention.
[0034] Figure 7 Schematic diagram showing the formation of a PGaN cap layer in the manufacturing method of the enhanced GaN HEMT device of the present invention.
[0035] Figure 8 Schematic diagram showing the removal of the mask layer in the manufacturing method of the enhanced GaN HEMT device of the present invention.
[0036] Description of component labels
[0037] 1 Substrate
[0038] 2 Nucleation layer
[0039] 3 Buffer layer
[0040] 4 GaN channel layer
[0041] 5 AlGaN barrier layer
[0042] 6 Passivation layer
[0043] 7 Mask layer
[0044] 8 Photoresist layer
[0045] 9 Mask opening
[0046] 10 PGaN cap layer
[0047] 11 PGaN material layer
[0048] Steps S1 to S3 Detailed implementation manners
[0049] The following illustrates the implementation manners of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0050] Please refer to Figures 3 to 8 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0051] This embodiment provides a method for manufacturing an enhanced GaN HEMT device. Please refer to Figure 3 , which shows a process flow chart of the manufacturing method, including the following steps:
[0052] S1: Provide a substrate, form a GaN channel layer and an AlGaN barrier layer stacked from bottom to top on the substrate, and form a mask layer on the AlGaN barrier layer;
[0053] S2: Pattern the mask layer to form a mask opening, the mask opening defines the position of the PGaN cap layer, wherein the mask opening exposes the AlGaN barrier layer;
[0054] S3: Form the PGaN cap layer in the mask opening.
[0055] First, please refer to Figure 4 , perform step S1: Provide a substrate 1, form a GaN channel layer 4 and an AlGaN barrier layer 5 stacked from bottom to top on the substrate 1, and form a mask layer 7 on the AlGaN barrier layer 5.
[0056] As an example, the substrate 1 can be a silicon substrate, a silicon carbide substrate, a sapphire substrate, or any other suitable substrate.
[0057] As an example, before forming the GaN channel layer 4 and the AlGaN barrier layer 5, it further includes the steps of forming a nucleation layer 2 and a buffer layer 3 to alleviate the problem of crystal mismatch between the GaN channel layer 4 and the substrate 1 and improve the quality of the GaN channel layer 4; specifically, in this embodiment, the nucleation layer 2 is an AlN layer, the buffer layer 3 is an AlGaN layer, and the buffer layer 3 is a multi-layered Al-Ga-N-based material layer to form the stress-relieved buffer layer 3.
[0058] As an example, it further includes the step of forming a GaN high-resistance layer (not shown) between the buffer layer 3 and the GaN channel layer 4. The GaN high-resistance layer is doped with elements such as C or Fe to increase the resistance value, thereby improving the breakdown voltage of the power device.
[0059] As an example, before forming the mask layer 7, it further includes the step of forming a passivation layer 6, and the passivation layer 6 is located between the AlGaN barrier layer 5 and the mask layer 7; specifically, in this embodiment, the passivation layer 6 is an Al2O3 layer, and the mask layer 7 is an SiO2 layer or a SiN layer.
[0060] As an example, the nucleation layer 2, the buffer layer 3, the GaN channel layer 4, and the AlGaN barrier layer 5 are sequentially formed on the substrate 1 by metal organic chemical vapor deposition (MOCVD), the passivation layer 6 is formed on the AlGaN barrier layer 5 by atomic layer deposition (ALD), and the mask layer 7 is formed on the passivation layer 6 by magnetron sputtering. Of course, in other examples, other suitable deposition methods may also be used to form the nucleation layer 2, the buffer layer 3, the GaN channel layer 4, the AlGaN barrier layer 5, the passivation layer 6, and the mask layer 7, which is not limited to this embodiment.
[0061] Next, please refer to Figures 5 to 6 , and perform step S2: Pattern the mask layer 7 to form a mask opening 9, and the mask opening 9 defines the position of the p-GaN cap layer, wherein the mask opening 9 exposes the AlGaN barrier layer 5.
[0062] As an example, since the passivation layer 6 is provided between the mask layer 7 and the AlGaN barrier layer 5, the mask opening 9 also penetrates through the passivation layer 6 to expose the AlGaN barrier layer 5.
[0063] As an example, the step of forming the mask opening 9 includes:
[0064] (1) As shown in Figure 5 , form a photoresist layer 8 on the mask layer 7 and pattern it, and the patterned photoresist layer 8 defines the position of the mask opening 9;
[0065] (2) As shown in Figure 6 , etch the mask layer 7 with buffered oxide etchant (BOE) to form the mask opening 9, and etch the passivation layer 6 with a diluted hydrochloric acid solution to expose the AlGaN barrier layer 5 through the mask opening 9.
[0066] As an example, after the mask opening 9 exposes the AlGaN barrier layer 5, it further includes the step of removing the photoresist layer 8.
[0067] Next, please refer to Figure 7 , and perform step S3: Form the p-GaN cap layer 10 in the mask opening 9.
[0068] As an example, the PGaN capping layer 10 (P-type gate) is formed by metalorganic chemical vapor deposition (MOCVD). The temperature range for forming the PGaN capping layer 10 is 900 - 1100 °C. Due to the difference in nucleation energy, the PGaN capping layer 10 can only nucleate and grow in the exposed AlGaN layer 5 region. The PGaN capping layer 10 raises the conduction band energy level, realizes the depletion of 2DEG, and realizes the normally-off function of the device. Moreover, the PGaN capping layer 10 formed by high-temperature MOCVD has high crystal quality, improves the stability of the gate in the forward and reverse directions, and improves the gate lifetime. Specifically, in this embodiment, the temperature for depositing the PGaN capping layer 10 is 1000 °C.
[0069] As an example, after the mask opening 9 defines the position of the PGaN capping layer 10, the PGaN capping layer 10 is deposited and formed. Since there is no PGaN gate etching step, the leakage channel on the side of the PGaN gate is suppressed, and the gate breakdown voltage is improved.
[0070] As an example, since there is no dry etching process in the preparation process of the PGaN gate, the damage to the AlGaN barrier layer 5 caused by dry etching is avoided, the trap concentration in the AlGaN barrier layer 5 is reduced, and the high mobility and concentration of 2DEG in the channel layer are maintained, thereby reducing the on-resistance of the device.
[0071] As an example, as Figure 8 shown, after the PGaN capping layer 10 is formed, the mask layer 7 is removed by a diluted hydrofluoric acid solution, and the passivation layer 6 is retained. In this embodiment, the AlGaN barrier layer 5 prepared by metalorganic chemical vapor deposition has a small surface roughness, can reduce the surface defects of the AlGaN barrier layer 5, and combined with the deposited passivation layer 7, further passivates the interface defects, which can reduce the interface leakage current, thereby improving the off-state drain breakdown voltage.
[0072] As an example, in this embodiment, the thickness of the passivation layer 6 is 0.5 - 15 nm. The main function of the passivation layer 6 is to reduce the interface leakage current. A too thick passivation layer 7 is not conducive to device integration and miniaturization, and increases the cost. The thickness of the mask layer 7 is 50 - 500 nm, and the thickness of the mask layer 7 is not less than the thickness of the PGaN capping layer 10.
[0073] As an example, the 2DEG below the PGaN capping layer 10 region is depleted, and the concentration of 2DEG in the regions on both sides of the PGaN capping layer 10 is well maintained. The subsequent processes are compatible with depletion-mode GaN devices, which is convenient for the integration of enhancement-mode and depletion-mode devices.
[0074] So far, an enhancement-mode GaN HEMT device is fabricated. Please refer toFigure 8 , the enhanced GaN HEMT device includes a substrate 1, a GaN channel layer 4, an AlGaN barrier layer 5, a PGaN cap layer 10, and a passivation layer 6. Among them, the GaN channel layer 4 is located above the substrate 1; the AlGaN barrier layer 5 is located above the GaN channel layer 4; the PGaN cap layer 10 is located above the AlGaN barrier layer 5; the passivation layer 6 is located above the AlGaN barrier layer 5. Horizontally, the passivation layer 6 is located on both sides of the PGaN cap layer 10.
[0075] As an example, the substrate 1 can be a silicon substrate, a silicon carbide substrate, a sapphire substrate, or any other suitable substrate.
[0076] As an example, the GaN channel layer 4 and the AlGaN barrier layer 5 form an AlGaN / GaN heterojunction. There is a high concentration of 2DEG naturally in the channel. The PGaN cap layer 10 is provided on the AlGaN barrier layer 5 to increase the conduction band energy level, so that the 2DEG below the PGaN cap layer 10 is depleted, realizing the normally-off function of the device.
[0077] As an example, the passivation layer 6 includes an Al2O3 layer with a thickness range of 0.5 - 15 nm. The passivation layer 6 can passivate the interface defects of the AlGaN barrier layer 5, reduce the interface leakage current, and thus increase the off-state drain breakdown voltage.
[0078] As an example, between the substrate 1 and the GaN channel layer 4, there are also a nucleation layer 2 and a buffer layer 3 stacked from bottom to top to alleviate the problem of crystal mismatch between the GaN channel layer 4 and the substrate 1. Specifically, in this embodiment, the nucleation layer 2 is made of an AlN layer, the buffer layer 3 is made of an AlGaN layer, and the buffer layer 3 is made of a multi-layered Al-Ga-N-based material layer to form the stress-relieved buffer layer 3.
[0079] As an example, a GaN high-resistance layer is provided between the buffer layer 3 and the GaN channel layer 4. The GaN high-resistance layer is doped with elements such as C or Fe to increase the resistance value, thereby improving the breakdown voltage withstand capacity of the power device.
[0080] In summary, in the enhanced GaN HEMT device and manufacturing method of the present invention, after forming the mask opening, a PGaN top layer is deposited to suppress the side leakage channel of the PGaN top layer, improve the gate breakdown voltage, avoid the damage to the AlGaN barrier layer caused by dry etching, reduce the trap concentration in the AlGaN barrier layer, and reduce the on-resistance of the device. In addition, a passivation layer is formed on the AlGaN barrier layer, which can reduce the interface leakage current and improve the off-state drain breakdown voltage. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0081] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A manufacturing method of an enhanced GaN HEMT device, characterized in that, Including the following steps: Providing a substrate, forming a GaN channel layer and an AlGaN barrier layer stacked from bottom to top on the substrate, and forming a mask layer on the AlGaN barrier layer; Patternizing the mask layer to form a mask opening, the mask opening defining the position of a PGaN cap layer, wherein the mask opening exposes the AlGaN barrier layer; Forming the PGaN cap layer in the mask opening.
2. The manufacturing method of the enhanced GaN HEMT device according to claim 1, characterized in that: Before forming the mask layer, it further includes the step of forming a passivation layer, the mask layer being formed on the upper surface of the passivation layer, wherein the mask opening also penetrates through the passivation layer to expose the AlGaN barrier layer.
3. The manufacturing method of the enhanced GaN HEMT device according to claim 2, characterized in that: The passivation layer includes an Al2O3 layer, and the mask layer includes a SiO2 layer or a SiN layer.
4. The manufacturing method of the enhanced GaN HEMT device according to claim 3, characterized in that, The step of patternizing the mask layer to form the mask opening includes: Forming a photoresist layer on the mask layer, patternizing the photoresist layer to define the position of the mask opening; Etching the mask layer using a buffered oxide etchant to form the mask opening; Etching the passivation layer using a hydrochloric acid solution to make the mask opening expose the AlGaN barrier layer.
5. The manufacturing method of the enhanced GaN HEMT device according to claim 2, characterized in that: The method for forming the GaN channel layer and the AlGaN barrier layer includes metal organic chemical vapor deposition, the method for forming the passivation layer includes atomic layer deposition, and the method for forming the mask layer includes magnetron sputtering.
6. The manufacturing method of the enhanced GaN HEMT device according to claim 1, characterized in that: The method for forming the PGaN cap layer includes metal organic chemical vapor deposition, and the temperature range for forming the PGaN cap layer is 900 - 1100 °C.
7. The manufacturing method of the enhanced GaN HEMT device according to claim 1, characterized in that: Before forming the GaN channel layer on the substrate, it further includes the steps of forming a nucleation layer and a buffer layer, the GaN channel layer being formed on the upper surface of the buffer layer.
8. The manufacturing method of the enhanced GaN HEMT device according to claim 7, characterized in that: The nucleation layer includes an AlN layer, and the buffer layer includes an AlGaN layer.
9. An enhanced GaN HEMT device, characterized in that, Including: A substrate; A GaN channel layer, located above the substrate; An AlGaN barrier layer, located above the GaN channel layer; A PGaN cap layer, located above the AlGaN barrier layer; A passivation layer, located above the AlGaN barrier layer, and in the horizontal direction, the passivation layer is located on both sides of the PGaN cap layer.
10. The enhanced GaN HEMT device according to claim 9, wherein: The passivation layer includes an Al2O3 layer, and the thickness range of the passivation layer is 0.5 - 15 nm.