Planar gate silicon carbide VDMOS with high UIS reliability and preparation method thereof

Abstract

The invention provides a planar gate silicon carbide VDMOS with high UIS reliability and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a gate protection region is formed; a shunt region and a source protection region; the source electrode protection area is grounded; ion implantation is carried out again to form a P-type well region, and a protruding part is formed on the drift layer; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region and an N-type source region are formed; the method comprises the following steps of: forming a gate protection region, re-forming a barrier layer, etching, depositing and forming an insulating dielectric layer, a gate metal layer and a source metal layer, and ensuring that a parasitic NPN transistor in the device is turned off during drain voltage impact through the gate protection region and the source protection region connected with the ground, thereby improving the UIS resistance of the device and improving the reliability of the device.

Description

Technical Field

[0001] The present invention relates to a high-UIS-reliability planar-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Due to its wide bandgap characteristics, a silicon carbide VDMOS device naturally has the characteristics of low gate charge and high switching speed compared with a Si VDMOS device. Under the application conditions of high voltage (above 1000V) and large current (above 100A), a single silicon carbide VDMOS device cannot meet the application requirements, and multiple devices need to be applied in parallel. During the turn-off process of the parallel devices, due to the incomplete symmetry of the device distribution, current will impact a single silicon carbide VDMOS device, resulting in the burnout of the VDMOS device. Therefore, the existing technology has higher requirements for the UIS characteristics of VDMOS devices. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-UIS-reliability planar-gate silicon carbide VDMOS and a preparation method thereof. Through a gate protection area and a source protection area connected to the ground, the parasitic NPN transistor inside the device is ensured to turn off during the impact of the drain voltage, thereby improving the UIS resistance of the device and enhancing the device reliability.

[0004] In the first aspect, the present invention provides a preparation method of a high-UIS-reliability planar-gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a gate protection area; Step 3: Remove the blocking layer in Step 2, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a shunt area; Step 4: Remove the blocking layer in Step 3, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a source protection area; ground the source protection area; Step 5: Perform ion implantation again to form a P-type well area, and form a convex portion on the drift layer; Step 6: Remove the blocking layer in Step 4, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type source area; Step 7: Remove the blocking layer in Step 6, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source area; Step 8: Remove the blocking layer in Step 7, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating dielectric layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a via hole, deposit, and form a gate metal layer; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a via hole, deposit, and form a source metal layer, and remove the blocking layer to complete the preparation.

[0005] In a second aspect, the present invention provides a high-UIS-reliability planar-gate silicon carbide VDMOS, which is prepared by using the preparation method of a high-UIS-reliability planar-gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are as follows: 1. The present invention constructs a source protection area, and the source protection area is grounded. The P-type area in the middle of the NPN transistor in the N-type source area - P-type well area - source protection area - drift layer inside the device is always at a low potential, and the NPN transistor cannot conduct, thereby improving the source UIS characteristics of the device; 2. The present invention constructs a gate protection area and a shunt area structure. When the drain bears a high voltage, the gate protection area forms protection for the gate structure, and the shunt area realizes the potential transfer from the drift layer near the drain to the drift layer near the gate, thereby ensuring that the NPN structures in the horizontal and vertical directions of the device will not conduct; in addition to the function of potential transfer, the shunt area can also reduce the body resistance of the device, effectively reduce the on-resistance of the device, and reduce the conduction loss of the device. Description of the Drawings

[0007] The following further describes the present invention with reference to the accompanying drawings in conjunction with embodiments.

[0008] Figure 1 It is a schematic diagram of a high-UIS-reliability planar-gate silicon carbide VDMOS of the present invention.

[0009] Figure 2 It is a process cross-section of a high-UIS-reliability planar-gate silicon carbide VDMOS of the present invention Figure 1 。

[0010] Figure 3 It is a process cross-section of a high-UIS-reliability planar-gate silicon carbide VDMOS of the present invention Figure 2 。

[0011] Figure 4 It is a process cross-section of a high-UIS-reliability planar-gate silicon carbide VDMOS of the present invention Figure 3 。

[0012] Figure 5 It is a process cross-section of a high-UIS-reliability planar-gate silicon carbide VDMOS of the present invention Figure 4 。

[0013] Figure 6 Process cross-section of a high-UIS reliability planar-gate silicon carbide VDMOS according to the present invention Figure 5 .

[0014] Figure 7 Process cross-section of a high-UIS reliability planar-gate silicon carbide VDMOS according to the present invention Figure 6 .

[0015] Figure 8 Process cross-section of a high-UIS reliability planar-gate silicon carbide VDMOS according to the present invention Figure 7 .

[0016] Figure 9 Process cross-section of a high-UIS reliability planar-gate silicon carbide VDMOS according to the present invention Figure 8 .

[0017] Figure 10 Process cross-section of a high-UIS reliability planar-gate silicon carbide VDMOS according to the present invention Figure 9 .

[0018] Figure 11 Process cross-section of a high-UIS reliability planar-gate silicon carbide VDMOS according to the present invention Figure 10 . Detailed implementation manners

[0019] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0021] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion.

[0022] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0023] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have" or the like specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0024] As Figures 1 to 11 shown, an embodiment of the present application provides a method for preparing a high-UIS reliability planar-gate silicon carbide VDMOS, comprising the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2; Step 2: Form a blocking layer 100 above the drift layer 2, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a gate protection region 21; Step 3: Remove the blocking layer 100 in Step 2, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a shunt region 22; Step 4: Remove the blocking layer 100 in Step 3, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a source protection region 3; ground the source protection region 3; Step 5: Perform ion implantation again to form a P-type well region 4, and form a protrusion 23 on the drift layer 2; Step 6: Remove the blocking layer 100 in Step 4, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type source region 42; Step 7: Remove the blocking layer 100 in Step 6, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form an N-type source region 41; Step 8: Remove the blocking layer 100 in Step 7, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit to form an insulating dielectric layer 5; Step 9: Remove the blocking layer 100 in Step 8, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit to form a gate metal layer 6; Step 10: Remove the blocking layer 100 in Step 9, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit to form a source metal layer 7, and remove the blocking layer 100 to complete the preparation.

[0025] In this embodiment, preferably, the width of the gate protection region 21 is equal to the width of the protrusion 23, and the gate protection region 21 is located directly below the protrusion 23.

[0026] In this embodiment, preferably, the thickness of the gate protection region 21 is less than the thickness of the shunt region 22, and the lower side of the gate protection region 21 and the lower side of the shunt region 22 are on the same plane.

[0027] In this embodiment, preferably, the doping concentration of the gate protection region 21 is less than the doping concentration of the shunt region 22.

[0028] In this embodiment, preferably, the width of the shunt region 22 is equal to the width of the source protection region 3, and the shunt region 22 is located directly below the source protection region 3.

[0029] In this embodiment, preferably, the doping concentration of the source protection region 3 is greater than that of the drift layer 2, and the doping concentration of the source protection region 3 is greater than that of the P-type well region 4.

[0030] In this embodiment, preferably, the doping concentration of the P-type well region 4 is less than that of the drift layer 2.

[0031] In this embodiment, preferably, the silicon carbide substrate 1, the drift layer 2, and the shunt region 22 are of N-type; the gate protection region 21 and the source protection region 3 are of P-type.

[0032] As Figure 1 shown, the planar gate silicon carbide VDMOS obtained by the above manufacturing method includes: A silicon carbide substrate 1, A drift layer 2, the lower side of the drift layer 2 is connected to the silicon carbide substrate 1, the gate protection region 21 and the shunt region 22 are provided in the drift layer 2, and the outer side of the gate protection region 21 is connected to the inner side of the shunt region 22; a convex portion 23 is provided on the drift layer 2; A source protection region 3, the lower side of the source protection region 3 is connected to the upper side of the drift layer 2, and the inner side of the source protection region 3 is connected to the outer side of the convex portion 23; the source protection region 3 is grounded; A P-type well region 4, the lower side of the P-type well region 4 is connected to the upper side of the source protection region 3, the inner side of the P-type well region 4 is connected to the outer side of the convex portion 23, an N-type source region 41 and a P-type source region 42 are provided on the P-type well region 4, the outer side of the N-type source region 41 is connected to the inner side of the P-type source region 42, and the inner side of the N-type source region 41 is connected to the P-type well region 4; An insulating dielectric layer 5, the lower side of the insulating dielectric layer 5 is connected to the P-type well region 4 and the convex portion 23; A gate metal layer 6, the lower side of the gate metal layer 6 is connected to the upper side of the insulating dielectric layer 5; A source metal layer 7, the source metal layer 7 is respectively connected to the P-type source region 42 and the N-type source region 41; And a drain metal layer 8, the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1.

[0033] In another embodiment of the present invention, the doping concentration of the silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the drift layer 2 is 6 - 10e16 cm -3 , the doping concentration of the gate protection region 21 is 5 - 8e16 cm -3 , the doping concentration of the shunt region 22 is 1 - 5e18 cm -3, the doping concentration of the source protection region 3 is 5 - 8e18 cm -3 , the doping concentration of the P-type well region 4 is 1 - 5e15 cm -3 , the doping concentration of the P-type source region 42 is 1 - 5e19 cm -3 , the material of the insulating dielectric layer 5 can be silicon dioxide, and the doping concentration of the N-type source region 41 is 2 - 8e18 cm -3 ; The doping concentration of the silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentration design of the gate protection region 21 is to reduce the impact on the on-state characteristics of the device while ensuring device protection; the doping concentration of the shunt region 22 is not only to reduce the bulk resistance of the device and the on-state loss of the device, but also to transfer the potential from below the gate protection region 21 to above the gate protection region 21 to avoid the conduction of the NPN transistor inside the device and affect the device reliability; the doping concentration design of the source protection region 3 is to transfer the low potential to the P-type well region inside the device, so that the N-type source region 41 - P-type well region 4 - source protection region 3 - drift layer 2 structure of the device cannot conduct, improving the UIS resistance of the device; The doping concentration of the P-type source region 42 is not only to reduce the contact resistance between the P-type source region 42 and the source metal layer 7, thereby reducing the conduction loss of the parasitic PN junction body diode of the device, but also to ensure that in the P-type source region 42, the diffusion speed of the space charge region towards the gate and source of the device at high drain voltage is reduced; The doping concentration of the P-type well region 4 is to reduce the gate control charge of the device gate, improve the switching speed of the device, and also to form a buffer region between the P-type source region 42 and the N-type source region 41, thereby reducing the electric field strength near the N-type source region 41 and improving the reliability of the device near the N-type source region 41; The thickness of the silicon carbide substrate 1 of the device is 1 μm, the thickness of the drift layer 2 is 50 - 100 μm, which can be adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the gate protection region 21 is 1 μm, and the top of it is 10 μm away from the bottom of the source protection region 3. The thickness design of the gate protection region 21 is to ensure the protection ability of the structure for the gate of the device. The distance between the gate protection region 21 and the source protection region 3 is designed to avoid affecting the conductive channel of the device while keeping the ion implantation depth as shallow as possible to reduce the manufacturing difficulty. The thickness of the shunt region 22 is 1.5 times that of the gate protection region 21, and the lower side of the shunt region 22 is flush with the lower side of the gate protection region 21. Such a structure can transfer the potential from the lower side of the gate protection region 21 to the upper side of the gate protection region 21, thus ensuring that the parasitic body diode does not conduct. The thickness relationship between the shunt region 22 and the gate protection region 21 can reduce the body resistance of the device and the conduction loss. The thickness of the source protection region 3 is 500 nm, which is to ensure the protection efficiency for the source of the device. The thickness of the P-type well region 4 is 600 nm, and the thicknesses of the N-type source region 41 and the P-type source region 42 are 300 nm. The thickness of the device insulating dielectric layer 5 is 50 nm.

[0034] The width of the P-type source region 42 of the device is 1 μm, the width of the N-type source region 41 is 500 nm, and the width of the P-type well region 4 is 1.8 μm. The width design of the P-type source region 42 is to ensure the freewheeling ability of the body diode of the device. The width of the N-type source region 41 only needs to ensure a low-resistance ohmic contact with the source metal layer 7, and its width has a relatively small impact on the characteristics of the device. The width of the P-type well region 4 forms a gate control structure based on the P-type source region 42 and the N-type source region 41. The width of the source protection region 3 is 1.8 μm to ensure the complete transfer of the potential to the P-type well region 4. The width of the device insulating dielectric layer 5 is 2.7 μm, which is distributed in the middle of the device. The width of the device gate metal layer 6 is 2.6 μm, which is to ensure the gate control ability of the device and the manufacturing margin of the gate structure. The thickness of the device gate metal layer 6 is 250 nm, the thickness of the source metal layer 7 is 300 nm, the width of the shunt region 22 is 1.8 μm, and the width of the gate protection region 21 is 2 μm. On the basis of not affecting the device characteristics, the shunt region 22 can be fabricated using the same photolithography mask as the source protection region 3, reducing the process cost.

[0035] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method of a high-UIS reliability planar-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a gate protection region; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a shunt region; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a source protection region; ground the source protection region; Step 5: Perform ion implantation again to form a P-type well region, and form a raised portion on the drift layer; Step 6: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type source region; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form an insulating dielectric layer; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form a gate metal layer; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, deposit to form a source metal layer, and remove the blocking layer to complete the preparation.

2. The preparation method of a high-UIS reliability planar-gate silicon carbide VDMOS according to claim 1, wherein: The width of the gate protection region is equal to the width of the raised portion, and the gate protection region is located directly below the raised portion.

3. The manufacturing method of a high-UIS-reliability planar-gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the gate protection region is less than the thickness of the shunt region, and the lower side of the gate protection region and the lower side of the shunt region are in the same plane.

4. The manufacturing method of a high-UIS-reliability planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the gate protection region is less than the doping concentration of the shunt region.

5. The manufacturing method of a high-UIS-reliability planar-gate silicon carbide VDMOS as claimed in claim 1, wherein: The width of the shunt region is equal to the width of the source protection region, and the shunt region is located directly below the source protection region.

6. The manufacturing method of a high-UIS reliability planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the source protection region is greater than the doping concentration of the drift layer, and the doping concentration of the source protection region is greater than the doping concentration of the P-type well region.

7. The manufacturing method of a high-UIS reliability planar-gate silicon carbide VDMOS according to claim 1, wherein: The doping concentration of the P-type well region is less than the doping concentration of the drift layer.

8. The manufacturing method of a high-UIS-reliability planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, the drift layer, and the shunt region are N-type; the gate protection region and the source protection region are P-type.

9. A high-UIS reliability planar-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 8.

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