High-reliability planar gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a first P-type region, a second P-type region, a P-type well region, a gate protection region, a protruding part and an N-type source region are formed; forming a barrier layer again, etching to obtain a first P-type source region, a second P-type source region and a groove, and depositing to form a Schottky metal layer, a first protruding part, a second protruding part, a gate metal layer and an insulating dielectric layer; and depositing metal to form a source metal layer, thereby improving the reliability when the drain electrode of the device bears voltage.

Description

Technical Field

[0001] The present invention relates to a highly reliable planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Due to its wide bandgap characteristics, compared with silicon VDMOS devices, silicon carbide VDMOS devices naturally have the characteristics of low gate charge and high switching speed. However, due to the characteristics of silicon carbide materials, there are two problems. One is that the quality of its insulating medium silicon dioxide is relatively reduced, which will affect the gate reliability of the device. The other is that only when the insulating medium is relatively thick can the gate reliability be ensured, but the gate control ability will decrease. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a highly reliable planar gate silicon carbide VDMOS and a preparation method thereof, so as to improve the reliability when the device withstands voltage at the drain.

[0004] In a first aspect, the present invention provides a preparation method of a highly reliable planar gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type region I; Step 3: Remove the blocking layer in Step 2, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type region II; Step 4: Remove the blocking layer in Step 3, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to respectively form a P-type well region, a gate protection region, and a protrusion; Step 5: Remove the blocking layer in Step 4, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 6: Remove the blocking layer in Step 5, re-form a blocking layer, etch the blocking layer to form a through hole, and etch the P-type region I and the drift layer to obtain a first P-type source region, a second P-type source region, and a groove, and deposit to form a Schottky metal layer; Step 7: Remove the blocking layer in Step 6, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit to form a first insulating layer; Step 8: Remove the blocking layer in Step 7, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a first protrusion and a second protrusion; Step 9: Remove the blocking layer in Step 8, re-form a blocking layer, etch the blocking layer to form a through hole, and deposit to form a second insulating layer; Step 10: Remove the barrier layer in Step 9, reform the barrier layer, etch the barrier layer to form a via hole, deposit metal, and form a gate metal layer; Step 11: Remove the barrier layer in Step 10, reform the barrier layer, etch the barrier layer to form a via hole, deposit to form a third insulating layer, and the insulating dielectric layer includes a first insulating layer, a second insulating layer, and a third insulating layer; Step 12: Remove the barrier layer in Step 11, deposit metal, and form a source metal layer.

[0005] In a second aspect, the present invention provides a highly reliable planar-gate silicon carbide VDMOS, which is prepared by using the preparation method of a highly reliable planar-gate silicon carbide VDMOS described in the first aspect.

[0006] The advantages of the present invention are as follows: 1. The present invention constructs a structure in which the second P-type source region wraps the P-type well region, and the P-type well region wraps the N-type source region. Under the condition that the drain bears a large voltage, the electric field intensity near the gate and source of the device can be gradually reduced, thereby improving the reliability of the device; 2. The present invention constructs a first protrusion and a second protrusion, and the widths of the P-type well regions between the lower N-type source region and the protrusion are equal, which can achieve good gate control ability. There is a thick insulating dielectric layer under the gate metal layer, which can improve the reliability of the device gate. There is a P-type gate protection region corresponding to it with the same doping concentration and thickness as the P-type well region, which can improve the gate reliability of the device when the drain of the device bears a large voltage; 3. An insulating dielectric is covered on the top of the gate metal layer of the device, and a source metal layer is covered on the top of the insulating dielectric, which can improve the ability of the device top to withstand external impacts; 4. A structure in which the first P-type source region - Schottky metal layer - second P-type source region is staggered is constructed in the body diode region of the device. The Schottky diode and the parasitic pn junction diode jointly provide freewheeling, and both the freewheeling ability and the conduction loss of the body diode are reduced; the depth of the Schottky diode of the device is greater than the thickness of the first P-type source region, which is to increase the contact surface of the Schottky diode and improve the freewheeling ability of the Schottky diode, and improve the low conduction loss of the body diode on the basis of ensuring the breakdown voltage of the device. Description of the Drawings

[0007] The following further describes the present invention with reference to the accompanying drawings in conjunction with embodiments.

[0008] Figure 1 It is a schematic diagram of a highly reliable planar-gate silicon carbide VDMOS of the present invention.

[0009] Figure 2 It is a process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 1 .

[0010] Figure 3 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 2 。

[0011] Figure 4 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 3 。

[0012] Figure 5 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 4 。

[0013] Figure 6 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 5 。

[0014] Figure 7 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 6 。

[0015] Figure 8 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 7 。

[0016] Figure 9 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 8 。

[0017] Figure 10 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 9 。

[0018] Figure 11 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 10 。

[0019] Figure 12 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 10 One.

[0020] Figure 13 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 10 Two.

[0021] Figure 14 Process cross-section of a highly reliable planar-gate silicon carbide VDMOS of the present invention Figure 10 Three. Detailed implementation manners

[0022] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0024] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "in contact with", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0025] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0026] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0027] As Figures 1 to 14 shown, an embodiment of the present application provides a method for preparing a highly reliable planar-gate silicon carbide VDMOS, including the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2; Step 2: Form a blocking layer 100 above the drift layer 2, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type region I 200; Step 3: Remove the blocking layer 100 in Step 2, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form a P-type region II 300; Step 4: Remove the blocking layer 100 in Step 3, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to respectively form a P-type well region 51, a gate protection region 211, and a protrusion 21; Step 5: Remove the blocking layer 100 in Step 4, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and perform ion implantation to form an N-type source region 511; Step 6: Remove the blocking layer 100 in Step 5, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and etch the P-type region I 200 and the drift layer 2 to obtain a first P-type source region 3, a second P-type source region 5, and a groove 22, and deposit to form a Schottky metal layer 4; Step 7: Remove the blocking layer 100 in Step 6, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit to form a first insulating layer 62; Step 8: Remove the blocking layer 100 in Step 7, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit metal to form a first protrusion 71 and a second protrusion 72; Step 9: Remove the blocking layer 100 in Step 8, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit to form a second insulating layer 63; Step 10: Remove the blocking layer 100 in Step 9, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, and deposit metal to form a gate metal layer 7; Step 11: Remove the blocking layer 100 in Step 10, reform the blocking layer 100, etch the blocking layer 100 to form a through hole, deposit to form a third insulating layer 64, and the insulating dielectric layer 6 includes a first insulating layer 62, a second insulating layer 63, and a third insulating layer 64; Step 12: Remove the blocking layer 100 in Step 11, deposit metal, and form a source metal layer 8.

[0028] In this embodiment, preferably, a first protrusion 71 and a second protrusion 72 are provided below the gate metal layer 7; the first protrusion 71 and the second protrusion 72 are directly above the P-type well region 51 between the protrusion 21 and the N-type source region 511, the width of the first protrusion 71 is equal to the width of the second protrusion 72, and the width of the first protrusion 71 is equal to the distance between the protrusion 21 and the N-type source region 511.

[0029] In this embodiment, preferably, the doping concentration of the first P-type source region 3 is greater than the doping concentration of the drift layer 2; the doping concentration of the second P-type source region 5 is greater than the doping concentration of the P-type well region 51; the doping concentration of the first P-type source region 3 is equal to the doping concentration of the second P-type source region 5.

[0030] In this embodiment, preferably, the doping concentration of the P-type well region 51 is less than the doping concentration of the N-type source region 511.

[0031] In this embodiment, preferably, the thickness of the gate protection region 211 is equal to the thickness of the P-type well region 51.

[0032] As Figure 1 shown, the planar-gate silicon carbide VDMOS obtained by the above manufacturing method includes: A silicon carbide substrate 1; A drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a protrusion 21 and a groove 22 are provided on the drift layer 2; a gate protection region 211 is provided on the protrusion 21; A first P-type source region 3, the lower side of the first P-type source region 3 is connected to the upper side of the drift layer 2; A Schottky metal layer 4, the lower part of the Schottky metal layer 4 is disposed in the groove 22, and the inner side of the first P-type source region 3 is connected to the outer side of the Schottky metal layer 4; A second P-type source region 5, the lower side of the second P-type source region 5 is connected to the upper side of the drift layer 2, the outer side of the second P-type source region 5 is connected to the inner side of the Schottky metal layer 4, a P-type well region 51 is provided on the second P-type source region 5, an N-type source region 511 is provided on the P-type well region 51, and the inner sides of the second P-type source region 5 and the P-type well region 51 are both connected to the outer side of the protrusion 21; An insulating dielectric layer 6, the lower side of the insulating dielectric layer 6 is respectively connected to the upper side of the N-type source region 511, the upper side of the P-type well region 51, the upper side of the convex portion 21, and the upper side of the gate protection region 211; a hollow groove 61 is provided in the insulating dielectric layer 6; A gate metal layer 7, the gate metal layer 7 is disposed in the hollow groove 61; A source metal layer 8, the source metal layer 8 is respectively connected to the first P-type source region 3, the Schottky metal layer 4, the second P-type source region 5, the P-type well region 51, and the N-type source region 511; And a drain metal layer 9, the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1.

[0033] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 6-10e16 cm -3 , the doping concentration of the P-type well region 51 is 1-5e15 cm -3 , the doping concentrations of the first P-type source region 3 and the second P-type source region 5 are 1-5e19 cm -3 , the material of the insulating dielectric layer 6 can be silicon dioxide, and the doping concentration of the N-type source region 511 is 2-8e18 cm -3 ; the doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a trade-off between the reverse breakdown voltage and the on-resistance of the device, and the doping concentration of the first P-type source region 3 is to reduce the contact resistance between the first P-type source region 3 and the source metal layer 8, thereby reducing the conduction loss of the parasitic pn junction body diode of the device; the doping concentration of the second P-type source region 5 is to reduce the diffusion speed when the space charge region at high drain voltage diffuses towards the gate and source of the device; the doping concentration of the P-type well region 51 is to reduce the gate control charge of the device gate, improve the switching speed of the device, and form a buffer region between the second P-type source region 5 and the N-type source region 511, thereby reducing the electric field strength near the N-type source region 511 and improving the reliability near the N-type source region 511 of the device; The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, and the thickness of the N-type drift layer 2 is 50 - 100 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the insulating medium below the first protrusion 71 and the second protrusion 72 is 50 nm, which is to ensure the gate control ability of the device. The thickness of the insulating medium below the gate metal layer 7 is 200 nm, which is to ensure the reliability of the middle region of the device gate and at the same time reduce the gate-drain capacitance of the device and improve the switching speed of the device. The width of the insulating medium on the left and right sides of the gate metal layer 7 is 500 nm, which is to achieve isolation from the source metal layer 8, and its width does not affect the device characteristics. The maximum thickness of the first P-type source region 3 and the second P-type source region 5 is 600 nm, the thickness of the N-type source region 511 is 150 nm, the maximum thickness of the P-type well region 51 is 300 nm, and the thickness of the Schottky metal layer 4 is 800 nm, which is to improve the Schottky metal contact surface, improve the freewheeling ability of the Schottky diode, and reduce the freewheeling loss of the body diode. The widths of the first protrusion 71 and the second protrusion 72 are both 500 nm, and the thicknesses are both 250 nm. The width of the gate metal layer 7 is 3 μm, the thickness in the middle of the gate metal layer 7 is 100 nm, the maximum thickness of the source metal layer 8 is 600 nm, the widths of the Schottky metal layer 4 and the first P-type source region 3 are both 500 nm, the width of the N-type source region 511 is 500 nm, the width of the P-type well region inside the N-type source region 511 is 500 nm, and the width of the P-type gate protection region 211 is 1 μm, which is to ensure the conductive channel of the device while protecting the gate metal layer 7 of the device.

[0034] The present invention constructs a structure in which the second P-type source region 5 wraps the P-type well region 51, and the P-type well region 51 wraps the N-type source region 511. Under the condition that the drain bears a large voltage, the electric field intensity near the gate and source of the device can be gradually reduced, thereby improving the reliability of the device; The present invention constructs the first protrusion 71 and the second protrusion 72, and the width of the P-type well region 51 between them and the underlying N-type source region 511 and the protrusion 21 is equal, which can achieve good gate control ability. There is a thick insulating medium below the gate metal layer 7, which can improve the reliability of the device gate. The corresponding P-type gate protection region 211 with the same doping concentration and thickness as the P-type well region 51 below it can improve the gate reliability of the device when the drain of the device bears a large voltage; An insulating medium is covered on the top of the gate metal layer 7 of the device, and a source metal layer 8 is covered on the top of the insulating medium, which can improve the ability of the device top to withstand external impacts; A structure with an interleaved arrangement of a first P-type source region 3, a Schottky metal layer 4, and a second P-type source region 5 is constructed in the body diode region of the device. The Schottky diode and the parasitic pn junction diode share the freewheeling function, reducing both the freewheeling ability and the conduction loss of the body diode. The depth of the Schottky diode in the device should be greater than the thickness of the first P-type source region 3, which is to increase the contact surface of the Schottky diode and improve its freewheeling ability, thereby reducing the conduction loss of the body diode while ensuring the breakdown voltage of the device.

[0035] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative only and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope of the claims of the present invention.

Claims

1. A preparation method of a highly reliable planar-gate silicon carbide VDMOS, characterized in that: It includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type region I; Step 3: Remove the blocking layer in Step 2, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type region II; Step 4: Remove the blocking layer in Step 3, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P-type well region, a gate protection region, and a protrusion respectively; Step 5: Remove the blocking layer in Step 4, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form an N-type source region; Step 6: Remove the blocking layer in Step 5, reform the blocking layer, etch the blocking layer to form a through hole, and etch the P-type region I and the drift layer to obtain a first P-type source region, a second P-type source region, and a groove, and deposit to form a Schottky metal layer; Step 7: Remove the blocking layer in Step 6, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form a first insulating layer; Step 8: Remove the blocking layer in Step 7, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a first protrusion and a second protrusion; Step 9: Remove the blocking layer in Step 8, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form a second insulating layer; Step 10: Remove the blocking layer in Step 9, reform the blocking layer, etch the blocking layer to form a through hole, and deposit metal to form a gate metal layer; Step 11: Remove the blocking layer in Step 10, reform the blocking layer, etch the blocking layer to form a through hole, and deposit to form a third insulating layer. The insulating dielectric layer includes the first insulating layer, the second insulating layer, and the third insulating layer; Step 12: Remove the blocking layer in Step 11, deposit metal to form a source metal layer.

2. The manufacturing method of a highly reliable planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The first protrusion and the second protrusion are directly above the P-type well region between the protrusion and the N-type source region. The width of the first protrusion is equal to the width of the second protrusion, and the width of the first protrusion is equal to the distance between the protrusion and the N-type source region.

3. The manufacturing method of a highly reliable planar-gate silicon carbide VDMOS as claimed in claim 1, wherein: The doping concentration of the first P-type source region is greater than the doping concentration of the drift layer; the doping concentration of the second P-type source region is greater than the doping concentration of the P-type well region; the doping concentration of the first P-type source region is equal to the doping concentration of the second P-type source region.

4. The manufacturing method of a highly reliable planar-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type well region is less than the doping concentration of the N-type source region.

5. The manufacturing method of a highly reliable planar-gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the gate protection region is equal to the thickness of the P-type well region.

6. A highly reliable planar-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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