Silicon carbide semiconductor device and method for manufacturing same

Abstract

The present application relates to a silicon carbide semiconductor device and a method for manufacturing the same. The silicon carbide semiconductor device includes: a silicon carbide substrate formed of silicon carbide of a first conductivity type; a drift layer formed on the first surface of the silicon carbide substrate from silicon carbide of the first conductivity type, and a plurality of bulk layers formed on the drift layer from silicon carbide of the second conductivity type; a plurality of source layers composed of silicon carbide of the first conductivity type; a gate insulating film in contact with the body layer and the source layer; a gate capacitor; an interlayer insulating film covering the gate electrode and the gate insulating film; and a source wiring electrode covering the source electrode and the interlayer insulating film, the source wiring electrode including a first layer composed of a polycrystalline metal having an average particle diameter of greater than 1 [mu] m and a second layer composed of a polycrystalline metal having an average particle diameter of less than 0.1 [mu] m. Thus, it is possible to prevent hydrogen ions from reaching a channel region through the source wiring electrode while preventing voids from being generated in the source wiring electrode, thereby improving the reliability of the silicon carbide semiconductor device.

Description

Technical Field

[0001] This application relates to semiconductor technology, and particularly to a silicon carbide semiconductor device and a manufacturing method thereof. Background Art

[0002] Compared with semiconductor devices using silicon (Si) as a substrate, semiconductor devices using silicon carbide (SiC) as a substrate and a drift layer (epitaxial layer) can achieve higher breakdown voltage, lower loss, and higher speed, and are thus used in, for example, power semiconductor devices.

[0003] For example, a SiC-MOSFET as a silicon carbide semiconductor device is disclosed in Patent Document [Japanese Unexamined Patent Application Publication No. 2021-93496]. It is pointed out in Non-Patent Document 1 [DOI 10.1109 / JEDS.2021.3109347, Journal of the Institute of Electrical and Electronics Engineers, Inc. Electron Devices Society] that in a trench-type power SiC-MOSFET, when hydrogen ions (H+) enter the device, it will affect the reliability of the HTRB (High Temperature Reverse Bias) test. As a countermeasure, an interlayer insulating film material with a high phosphorus concentration can adsorb hydrogen ions, thereby preventing hydrogen ions from entering the interior of the semiconductor device and improving the reliability of the semiconductor device. It is also pointed out in another Non-Patent Document 2 ["Grain Boundary Effect on Hydrogen Diffusion in Pure Aluminum", Acta Materialia, JIM, Vol. 32, No. 12 (1991), pp. 1109 to 1114] that when the average grain size of aluminum is small, the hydrogen diffusion rate (hydrogen permeability) tends to decrease. Figure 10 Fig. shows a cross-sectional view of a side-by-side state of a silicon carbide semiconductor device 100 as the minimum unit structure of a conventional planar SiC-MOSFET. The silicon carbide semiconductor device 100 includes a silicon carbide substrate 102, a drift layer 103, a source wiring electrode 111, a source electrode 110, a gate insulating film 107, a gate electrode 108, an interlayer insulating film 109, a body layer 104, a source layer 105, a body contact layer 106, and a drain electrode 112. In addition, the silicon carbide semiconductor device 100 is encapsulated with a resin 114 together with a wiring 113 on the source wiring electrode 111 provided by wire bonding. As Figure 10As shown, in a silicon carbide semiconductor device 100 such as a SiC-MOSFET, hydrogen ions precipitated from the resin 114 used for the package enter the channel region of the body layer 104 through the source wiring electrode 111, the gate electrode 108, and the gate insulating film 107, resulting in a decrease in the reliability of the HTRB (High Temperature Reverse Bias) test and possibly causing changes in the gate threshold voltage (Vth) and an increase in leakage current of the silicon carbide semiconductor device 100. Therefore, it is advantageous to prevent hydrogen ions from reaching the channel region. To improve the reliability of the semiconductor device, Non-Patent Document 2 points out that the penetration of hydrogen ions can be suppressed by reducing the grain size of aluminum in the source wiring electrode. However, when the source wiring electrode 111 is deposited at a low temperature, voids are likely to be generated during the deposition of the source wiring electrode 111, especially in the vicinity of the region 120 between the adjacent interlayer insulating films 109 in Figure 10 due to the step between the interlayer insulating film 109 and the source electrode 110, voids are likely to occur during the deposition process. Therefore, it is difficult to deposit the wiring electrode 111 at a low temperature. Summary of the Invention

[0004] This application is made to overcome the above problems. The object of this application is to provide a silicon carbide semiconductor device that can prevent voids from being generated in the source wiring electrode and prevent hydrogen ions from reaching the channel region through the source wiring electrode, thereby improving the reliability of the semiconductor device.

[0005] In a first aspect, in an embodiment of this application, a silicon carbide semiconductor device is provided, including: A silicon carbide substrate formed of silicon carbide of a first conductivity type; A drift layer formed of silicon carbide of a first conductivity type on the first surface of the silicon carbide substrate; A plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer; A plurality of source layers formed of silicon carbide of a first conductivity type and having a doping concentration higher than that of the drift layer on each of the plurality of body layers; A gate insulating film formed in contact with the body layer and the source layer; A gate electrode formed on the gate insulating film; An interlayer insulating film covering the gate electrode and the gate insulating film; A source electrode formed on the source layer; A source wiring electrode covering the source electrode and the interlayer insulating film; The source wiring electrode includes a first layer composed of polycrystalline metal with an average particle size of 1 μm or more, and a second layer formed on the first layer and composed of polycrystalline metal with an average particle size of 0.1 μm or less.

[0006] Second aspect, in the embodiments of the present application, a manufacturing method of a silicon carbide semiconductor device is provided, and the method steps include: A step of forming a drift layer on a silicon carbide substrate; A step of forming a body layer and a source layer on the drift layer by ion implantation; A step of forming a gate insulating film in contact with the body layer and the source layer; A step of forming a gate electrode on the gate insulating film; A step of forming an interlayer insulating film covering the gate electrode; A step of forming a source electrode covering the source layer; A step of forming a source wiring electrode covering the interlayer insulating film and the source electrode; The step of forming the source wiring electrode includes: a step of forming a first layer made of aluminum at a temperature above 350 °C and below 550 °C by a deposition method; a step of forming a second layer made of aluminum at a temperature above 0 °C and below 250 °C.

[0007] According to the silicon carbide semiconductor device and its manufacturing method provided by the embodiments of the present application, since in the source wiring electrode of the silicon carbide semiconductor device, a second layer made of polycrystalline metal with an average grain size less than 0.1 μm is provided, the hydrogen permeation rate of the second layer is relatively low, which can prevent or inhibit hydrogen ions precipitated from the resin from reaching the channel region through the second layer, thereby preventing the reliability degradation caused by hydrogen ions and ensuring the long-term reliability of the silicon carbide semiconductor device. Therefore, problems such as the reliability degradation, the change of the gate threshold voltage (Vth), and the increase of the leakage current in the HTRB (High Temperature Reverse Bias) test caused by hydrogen ions reaching the channel region can be prevented, and the reliability of the silicon carbide semiconductor device can be improved. In addition, the first layer on the side of the silicon carbide substrate is made of polycrystalline metal with an average grain size greater than 1 μm, so the source wiring electrode can be deposited at a conventional temperature, and no voids will be generated due to low-temperature deposition during the manufacturing process. Therefore, the embodiments of the present application can achieve a low hydrogen ion permeation rate to ensure the long-term reliability of the device, and at the same time can prevent the generation of voids during the manufacturing process.

[0008] Details of one or more embodiments of the present application are set forth in the following drawings and description, so that other features, objects, and advantages of the present application can be more clearly understood. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application.

[0010] Figure 1 is a plan view showing an outline of a semiconductor chip having a first embodiment of the silicon carbide semiconductor device of the present application; Figure 2 is a cross-sectional view showing a first embodiment of the silicon carbide semiconductor device of the present application; Figure 3 is showing Figure 2 a cross-sectional view of a part of the manufacturing process of the planar MOSFET shown; Figure 4 is showing Figure 2 a cross-sectional view of a part of the manufacturing process of the planar MOSFET shown; Figure 5 is showing Figure 2 a cross-sectional view of a part of the manufacturing process of the planar MOSFET shown; Figure 6 is showing Figure 2 a cross-sectional view of a part of the manufacturing process of the planar MOSFET shown; Figure 7 is showing Figure 2 a cross-sectional view of a part of the manufacturing process of the planar MOSFET shown; Figure 8 is showing Figure 2 a cross-sectional view of a part of the manufacturing process of the planar MOSFET shown; Figure 9 is a cross-sectional view showing a second embodiment of the silicon carbide semiconductor device of the present application; Figure 10 is a cross-sectional view showing an existing silicon carbide semiconductor device.

[0011] 1 - semiconductor device; 2 - silicon carbide substrate; 3 - drift layer; 4 - body layer; 5 - source layer; 6 - body contact layer; 7 - gate insulating film; 8 - gate electrode; 9 - interlayer insulating film; 10 - source electrode; 12 - drain electrode; 13 - wiring; 13a - ball bonding; 14 - resin; 15 - source wiring electrode; 16 - first layer; 17 - second layer; 19 - conductive barrier layer; 30 - first surface; 31 - second surface; 50 - semiconductor chip; 51 - source pad; 52 - gate pad. Detailed Embodiments

[0012] For a clearer understanding of the purpose, technical solution and advantages of the present application, the present application is described and illustrated below with reference to the accompanying drawings and embodiments.

[0013] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by those of ordinary skill in the technical field to which this application belongs. In this application, words such as "a", "an", "one", "the", "these", etc. do not indicate a limitation in quantity and can be singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The terms "connect", "couple", etc. used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" used in this application means two or more. "And / or" describes the relationship between associated objects and indicates that three relationships may exist. For example, "A and / or B" may mean: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. used in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0014] In the embodiments described below, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type can also be set to p-type and the second conductivity type can be set to n-type.

[0015] In addition, with regard to words indicating directions such as up, down, left, right, side, inner, outer, etc., based on Figure 1 explanation is made, so it may be different from the direction of the actual product. In addition, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the thickness ratio of each layer, etc. may be different from the actual situation. In addition, there may also be differences in the dimensional relationships and ratios between the drawings.

[0016] First Embodiment: An example of the silicon carbide semiconductor device of this application is described as the first embodiment. Figure 1It is a plan view showing the semiconductor chip 50 of the silicon carbide semiconductor device 1 according to the present embodiment. The shape of the semiconductor chip 50 is, for example, rectangular in a plan view. Active pads 51 and gate pads 52 are provided on the plane of the semiconductor chip, and element regions not shown in the plan view are arranged thereunder. In these element regions, multiple silicon carbide semiconductor devices 1 (cells of MOSFET) as the minimum unit structure are arranged. The source pads 51 are electrically connected to the source electrodes of the respective silicon carbide semiconductor devices 1, and the gate pads 52 are electrically connected to the gate electrodes of the respective silicon carbide semiconductor devices 1. In addition, the source pads 51 and the gate pads 52 are each connected to a wiring (not shown) by wire bonding. It should be noted that the source pads 51 and the gate pads 52 are examples and may actually be different from the present embodiment. A drain pad is provided on the bottom surface (not shown) of the semiconductor chip, and the drain pad is electrically connected to the drain electrode of each silicon carbide semiconductor device 1.

[0017] Figure 2 A cross-sectional view showing two juxtaposed silicon carbide semiconductor devices 1 as the minimum unit structure is shown, Figure 2 in which the silicon carbide semiconductor device 1 and Figure 1 the multiple silicon carbide semiconductor devices inside the semiconductor chip shown are the same.

[0018] Figure 2 The silicon carbide semiconductor device 1 in

[0019] includes a silicon carbide substrate 2, a drift layer 3, a body layer 4, a source layer 5, a body contact layer 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, a source electrode 10, a source wiring electrode 15, and a drain electrode 12.

[0019] As Figure 2 shown, a planar MOSFET is formed on the n+-type silicon carbide substrate 2. The silicon carbide substrate 2 has a first surface 30 on the upper side and a second surface 31 on the lower side in Figure 2 . The impurity concentration of the n+-type silicon carbide substrate 2 is higher than that of the n-type drift layer 3 described later. The thickness of the silicon carbide substrate 2 is approximately 350 μm for a 6-inch wafer and approximately 500 μm for an 8-inch wafer, but before forming the drain electrode 12 described later, it may be thinned to about 100 - 200 μm in order to improve heat dissipation.

[0020] On the first surface 30 of the silicon carbide substrate 2 ( Figure 2 the upper surface in ), an n-type drift layer 3 formed by epitaxial growth is formed. The impurity concentration of the n-type drift layer 3 is lower than that of the silicon carbide substrate 2, and the thickness is 5 - 20 μm. Nitrogen, for example, is used as the n-type impurity in the n-type drift layer 3.

[0021] On the side where the upper surface of the n-type drift layer 3 is located (the surface opposite to the silicon carbide substrate 2), two p-type body layers 4 are formed and arranged at intervals. The thickness of the body layer 4 is approximately 1 μm. The p-type body layer 4 is formed by ion implantation of, for example, aluminum. The body layer 4 forms a connected structure between two adjacent silicon carbide semiconductor devices 1.

[0022] Near the upper surface of the drift layer 3 within each p-type body layer 4, an n+-type source layer 5 with a high impurity concentration is provided. The impurity concentration of the n+-type source layer 5 is higher than that of the n-type drift layer 3, and the thickness is approximately 0.3 - 0.4 μm. Inside the p-type body layer 4 near the upper surface of the drift layer, a p+-type body contact layer 6 is provided outside the n+-type source layer 5. The body contact layer 6 is provided between two adjacent silicon carbide semiconductor devices 1, and its impurity concentration is higher than that of the p-type body layer 4.

[0023] The body layer 4 is located between the n+-type source layer 5 and the drift layer 3 and is in contact with the gate insulating film 7. The gate insulating film 7 covers the drift layer 3, the body layer 4, and the source layer 5, and a gate electrode 8 is provided above it. The gate electrode 8 is made of, for example, polysilicon implanted with n-type impurities [such as phosphorus (P)]. In addition, the gate electrode 8 is electrically connected to the gate pad 52 of the semiconductor chip through a contact hole (not shown because it is different from the Figure 2 cross-section) provided in the interlayer insulating film 9 to the external wiring.

[0024] A part of the gate insulating film 7 and the gate electrode 8 are covered by the interlayer insulating film 9. One of the functions of the interlayer insulating film 9 is to insulate the gate electrode 8 from other conductive components such as the source wiring electrode 15, for example. The interlayer insulating film 9 is composed of one or more different types of layers. In this embodiment, specifically, for example, the interlayer insulating film 9 is composed of a two-layer structure of a BPSG (Boro-phospho-silicate Glass) film covering the gate electrode 8 and a TEOS (Tetraethyl orthosilicate) oxide film covering the BPSG film. The hydrogen permeability of the interlayer insulating film 9 is lower than that of aluminum or an alloy mainly composed of aluminum, so it also has the function of preventing hydrogen ions from reaching the channel region from the source wiring electrode 15 via the gate insulating film 7.

[0025] The source electrode 10 is formed on the source layer 5 and the body contact layer 6. The source electrode 10 is made of, for example, nickel silicide (NiSi). The source wiring electrode 15 is in contact with and electrically connected to the source electrode 10, and is disposed above the source electrode 10 and the interlayer insulating film 9. The source wiring electrode 15 includes a first layer 16 and a second layer 17. The first layer is disposed on the side closer to the interlayer insulating film 9. The first layer 16 is aluminum or an aluminum alloy as a polycrystalline metal, and is formed by a sputtering deposition method at a temperature of 350°C to 550°C to form a structure with an average grain size greater than 1 μm. The second layer is aluminum or an aluminum alloy as a polycrystalline metal, and is formed by a sputtering deposition method at a temperature of 0°C to 250°C to form a structure with an average grain size of 0.005 μm to 0.1 μm. The temperature during film formation is more preferably 150°C to 250°C. Regarding the average grain size, refer to the symbol I in the Japanese Industrial Standard "JIS G 0551: 2020": "Average line segment length per grain of the test line passing through the grains" standard. Specifically, observe the image of the grains using a microscope, draw a test line with a length of l so that it passes through the grains, find the intersection point P of the test line and the grain boundary, count the number of grains N based on the found intersection point P, and then divide the length l of the test line by the number of grains N to obtain the average value.

[0026] The material of the source wiring electrode 15 (the first layer 16 and the second layer 17) is a polycrystalline metal, such as aluminum, but may also be an alloy mainly composed of aluminum. An alloy mainly composed of aluminum means an alloy in which the total content of components other than aluminum does not exceed 3% by weight, and more preferably an aluminum alloy in which the total content of components other than aluminum is about 1.5% by weight. Alloys mainly composed of aluminum include aluminum-copper-silicon-magnesium (Al-Cu-Si-Mg), aluminum-copper-silicon (Al-Cu-Si), aluminum-silicon-magnesium (Al-Si-Mg), aluminum-copper (Al-Cu), and aluminum-silicon (Al-Si) alloys. In addition, the materials of the first layer 16 and the second layer 17 of the source wiring electrode 15 may be the same polycrystalline metal or different polycrystalline metals.

[0027] On the source wiring electrode 15, the wiring 13 is connected by a ball bond 13a. The material of the wiring 13 is, for example, aluminum or an aluminum-copper alloy (Al-Cu).

[0028] The planar SiC-MOSFET constituting the silicon carbide semiconductor device 1 as described above, in the body layer 4 as described above, the region close to the gate insulating film 7 is the channel region. Through this channel region as the current path, the electron current flows from the source electrode 10 through the source layer 5 and the drift layer 3 to the drain electrode 12. In addition, by controlling the applied voltage of the gate electrode 8, the width of the depletion layer formed in the channel region is controlled, thereby controlling the current flowing through the channel region, and further controlling the current between the source electrode 10 and the drain electrode 12.

[0029] The source wiring electrode 15 of the silicon carbide semiconductor device 1 configured as such includes a first layer 16 and a second layer 17. The second layer 17 is formed of aluminum or an aluminum alloy, which is a polycrystalline metal, by a sputtering deposition method at 0°C to 250°C, and has an average grain size of less than 0.1 μm. Since the smaller the average grain size of aluminum or an aluminum alloy, the lower the hydrogen permeability, this second layer can prevent hydrogen ions precipitated from the resin from reaching the channel region, thereby preventing a decrease in reliability caused by hydrogen ions and improving the reliability of the silicon carbide semiconductor device. In addition, the first layer is formed of aluminum or an aluminum alloy by a sputtering method at 350°C to 550°C, and has an average grain size of greater than 1 μm, so voids are not generated during low-temperature film formation. This makes it possible to prevent a decrease in reliability caused by hydrogen ions and the generation of voids during low-temperature film formation at the same time.

[0030] Manufacturing process of the first embodiment: Through Figures 3 to 8 , the manufacturing process of the silicon carbide semiconductor device 1 of the first embodiment will be described. Figures 3 to 5 Part of the manufacturing process of a single silicon carbide semiconductor device 1 is shown, while Figures 6 to 8 Part of the manufacturing process of two silicon carbide semiconductor devices 1 formed side by side is shown. As Figure 3 shown in (A), first, an n+-type silicon carbide substrate 2 of the first conductivity type is prepared. Then, an n-type drift layer 3 is formed by epitaxial growth on the first surface 30 ( Figure 1 the upper surface on the upper side) of the silicon carbide substrate 2.

[0031] Next, on the surface of the n-type drift layer 3, a mask such as SiO2 is formed by film formation, for example, and a mask 20 is formed by a photolithography process to expose the upper part of a predetermined formation region of the p-type body layer 4. Subsequently, ion implantation of p-type impurity aluminum (Al) is performed from the mask 20. The thickness of the body layer 4 is, for example, 1 μm. In the present embodiment, Al is used as the p-type impurity, but B (boron) or BF2 (boron difluoride) may also be used.

[0032] Next, as Figure 3 shown in (B), by a self-alignment method, a layer of the same material as the mask 20 (for example, SiO2) is laminated on the main surface of the silicon carbide substrate 2, and then an anisotropic etching is performed to form a mask 21 wider than the mask 20. The formed mask 21 exposes the upper part of a predetermined formation region of the n-type source layer 5. Then, ion implantation of an n-type impurity (for example, nitrogen) is performed from the mask 21. In the present embodiment, an n-type impurity such as nitrogen (N) is used, but phosphorus (P) may also be used.

[0033] Next, as Figure 3As shown in (C), after removing the mask 21, a mask 23 such as SiO2 is formed by film formation, and the mask 23 is formed by a photolithography process to expose the upper part of the predetermined formation region of the p+-type body contact layer 6. Subsequently, aluminum (Al) as a p-type impurity is formed into the body contact layer 6 by ion implantation.

[0034] Then, after removing the mask 23, an annealing treatment at, for example, 1600 °C is performed. By this annealing, the p-type body layer 4, the n+-type source layer 5, and the body contact layer 6 are activated.

[0035] Next, as Figure 4 shown in (A), a gate insulating film 7 such as SiO2 is formed. Specifically, SiO2 is formed by thermal oxidation at 900 °C to 1350 °C in the upper region including the body layer 4, the n+-type source layer 5, and the body contact layer 6, and the gate insulating film 7 is patterned using a photoresist as a mask through photolithography and etching processes.

[0036] Then, as Figure 4 shown in (B), a gate electrode 8 is formed on the surface of the gate insulating film 7. Specifically, polysilicon doped with an n-type impurity is deposited, for example, to improve conductivity, and then it is patterned using a photoresist as a mask through photolithography and etching processes to form the gate electrode 8.

[0037] Next, as Figure 4 shown in (C), an interlayer insulating film 9 covering the gate electrode 8 is formed. The interlayer insulating film 9 can be, for example, a single-layer structure formed of BPSG, TEOS, or PSG, or a multi-layer structure. For example, in a double-layer structure of a BPSG insulating film and a TEOS film, a BPSG insulating film can be first formed on the gate electrode 8, and then a TEOS insulating film can be formed thereon. In this case, a BPSG film is first deposited on the entire main surface of the wafer including the gate electrode 8, and then the BPSG film is patterned using a photoresist formed through photolithography and etching as a mask to form the first interlayer insulating film BPSG. Next, a TEOS film is deposited on the first interlayer insulating film BPSG, and the TEOS film is patterned using a photoresist formed through photolithography and etching as a mask to form the TEOS film as the second interlayer insulating film. By performing a reflow process, the upper part of the BPSG film is flattened, and at the same time, as Figure 4 shown in (C), the corners of the interlayer insulating film 9 form arcs. The formation of the arcs can prevent the electric field concentration phenomenon generated at the corners of the interlayer insulating film 9.

[0038] Next, as Figure 5As shown, a source electrode 10 is formed, which is made of nickel silicide (NiSi), for example. Specifically, first, nickel (Ni) is deposited on the main surface of the substrate 2 including the source layer 5 and the upper part of the body contact layer 6 by sputtering. Subsequently, an annealing treatment for alloying is carried out. Specifically, after the nickel (Ni) is deposited, the silicon carbide substrate 2 is heat-treated at 900 °C to 1100 °C for about 5 minutes by laser annealing, for example. Thereby, at least part of the source electrode 10 (the part where the source layer 5 and the body contact layer 6 are in contact with the Ni film) is silicided to form nickel silicide. Then, the unsilicided nickel (Ni) part is removed, thereby forming the source electrode 10 that makes an ohmic contact with the source layer 5 and the body contact layer 6.

[0039] Next, as Figure 6 shown, the first layer 16 of the source wiring electrode 15 is formed. Specifically, the first layer 16 covering the source electrode 10 and the interlayer insulating film 9 is deposited by sputtering in the temperature range of 350 °C to 550 °C. Other conditions of this sputtering process are, for example, using an RF sputtering device, the vacuum pressure is 1 to 10 Pa, the flow rate of argon (Ar) as an inert gas is 5 to 10 sccm, the RF power is 100 to 250 W, and the deposition rate is 1 to 2 nm / s. In addition, the film thickness is controlled by adjusting the sputtering time. As described above, the material of the source wiring electrode 15 can be aluminum (Al) or an alloy mainly composed of aluminum. The thickness of the source wiring electrode 15 is about 5 μm. As Figure 6 shown, the first layer 16 forms a recess 16a at the step between the source electrode 10 and the interlayer insulating film 9. The height difference between the highest point and the lowest point of the recess 16a is smaller than the height difference of the step between the source electrode 10 and the interlayer insulating film 9, and the inclination is relatively gentle. Due to the small height difference of this recess 16a, even when the next second layer 17 is deposited at a relatively low temperature, voids will not be generated due to low-temperature deposition and step effect. That is to say, by forming this recess 16a, the problem of void generation in the source wiring electrode 15 can be solved.

[0040] In this embodiment, the thickness of the source wiring electrode 15 is, for example, 5 μm, the thickness of the first layer 16 is about 2.5 μm, and the thickness of the second layer is 2.5 μm. However, it is important to form a void-free first layer in the range of 350 °C to 550 °C, and after the deposition of the first layer is completed, the height difference of the step between the source electrode 10 and the interlayer insulating film 9 is moderately alleviated by the first layer to such an extent that voids will not be generated even when the second layer is deposited at 0 °C to 250 °C. Therefore, it is not necessary to be limited to the above thickness. For example, as long as the height of the first layer exceeds the height of the interlayer insulating film 9, the remaining part can be used as the second layer, and the second layer can exceed 2.5 μm. If the thickness of the second layer is increased, the time for hydrogen to pass through the second layer can be correspondingly extended.

[0041] Next, as Figure 7As shown, the second layer 17 of the source wiring electrode 15 is formed. Specifically, in the case of covering the first layer 16, the second layer is deposited by sputtering within a temperature range of 0°C to 250°C (more preferably 150°C to 250°C). Other conditions of the sputtering process are, for example, using an RF sputtering device, the vacuum pressure is 1 to 10 Pa, the argon gas flow rate is 5 to 10 sccm, the RF power is 100 to 250 W, and the deposition rate is 1 to 2 nm / s. In addition, the film thickness is controlled by adjusting the sputtering time. As described above, the material of the source wiring electrode 15 can be aluminum (Al) or an alloy mainly composed of aluminum. Not shown is that the first layer 16 and the second layer 17 of the source wiring electrode 15 are etched before installing the wiring 13 connected by wire bonding.

[0042] Next, as Figure 8 shown, a drain electrode 12 is formed on the second surface 31 of the silicon carbide substrate 2, which is composed of, for example, NiSi. The drain electrode 12 is formed by depositing Ni by sputtering and then heating the Ni by laser annealing. As a result, at least part of the Ni is silicided. Next, the unsilicided Ni part is removed to form the drain electrode 12.

[0043] Next, as Figure 8 shown, the wiring 13 is connected to the source wiring electrode 15 (the second layer 17) by ball bonding 13a through wire bonding. The wiring 13 is composed of, for example, an alloy of aluminum (Al) and copper (Cu).

[0044] Next, as Figure 2 shown, the silicon carbide semiconductor device 1 and the wiring 13 are encapsulated (molded) by the resin 14. Specifically, the source wiring electrode 15 side is covered by the resin 14. By this method, the manufacturing of the silicon carbide semiconductor device 1 of the first embodiment of the present application is completed.

[0045] Another example of the present application is the second embodiment, as Figure 9 shown. Figure 9 is a cross-sectional view showing two side-by-side silicon carbide semiconductor devices 1A of the second embodiment. Parts that perform the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 9 The silicon carbide semiconductor device 1A in Figure 2 is a planar SiC-MOSFET. Different from the silicon carbide semiconductor device 1 of the first embodiment ( Figure 2 ), in the second embodiment, a conductive barrier layer 19 is provided between the first layer 16 and the second layer 17 of the source wiring electrode 15.

[0046] The material of the conductive barrier layer 19 is preferably tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN). However, as long as the material of the conductive barrier layer 19 has conductivity and its hydrogen permeation rate is lower than that of aluminum (hydrogen permeation rate: 1×10^-12 [m^-1·s^-1·Pa^-0.5]) of the first layer 16 material of the source wiring electrode 15. Therefore, as the material of the conductive barrier layer 19, any material can be used as long as its resistivity is between 1.6 [μΩ·cm] and 200 [μΩ·cm], and its hydrogen permeation rate is between 1×10^-20 [m^-1·s^-1·Pa^-0.5] and 1×10^-12 [m^-1·s^-1·Pa^-0.5], not limited to the above materials.

[0047] In the second embodiment, similar to the first embodiment, by reducing the particle size of the second layer 17 of the source wiring electrode 15, it becomes difficult for hydrogen ions to pass through, thereby improving the reliability of the silicon carbide semiconductor device 1. In addition, since a conductive barrier layer 19 with a low hydrogen permeation rate is provided, compared with the first embodiment, it is more difficult for hydrogen ions to reach the channel region, thereby further improving the reliability of the silicon carbide semiconductor device.

[0048] Manufacturing process of the second embodiment: For the processes same as those in the first embodiment, the description is omitted. Figure 8 The conductive barrier layer 19 in [the above] is deposited by sputtering to cover the first layer 16 after the first layer 16 of the source wiring electrode 15 is deposited. Specific sputtering conditions are exemplified as follows. When depositing titanium nitride (TiN), an RF sputtering device is used, the substrate temperature is 150 - 250 °C, the inert gases are argon (Ar) and nitrogen (N2), the argon flow rate is 5 [sccm], the nitrogen flow rate is 10 [sccm], the vacuum pressure is 1 - 10 [Pa], the RF power is 100 - 250 [W], and the deposition rate is 0.2 - 2 nm / s. When depositing tantalum nitride (TaN), the target material is replaced with tantalum (Ta). In addition, when depositing tantalum (Ta), the target material is tantalum, and only argon is used as the inert gas with a flow rate of 5 - 10 sccm.

[0049] After the conductive barrier layer 19, the second layer 17 is deposited in the same manner as in the first embodiment.

[0050] In the above embodiments, an example of applying the silicon carbide semiconductor device of the present application to a planar SiC - MOSFET has been explained, but it can also be applied to an IGBT (insulated gate bipolar transistor).

[0051] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of patent protection. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A silicon carbide semiconductor device, characterized in that: include: a silicon carbide substrate formed of silicon carbide of a first conductivity type; a drift layer formed of silicon carbide of a first conductivity type on the first surface of the silicon carbide substrate; a plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer; a plurality of source layers formed of silicon carbide of a first conductivity type and having a higher doping concentration than the drift layer on each of the plurality of body layers; a gate insulating film formed in contact with the body layer and the source layer; a gate electrode formed on the gate insulating film; an interlayer insulating film covering the gate electrode and the gate insulating film; a source electrode formed on the source layer; a source wiring electrode covering the source electrode and the interlayer insulating film; The source wiring electrode includes a first layer made of a polycrystalline metal having an average grain size of 1 μm or more, and a second layer made of a polycrystalline metal having an average grain size of 0.1 μm or less and formed on the first layer.

2. The silicon carbide semiconductor device according to claim 1, wherein: The average grain size of the polycrystalline metal of the second layer is 0.005 μm to 0.1 μm.

3. The silicon carbide semiconductor device according to claim 1, wherein: The first layer and the second layer of the source wiring electrode are made of the same polycrystalline metal.

4. The silicon carbide semiconductor device according to claim 2, wherein: The first layer and the second layer of the source wiring electrode are made of different polycrystalline metals.

5. The silicon carbide semiconductor device according to claim 1, wherein: A conductive barrier layer is formed between the first layer and the second layer.

6. The silicon carbide semiconductor device according to claim 5, wherein: The conductive barrier layer is composed of tantalum, tantalum nitride or titanium nitride.

7. The silicon carbide semiconductor device according to claim 1, wherein: The interlayer insulating film has a lower hydrogen permeability than the source wiring electrode.

8. The silicon carbide semiconductor device according to claim 7, wherein: The interlayer insulating film at least includes: a BPSG film covering the gate electrode, and a TEOS oxide film covering the BPSG film.

9. The silicon carbide semiconductor device according to claim 1, wherein: The first layer forms a recess at a step between the source electrode and the interlayer insulating film, the height difference between the highest point and the lowest point of the recess is smaller than the step height difference between the source electrode and the interlayer insulating film, and the side wall of the recess is inclined.

10. A method for manufacturing a silicon carbide semiconductor device, characterized in that: The method steps include: forming a drift layer on a silicon carbide substrate; forming a body layer and a source layer on the drift layer by ion implantation; forming a gate insulating film in contact with the body layer and the source layer; forming a gate electrode on the gate insulating film; forming an interlayer insulating film covering the gate electrode; forming a source electrode covering the source layer; forming a source wiring electrode covering the interlayer insulating film and the source electrode; The step of forming the source wiring electrode comprises: forming a first layer composed of aluminum at a temperature of 350° C. to 550° C. by a deposition method; A step of forming a second layer made of aluminum at a temperature of 0° C. to 250° C.

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