PMOS (P-channel Metal Oxide Semiconductor) device structure and preparation method thereof
By forming a multi-layer structure with a specific germanium concentration gradient in the PMOS device structure, the germanium concentration distribution is optimized, the problems of lattice mismatch, dislocation and defects are solved, and the performance and reliability of the device are significantly improved, and the high-speed and high-performance requirements are met.
Patent Information
- Application Number
- CN202510442961.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2025-06-27
AI Technical Summary
In the existing PMOS device structure, due to the sharp changes in the content of germanium atoms at the interface between silicon and SiGe, lattice mismatch, dislocation and defects, limiting the improvement of hole mobility and affecting the long-term reliability of the device.
By forming a multi-layer structure with a specific germanium concentration gradient on the substrate, a pre-set seed layer is introduced at the bottom of the source and drain trench, a germanium-silicon seed layer is arranged on the side walls and bottom surfaces of the trench, and a germanium-silicon body layer is formed on its surface. The germanium concentration increases from low to high, optimizing the germanium concentration distribution and reducing dislocations and defects caused by lattice mismatch.
It effectively improves the operating speed and response performance of the PMOS device structure, improves the reliability and stability of the device, and promotes the improvement of hole mobility, meeting the demand for high-speed and high-performance devices of integrated circuits.
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Figure CN120224735A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular, to a PMOS device structure and a manufacturing method thereof. Background Art
[0002] With the continuous progress of integrated circuit technology, the size of devices has been gradually miniaturized, and the requirements for their operating speed and reliability have also been increasing day by day. Against this background, the embedded silicon germanium technology has emerged, aiming to improve the hole mobility in PMOS devices. This technology usually selectively epitaxially grows germanium silicon (SiGe) in the source and drain regions to introduce strain in the channel region, thereby optimizing device performance.
[0003] However, due to the sharp change in the germanium (Ge) atom content at the silicon (Si) and SiGe interface, dislocations and defects formed at this interface due to factors such as lattice matching result in a reduction in the compressive stress in the channel, thus limiting the effective improvement of hole mobility. The lattice mismatch phenomenon also exacerbates the formation of defects in SiGe, and these defects not only affect the electrical performance of the device but also pose a threat to the long-term reliability of the device.
[0004] Therefore, it is urgent to improve the existing PMOS device structure to effectively solve the above defects, thereby significantly improving the performance and quality of SiGe-related devices.
[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present application, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention
[0006] Based on this, the embodiments of the present application provide a PMOS device structure and a manufacturing method thereof, which can optimize the distribution of germanium concentration, reduce dislocations and defects caused by lattice mismatch, and improve the operating speed and response performance of the PMOS device structure.
[0007] According to some embodiments, on the one hand, the present application provides a PMOS device structure, including:
[0008] A substrate, on which a gate structure is formed, and source-drain trenches are opened on the surface of the substrate on at least one side of the gate structure;
[0009] A pre-seed layer, located in the substrate at the bottom of the source-drain trench;
[0010] A germanium silicon seed layer, located on the sidewalls and bottom surfaces of the source-drain trench;
[0011] A germanium silicon main layer, filling the source-drain trench on the surface of the germanium silicon seed layer;
[0012] Among them, the germanium concentration of the pre - deposited seed layer and the germanium concentration of the germanium - silicon seed layer are both less than the germanium concentration in the germanium - silicon main body layer.
[0013] In some embodiments, the germanium concentration of the pre - deposited seed layer is less than the germanium concentration of the germanium - silicon seed layer.
[0014] In some embodiments, the germanium concentration range in the pre - deposited seed layer includes 5% - 10%;
[0015] The germanium concentration range in the germanium - silicon seed layer includes 10% - 30%;
[0016] The germanium concentration range in the germanium - silicon main body layer includes 30% - 50%.
[0017] In some embodiments, the pre - deposited seed layer includes a doped pre - deposited seed layer, and the germanium - silicon seed layer includes a doped germanium - silicon seed layer.
[0018] In some embodiments, the PMOS device structure further includes:
[0019] A capping layer located on the surface of the germanium - silicon main body layer on the side away from the germanium - silicon seed layer.
[0020] In some embodiments, the thicknesses of the pre - deposited seed layer, the germanium - silicon seed layer, and the germanium - silicon main body layer increase gradually layer by layer.
[0021] According to some embodiments, on the other hand, the present application also provides a method for manufacturing a PMOS device structure, including:
[0022] Providing a substrate, on which a gate structure is formed, and source - drain trenches are opened on the surface of the substrate on at least one side of the gate structure;
[0023] Forming a pre - deposited seed layer in the substrate at the bottom of the source - drain trenches;
[0024] Forming a germanium - silicon seed layer on the side walls and bottom surfaces of the source - drain trenches;
[0025] Forming a germanium - silicon main body layer on the surface of the germanium - silicon seed layer to fill the source - drain trenches, where the germanium concentration in the germanium - silicon main body layer is greater than the germanium concentration of the pre - deposited seed layer and also greater than the germanium concentration of the germanium - silicon seed layer.
[0026] In some embodiments, forming a pre - deposited seed layer in the substrate at the bottom of the source - drain trenches includes:
[0027] Using an ion implantation process to implant germanium ions into the substrate at the bottom of the source - drain trenches;
[0028] The substrate at the bottom of the source-drain trench reacts with germanium ions by using a first annealing process to form the preset seed layer.
[0029] In some embodiments, the process temperature range during the execution of the first annealing process includes 600°C to 1000°C.
[0030] In some embodiments, the germanium-silicon seed layer includes a doped germanium-silicon seed layer; after the germanium-silicon seed layer is formed on the sidewalls and bottom surfaces of the source-drain trench, the method for manufacturing the PMOS device structure further includes:
[0031] The doped impurities in the germanium-silicon seed layer are diffused into the preset seed layer by using a second annealing process.
[0032] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application.
[0033] The embodiments of this application can / at least have the following advantages:
[0034] By forming a multi-layer structure with a specific germanium concentration gradient on the substrate in the embodiments of this application, a preset seed layer is introduced into the substrate at the bottom of the source-drain trench, germanium-silicon seed layers are provided on the bottom and sidewalls of the source-drain trench, and the germanium concentration of the preset seed layer and the germanium concentration of the germanium-silicon seed layer are both less than the germanium concentration in the germanium-silicon main layer, optimizing the distribution of the germanium concentration in the PMOS device structure, avoiding dislocations and defects caused by lattice mismatch at the interface between the substrate and the germanium-silicon seed layer, thereby improving the reliability and stability of the device, and at the same time helping to improve the hole mobility in the PMOS device structure, and further improving the response performance of the device.
[0035] Moreover, by providing a preset seed layer in the substrate at the bottom of the source-drain trench and germanium-silicon seed layers on the bottom and sidewall surfaces of the source-drain trench in the embodiments of this application, a smooth transition region can be established before the formation of the germanium-silicon main layer, providing a good growth foundation for the subsequent formation of the germanium-silicon main layer, reducing the generation of dislocations and defects, and thus improving the crystal quality of the germanium-silicon main layer. The high-quality germanium-silicon main layer can further improve the hole mobility in the PMOS device structure, increase the response speed of the device, enabling the device to work more efficiently in practical applications to meet the requirements of integrated circuits for high-speed and high-performance devices.
[0036] Other advantages, objectives, and features of this application will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be learned from the practice of this application. The objectives and other advantages of this application can be achieved and obtained through the following specification. Description of the Drawings
[0037] Other features, objects, and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0038] Figure 1 It is a schematic cross-sectional structure diagram of a PMOS device structure in some embodiments of the present application;
[0039] Figure 2 It is a schematic flow diagram of a method for manufacturing a PMOS device structure in some embodiments of the present application;
[0040] Figure 3 It is a schematic flow diagram of forming a pre-seed layer in some embodiments of the present application;
[0041] Figure 4 It is a schematic cross-sectional structure diagram of the structure obtained after ion implantation in some embodiments of the present application;
[0042] Figure 5 It is a schematic cross-sectional structure diagram of forming a pre-seed layer in some embodiments of the present application;
[0043] Figure 6 It is a schematic cross-sectional structure diagram of forming a germanium-silicon seed layer in some embodiments of the present application.
[0044] Description of reference numerals:
[0045] 110, substrate; 120, gate structure; T, source-drain trench;
[0046] 210, pre-seed layer; 210', germanium ions;
[0047] 310, germanium-silicon seed layer;
[0048] 410, germanium-silicon main layer;
[0049] 510, capping layer. Detailed implementation manners
[0050] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0052] It should be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe processes, these processes should not be limited by these terms, but are merely used to distinguish one process step from another. For example, the first annealing process can be referred to as the second annealing process, and similarly, the second annealing process can be referred to as the first annealing process; the first annealing process and the second annealing process are annealing processes performed in different steps.
[0053] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present disclosure. Although only the components related to the present disclosure are shown in the illustrations and are not drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0054] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the described features, integers, steps, operations, elements, and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups is not excluded. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.
[0055] Embedded silicon germanium technology introduces strain in the channel region by selectively epitaxially growing germanium silicon (SiGe) in the source and drain regions to optimize device performance. However, due to the sharp change in the germanium (Ge) atom content at the silicon (Si) and SiGe interface, dislocations and defects formed at this interface due to factors such as lattice matching result in a reduction in the compressive stress in the channel, thereby limiting the effective improvement of hole mobility. The lattice mismatch phenomenon also exacerbates the formation of defects in SiGe, and these defects not only affect the electrical performance of the device but also pose a threat to the long-term reliability of the device.
[0056] Therefore, it is urgent to improve the existing PMOS device structure to effectively solve the above defects and thus significantly improve the performance and quality of SiGe-related devices.
[0057] Based on this, the present application provides a PMOS device structure and a method for preparing the same, which can optimize the distribution of germanium concentration, reduce dislocations and defects caused by lattice mismatch, and improve the operating speed and response performance of the PMOS device structure. Its detailed content will be elaborated in the subsequent embodiments.
[0058] According to some embodiments, on the one hand, the present application provides a PMOS device structure. Please refer toFigure 1 , the PMOS device structure includes a substrate 110, a pre-seed layer 210, a germanium-silicon seed layer 310, and a germanium-silicon body layer 410.
[0059] A gate structure 120 is formed on the substrate 110, and source-drain trenches T are formed on the surface of the substrate 110 on at least one side of the gate structure 120; the pre-seed layer 210 is located in the substrate 110 at the bottom of the source-drain trench T; the germanium-silicon seed layer 310 is located on the sidewalls and bottom surfaces of the source-drain trench T; the germanium-silicon body layer 410 fills the source-drain trench T on the surface of the germanium-silicon seed layer 310.
[0060] Among them, the germanium concentration of the pre-seed layer 210 and the germanium concentration of the germanium-silicon seed layer 310 are both less than the germanium concentration in the germanium-silicon body layer 410.
[0061] The above PMOS device structure forms a multi-layer structure with a specific germanium concentration gradient on the substrate 110, introduces the pre-seed layer 210 into the substrate 110 at the bottom of the source-drain trench T, sets the germanium-silicon seed layer 310 on the bottom and sidewalls of the source-drain trench T, and the germanium concentration of the pre-seed layer 210 and the germanium concentration of the germanium-silicon seed layer 310 are both less than the germanium concentration in the germanium-silicon body layer 410, optimizing the distribution of the germanium concentration in the PMOS device structure, avoiding dislocations and defects caused by lattice mismatch at the interface between the substrate 110 and the germanium-silicon seed layer 310, thereby improving the reliability and stability of the device, and at the same time helping to improve the hole mobility in the PMOS device structure, and further improving the response performance of the device.
[0062] In some embodiments, the germanium concentration of the pre-seed layer 210 is less than the germanium concentration of the germanium-silicon seed layer 310.
[0063] In the above embodiments, the pre-seed layer 210, as a layer structure formed in the substrate 110, has a lower germanium concentration, making its lattice constant closer to that of the substrate 110, and being able to better achieve lattice matching with the substrate 110, reducing the lattice mismatch between the substrate 110 and the subsequent growth layers (such as the germanium-silicon seed layer 310 and the germanium-silicon body layer 410). The germanium concentration of the germanium-silicon seed layer 310 is relatively high. On the basis of the pre-seed layer 210, it further transitions to the high germanium concentration of the germanium-silicon body layer 410, forming a germanium concentration gradient from low to high, and realizing the gradual increase of the germanium concentration layer by layer from bottom to top.
[0064] Thus, in the above PMOS device structure, the germanium concentration gradient is relatively gentle, which can effectively reduce the problems of dislocations and lattice mismatch caused by the sharp change of the germanium concentration, thereby reducing the generation of defects at the interface and being beneficial to improving the overall crystal quality. At the same time, the transition of the germanium concentration gradient from low to high can also avoid the sudden change of the compressive stress in the channel caused by the sharp change of the germanium concentration, thereby further improving the hole mobility and being beneficial to improving the electrical performance of the PMOS device.
[0065] In the embodiments of the present application, the germanium concentration ranges in the preset seed layer 210, the germanium-silicon seed layer 310, and the germanium-silicon main body layer 410 are not specifically limited. The germanium concentrations of the above layers can be adaptively adjusted according to actual requirements, as long as the germanium concentration of the preset seed layer 210 and the germanium concentration of the germanium-silicon seed layer 310 are both less than the germanium concentration in the germanium-silicon main body layer 410. It can be understood that the adjustment ranges of the germanium concentrations of the above layers can be adaptively selected according to different process requirements and device performance targets to achieve the best device performance and manufacturing efficiency.
[0066] In some embodiments, the germanium concentration range in the preset seed layer 210 includes 5% to 10%, the germanium concentration range in the germanium-silicon seed layer 310 includes 10% to 30%, and the germanium concentration range in the germanium-silicon main body layer 410 includes 30% to 50%.
[0067] In the above embodiments, the germanium concentration of the preset seed layer 210 is controlled between 5% and 10%, and its lattice constant is closer to that of the substrate 110, so that better lattice matching with the substrate 110 can be achieved, and dislocations caused by lattice mismatch can be reduced. The germanium concentration of the germanium-silicon seed layer 310 is controlled between a relatively high 10% and 30%, and further transitions to the high germanium concentration of the germanium-silicon main body layer 410, such as 30% to 50%, so as to form a gentle germanium concentration gradient, avoid the lattice mismatch problem caused by a sharp change in germanium concentration, reduce the dislocation density at the interface, and thus improve the overall crystal quality.
[0068] Moreover, by forming a gentle germanium concentration gradient through the preset seed layer 210 and the germanium-silicon seed layer 310, the sudden change in the channel internal compressive stress caused by a sharp change in germanium concentration can be avoided. At the same time, the high germanium concentration of the germanium-silicon main body layer 410 can introduce appropriate compressive stress in the channel region, thereby improving the hole mobility and further improving the electrical performance of the PMOS device.
[0069] For example, the germanium concentration in the preset seed layer 210 can be 5%, 8%, 10%, etc. For example, the germanium concentration range in the germanium-silicon seed layer 310 can be 10%, 15%, 20%, 25%, 30%, etc. For another example, the germanium concentration range in the germanium-silicon main body layer 410 can be 30%, 35%, 40%, 45%, 50%, etc. Selections can be made according to the fact that the germanium concentration of the preset seed layer 210 and the germanium concentration of the germanium-silicon seed layer 310 are both less than the germanium concentration in the germanium-silicon main body layer 410, but it is not limited thereto.
[0070] To form a PMOS device structure, in some embodiments, the seed layer 210 includes a doped seed layer 210, and the germania-silicon seed layer 310 includes a doped germania-silicon seed layer 310, thereby performing P-type doping on the seed layer 210 and the germania-silicon seed layer 310.
[0071] By introducing P-type doping into the seed layer 210 and the germania-silicon seed layer 310, the carrier concentration can be precisely controlled to ensure that the seed layer 210 and the germania-silicon seed layer 310 achieve the target electrical properties, thereby improving the overall performance of the PMOS device structure. In the above embodiments, the doped seed layer 210 and the germania-silicon seed layer 310 can reduce the source-drain resistance and play a positive role in promoting the hole mobility, thereby further improving the response speed of the device.
[0072] As an example, the concentration range of the doped impurities in the doped germania-silicon seed layer 310 includes 5×10 8 atoms / cm 3 ~5×10 19 atoms / cm 3 . For example, the concentration range of the doped impurities in the doped germania-silicon seed layer 310 is 5×10 8 atoms / cm 3 , 5×10 10 atoms / cm 3 , 5×10 12 atoms / cm 3 , 5×10 15 atoms / cm 3 , 5×10 19 atoms / cm 3 and so on, but not limited thereto.
[0073] Considering that in the semiconductor manufacturing process, the device needs to go through various process steps such as chemical mechanical polishing (CMP), etching, and cleaning, and these processes may cause physical or chemical damage to the surface of the germania-silicon bulk layer 410. In some embodiments, as Figure 1 shown, the PMOS device structure may further include a capping layer 510, which is specifically located on the surface of the germania-silicon bulk layer 410 away from the germania-silicon seed layer 310.
[0074] The capping layer 510 can protect the germania-silicon bulk layer 410 from damage in subsequent processes and avoid adverse effects on the device performance caused by damage to the germania-silicon bulk layer 410. The capping layer 510 can also be used to provide a flatter surface, which helps to reduce interface defects and provides a better interface basis for subsequent processes (such as the deposition of the metal interconnect layer). Thereby, the overall performance and yield of the device are improved.
[0075] Exemplarily, the capping layer 510 can be converted into a metal silicide layer in subsequent processes as the contact metal for the source / drain.
[0076] Please continue to refer to Figure 1 , in some embodiments, the thicknesses of the pre-seed layer 210, the germanium-silicon seed layer 310, and the germanium-silicon body layer 410 increase layer by layer in sequence. Among them, the thinner pre-seed layer 210 can better achieve lattice matching with the substrate 110, while the thicker germanium-silicon body layer 410 helps to achieve a higher hole migration rate, thereby further improving the electrical performance of the device.
[0077] In the embodiments of the present application, the thickness ranges of the pre-seed layer 210, the germanium-silicon seed layer 310, and the germanium-silicon body layer 410 are not specifically limited. The thicknesses of the above layers can be adaptively adjusted according to actual needs to meet different process requirements and device performance goals.
[0078] For example, for applications that require higher mobility, the thickness of the germanium-silicon body layer 410 can be appropriately increased; while for applications that require higher crystal quality, the thicknesses of the pre-seed layer 210 and the germanium-silicon seed layer 310 can be appropriately increased.
[0079] The thickness range of the pre-seed layer 210 can include 0.1 nm to 10 nm, such as 0.1 nm, 1 nm, 5 nm, or 10 nm, etc. The thickness range of the germanium-silicon seed layer 310 can include 1 nm to 50 nm, such as 1 nm, 10 nm, 25 nm, or 50 nm, etc. The thickness range of the germanium-silicon body layer 410 can include 50 nm to 100 nm, such as 50 nm, 60 nm, 75 nm, or 100 nm, etc.
[0080] Based on the same inventive concept, on the other hand, the present application also provides a method for manufacturing a PMOS device structure. Please refer to Figure 2 , the method for manufacturing the PMOS device structure specifically includes the following steps S100 to S200:
[0081] S100: Provide a substrate, on which a gate structure is formed, and source / drain trenches are opened on the substrate surface at least on one side of the gate structure.
[0082] S200: Form a pre-seed layer in the substrate at the bottom of the source / drain trenches.
[0083] S300: Form a germanium-silicon seed layer on the sidewalls and bottom surfaces of the source / drain trenches.
[0084] S400: Form a germanium-silicon bulk layer that fills the source-drain trenches on the surface of the germanium-silicon seed layer. The germanium concentration in the germanium-silicon bulk layer is greater than that of the preset seed layer and also greater than that of the germanium-silicon seed layer. That is, the germanium concentrations of the preset seed layer and the germanium-silicon seed layer are both less than the germanium concentration in the germanium-silicon bulk layer.
[0085] The preparation method of the above PMOS device structure forms a multi-layer structure with a specific germanium concentration gradient on the substrate, introduces a preset seed layer into the substrate at the bottom of the source-drain trenches, sets germanium-silicon seed layers at the bottom and sidewalls of the source-drain trenches, and the germanium concentrations of the preset seed layer and the germanium-silicon seed layer are both less than the germanium concentration in the germanium-silicon bulk layer, optimizing the distribution of the germanium concentration in the PMOS device structure, avoiding dislocations and defects caused by lattice mismatch at the interface between the substrate and the germanium-silicon seed layer, thereby improving the reliability and stability of the device. At the same time, it also helps to improve the hole mobility in the PMOS device structure, and further improves the response performance of the device.
[0086] Moreover, before forming the germanium-silicon bulk layer, the preparation method of the above PMOS device structure sets a preset seed layer in the substrate at the bottom of the source-drain trenches and sets germanium-silicon seed layers on the bottom and sidewall surfaces of the source-drain trenches, establishing a smooth transition region, providing a good growth foundation for the subsequent formation of the germanium-silicon bulk layer, reducing the generation of dislocations and defects, and thus improving the crystal quality of the germanium-silicon bulk layer. The high-quality germanium-silicon bulk layer can further improve the hole mobility in the PMOS device structure, increase the response speed of the device, enable the device to work more efficiently in practical applications, and meet the requirements of integrated circuits for high-speed and high-performance devices.
[0087] Please refer to Figure 3 , in some embodiments, the process of forming the preset seed layer in the substrate at the bottom of the source-drain trenches may specifically include the following steps S210 - S220.
[0088] S210: Inject germanium ions into the substrate at the bottom of the source-drain trenches using an ion implantation process.
[0089] S220: Use a first annealing process to react the substrate at the bottom of the source-drain trenches with the germanium ions to generate a preset seed layer.
[0090] The following combines Figure 1 , Figures 4 to 6 to describe in detail the preparation method of the PMOS device structure provided by the embodiments of the present application.
[0091] In step S100, as Figure 4 shown, provide a substrate 110, on which a gate structure 120 is formed, and source-drain trenches T are opened on the surface of the substrate 110 on at least one side of the gate structure 120.
[0092] Exemplarily, the substrate 110 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination of their material types. The substrate 110 can be a single-layer structure or a multi-layer structure. For example, the substrate 110 can be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a stack of Si and SiC, or a layered substrate of silicon-on-insulator (SOI), etc. Hereinafter, the substrate 110 being a Si substrate will be taken as an example for illustration.
[0093] Exemplarily, the gate structure 120 can adopt a conventional gate structure, for example, it can include a gate conductive layer, a gate dielectric layer, sidewalls, etc.
[0094] It can be understood that the specific structures of the substrate 110 and the gate structure 120 are not the focus of this application, and their structures can also refer to the related art, and will not be further elaborated here.
[0095] As an example, the substrate 110 can be processed by an etching process to form a specific source-drain trench T, which will be used for the subsequent growth of the germanium-silicon seed layer and the germanium-silicon body layer.
[0096] In step S200, as Figures 4 to 5 shown, a pre-seed layer 210 is formed in the substrate 110 at the bottom of the source-drain trench T.
[0097] In some embodiments, the process of forming the pre-seed layer 210 in the substrate 110 at the bottom of the source-drain trench T in step S200 may specifically include step S210 to step S220.
[0098] In step S210, as Figure 4 shown, germanium ions 210' are implanted into the substrate 110 at the bottom of the source-drain trench T by an ion implantation process.
[0099] In step S220, as Figure 5 shown, a first annealing process is used to react the substrate 110 at the bottom of the source-drain trench T with the germanium ions 210' to generate the pre-seed layer 210.
[0100] In step S210, positively charged germanium ions 210' are introduced into the substrate 110 at the bottom of the source-drain trench T by an ion implantation process, and then in step S220, a first annealing process is used to react the germanium ions 210' with Si to generate the pre-seed layer 210.
[0101] The first annealing process in step S220 can also repair the lattice damage that may be caused during the ion implantation process to ensure the crystal quality of the pre-seed layer 210.
[0102] As an example, in the above steps, when performing the ion implantation process, the implantation energy range includes 10 keV to 100 keV, such as 10 keV, 25 keV, 50 keV, 75 keV, or 100 keV, etc.; the ion implantation dose range includes 1×10 10 cm -2 ~1×10 17 cm -2 For example, 1×10 10 cm -2 、1×10 12 cm -2 、1×10 15 cm -2 or 1×10 17 cm -2 etc.; the ion implantation angle range includes 30° to 150°, such as 30°, 60°, 120°, or 150°, etc. It can be understood that the ion implantation process parameters can be adjusted according to the required doping concentration to ensure the uniform formation of the pre-seed layer 210 in the subsequent process.
[0103] As an example, in the above steps, the first annealing process may include a rapid thermal annealing (RTA) process, a laser annealing process, or a furnace annealing process, but is not limited thereto. Exemplarily, when performing the first annealing process, the annealing temperature range may include 800°C to 1200°C, such as 800°C, 1000°C, or 1200°C, etc., to ensure the high-quality formation of the pre-seed layer 210.
[0104] In the embodiments of the present application, the process temperature range when performing the first annealing process is not specifically limited. Specifically, the temperature of the first annealing process can be adaptively adjusted according to actual requirements (such as the type of dopant, doping concentration, and required crystal quality) to ensure the uniform distribution of germanium atoms. By selecting a reasonable process temperature, the annealing effect can be optimized, thereby improving the crystal quality of the pre-seed layer 210 and contributing to further improving the device performance.
[0105] In some embodiments, the process temperature range when performing the first annealing process includes 600°C to 1000°C, such as 600°C, 800°C, or 1000°C, etc. The temperature range of 600°C to 1000°C can ensure the sufficient activation of germanium ions 210' and more effectively react with Si on the outer layer of the inner wall of the source-drain trench T, thereby generating a high-quality and stable pre-seed layer 210.
[0106] In step S300, as Figure 6 shown, a germanium-silicon seed layer 310 is formed on the sidewalls and bottom surfaces of the source-drain trench T.
[0107] Exemplarily, a low-pressure chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process can be used to form the germanium-silicon seed layer 310 on the sidewalls and bottom surface of the source-drain trench T, but it is not limited thereto.
[0108] In some embodiments, the germanium-silicon seed layer 310 includes a doped germanium-silicon seed layer 310. After the doped germanium-silicon seed layer 310 is formed on the sidewalls and bottom surface of the source-drain trench T, a second annealing process can be used to diffuse the doped impurities in the germanium-silicon seed layer 310 into the pre-set seed layer 210.
[0109] In the above preparation method, the undoped pre-set seed layer 210 is first prepared, then the doped germanium-silicon seed layer 310 is formed, and the doped impurities in the germanium-silicon seed layer 310 are diffused into the pre-set seed layer 210 by means of the second annealing process, so that the doped impurities can be evenly distributed in the pre-set seed layer 210 and the germanium-silicon seed layer 310, effectively avoiding the accumulation of doped impurities at the interface between the substrate 110 and the germanium-silicon seed layer 310, which is beneficial to reducing the source-drain resistance and plays a positive role in promoting the hole mobility, thereby improving the response speed and overall performance of the device.
[0110] In addition, the uniform distribution of the doped impurities is also beneficial to reducing the defects and dislocations at the interface, improving the crystal quality, and further improving the reliability and stability of the device.
[0111] Exemplarily, boron can be introduced as a doping element in the germanium-silicon seed layer 310 and the pre-set seed layer 210.
[0112] In step S400, as Figure 1 shown, a germanium-silicon main body layer 410 filling the source-drain trench T is formed on the surface of the germanium-silicon seed layer 310, and the germanium concentration in the germanium-silicon main body layer 410 is greater than the germanium concentration of the pre-set seed layer 210 and at the same time greater than the germanium concentration of the germanium-silicon seed layer 310.
[0113] Exemplarily, a low-pressure chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process can be used to form the germanium-silicon main body layer 410 filling the source-drain trench T on the surface of the germanium-silicon seed layer 310, but it is not limited thereto.
[0114] As an example, the germanium-silicon main body layer 410 includes a doped germanium-silicon main body layer 410. The concentration range of the doped impurities in the doped germanium-silicon main body layer 410 can include 5×10 19 atoms / cm 3 ~5×10 20 atoms / cm 3 ,for example 5×10 19 atoms / cm 3 、1×10 20atoms / cm 3 or 5×10 20 atoms / cm 3 and so on, but not limited thereto.
[0115] It should be noted that the preparation methods of the PMOS device structures in the embodiments of the present application can all be used to prepare the corresponding PMOS device structures. Therefore, the technical features between the method embodiments and the structure embodiments can be mutually replaced and supplemented on the premise of not generating conflicts, so that those skilled in the art can learn the technical content of the present application.
[0116] Various modifications and changes can be made to the present application without departing from the spirit or scope of the present application, which is obvious to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.
[0117] In the description of this specification, the descriptions referring to terms such as "some embodiments", "as an example", "exemplarily", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0118] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0119] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A PMOS device structure, characterized in that: include: A substrate, a gate structure is formed on the substrate, and a source-drain groove is opened on the surface of the substrate on at least one side of the gate structure; A pre-deposited seed layer located in the substrate at the bottom of the source-drain trench; A silicon germanium seed crystal layer, located on the sidewalls and bottom surfaces of the source and drain trenches; A silicon germanium main layer, filled in the source-drain grooves on the surface of the silicon germanium seed crystal layer; The germanium concentration of the preset seed crystal layer and the germanium concentration of the germanium-silicon seed crystal layer are both lower than the germanium concentration in the germanium-silicon main layer.
2. The PMOS device structure according to claim 1, characterized in that: The germanium concentration of the preset seed crystal layer is less than the germanium concentration of the germanium silicon seed crystal layer.
3. The PMOS device structure according to claim 2, characterized in that: The concentration of germanium in the preset seed crystal layer ranges from 5% to 10%; The germanium concentration in the germanium silicon seed crystal layer ranges from 10% to 30%; The germanium concentration in the germanium silicon main layer ranges from 30% to 50%.
4. The PMOS device structure according to claim 1, characterized in that: The pre-seed crystal layer comprises a doped pre-seed crystal layer, and the germanium silicon seed crystal layer comprises a doped germanium silicon seed crystal layer.
5. The PMOS device structure according to claim 1, characterized in that: The PMOS device structure also includes: The cap layer is located on the surface of the silicon germanium main layer at a side away from the silicon germanium seed crystal layer.
6. The PMOS device structure according to claim 1, characterized in that: The thicknesses of the preset seed crystal layer, the silicon germanium seed crystal layer and the silicon germanium main layer are increased layer by layer.
7. A method for preparing a PMOS device structure, characterized in that: include: Providing a substrate, on which a gate structure is formed, and a source-drain groove is opened on the surface of the substrate on at least one side of the gate structure; forming a pre-seed layer in the substrate at the bottom of the source / drain trench; forming a silicon germanium seed crystal layer on the sidewalls and bottom surfaces of the source / drain trench; A silicon germanium main layer filling the source and drain grooves is formed on the surface of the silicon germanium seed layer, wherein the germanium concentration in the silicon germanium main layer is greater than the germanium concentration of the preset seed layer and greater than the germanium concentration of the silicon germanium seed layer.
8. The method for preparing a PMOS device structure according to claim 7, characterized in that: Forming a pre-seed layer in the substrate at the bottom of the source / drain trench, comprising: Implanting germanium ions into the substrate at the bottom of the source-drain trench using an ion implantation process; A first annealing process is used to make the substrate at the bottom of the source / drain trench react with germanium ions to generate the preset seed crystal layer.
9. The method for preparing a PMOS device structure according to claim 8, characterized in that: The process temperature range when performing the first annealing process includes 600° C. to 1000° C.
10. The method for preparing a PMOS device structure according to claim 7, characterized in that: The silicon germanium seed crystal layer comprises a doped silicon germanium seed crystal layer; After forming a silicon germanium seed crystal layer on the sidewalls and bottom surfaces of the source and drain trenches, the method for preparing the PMOS device structure further includes: A second annealing process is used to diffuse the doped impurities in the silicon-germanium seed crystal layer into the preset seed crystal layer.