N-channel asymmetric DEMOS device structure and preparation method thereof

Abstract

According to the N-channel asymmetric DEMOS device structure, the area of a P well pattern is increased, a gate oxide layer, a nitrogen-oxygen-silicon layer and a polysilicon gate are sequentially stacked above a P well, the gate oxide layer structure is changed into a composite structure of the nitrogen-oxygen-silicon layer and a silicon dioxide layer, Si-H bonds and Si dangling bonds in an original gate oxide layer can be converted into firmer Si-N bonds, and the N-channel asymmetric DEMOS device structure is formed. According to the N-type DEMOS device and the manufacturing method thereof, the N-type DEMOS device and the manufacturing method of the N-type DEMOS device, the P trap and the polysilicon gate are connected to form nitrogen-oxygen-silicon, so that the radiation resistance of gate oxide is improved, meanwhile, the active region in the P trap and the polysilicon gate are both connected with the P + active region, an STI thick oxygen region between a high-voltage N-type region and a low-voltage N-type region can be divided, an electric leakage channel generated by the STI thick oxygen after radiation is blocked, and the electric leakage level of the N-type DEMOS device after radiation is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of DEMOS device structures, and relates to an N-channel asymmetric DEMOS device structure and a preparation method thereof. Background Art

[0002] The BCD process is a technology that combines bipolar devices, CMOS devices, and DMOS devices in a single integrated circuit. It combines the high speed and strong driving ability of bipolar transistors, the low power consumption and high integration of CMOS transistors, and the high voltage and large current driving of DMOS transistors. Based on the CMOS platform, integrating the BCD process with the standard CMOS process can provide manufacturing services for products such as high-performance switching power supplies, power management, SPIC, and high-performance drivers widely used in the aerospace field. In the BCD process platform, DMOS devices can be divided into two structures: LDMOS and DEMOS. LDMOS devices have high breakdown voltage, relatively low on-resistance, a threshold voltage higher than that of CMOS devices, and can change the channel width while the channel length is fixed, with strong driving ability. DEMOS devices have high breakdown voltage, large on-resistance, a threshold voltage matching that of CMOS devices, and variable channel width and length. They can be selected according to the module requirements during the circuit design process.

[0003] When the DMOS devices in the BCD process platform are continuously exposed to ionizing radiation (such as χ-rays, γ-rays), the total dose radiation effect will occur. The radiation energy will interact with the electrons in the valence band of the device's silicon dioxide layer, pulling the electrons to the conduction band and generating a hole in the valence band at the same time. Because the mobility of electrons is relatively high, they can be quickly recombined or drift out of the silicon dioxide layer, while the holes accumulate in the area near the silicon-silicon dioxide interface about of the region, generating a large number of interface states and fixed charges, which will lead to phenomena such as the threshold voltage drift and increased leakage current of the DMOS device. In severe cases, it will cause the device to fail. The literature "Radiation Effects in MOS Oxides" (IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL.55, NO.4, AUGUST, page 1838) points out that the relationship between the device threshold drift and the oxide layer thickness is Ta, where T is the oxide layer thickness, and the value of a is generally between 1.5 and 1.8. For oxide layers less than 20nm, the change caused by the total dose radiation can be basically ignored. At the same time, page 1841 points out that the leakage current generated by MOS devices after radiation is mainly divided into two paths. The first is the leakage from the source to the drain of the NMOS device, and the second is the leakage from the source of the NMOS device to the N-well of the PMOS device.

[0004] In the BCD platform, LDMOS devices often adopt a gate-all-around structure, which naturally blocks the first leakage current path and has high radiation resistance. The asymmetric DEMOS uses a strip gate structure, and both the first and second leakage channels exist. In the conventional asymmetric DEMOS, due to the existence of a thick STI oxide region in the P-well, after the N-type DEMOS device undergoes total dose radiation, the N-well and N-type epitaxy connected to the high-voltage N-type active region (drain end) outside the central P-well of the device form a parasitic leakage path with the low-voltage N-type active region (source end) in the P-well.

[0005] In addition, in order to improve the gate oxidation efficiency in the conventional integrated circuit process, DCE (dichloroethylene) gas is introduced during the gate oxide growth process to assist the oxidation growth. The DCE gas contains chlorine element, which will affect the formation of covalent bonds between oxygen and silicon elements, introduce fixed charges and interface states in the gate oxide layer after radiation, and thus affect the threshold voltage and leakage current changes of the N-type DEMOS device after radiation. Summary of the Invention

[0006] The purpose of the present invention is to solve the problem that in the prior art, DEMOS devices are easily affected by radiation effects, resulting in device-induced leakage and threshold voltage drift, and to provide an N-channel asymmetric DEMOS device structure. By adjusting the layout structures of the N-well, P-well, active region, and polysilicon, and modifying the process conditions of gate oxide growth during manufacturing, a nitrogen-oxygen-silicon gate dielectric structure with stronger radiation resistance is formed, overcoming the problems of device-induced leakage and threshold voltage drift.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] An N-channel asymmetric DEMOS device structure includes a P-buried and an N-buried formed side by side;

[0009] Above the P-buried and N-buried, a P-well and an N-well are formed side by side;

[0010] Inside the P-well, a P+ active region and an N+ low-voltage active region are formed. Above the P-well, a gate oxide layer, a nitrogen-oxygen-silicon layer, and a polysilicon gate are sequentially stacked, and sidewalls are formed on both sides of the gate oxide layer;

[0011] The active region and the polysilicon gate inside the P-well are both connected to the P+ active region;

[0012] There are STI regions on both sides of the N-well, and an N+ high-voltage active region is inside the N-well;

[0013] An interlayer dielectric layer is formed on the P-well, STI region, and polysilicon gate.

[0014] A further improvement of the present invention lies in:

[0015] The silicon oxynitride layer is formed after the gate oxide layer is subjected to nitridation annealing, and the silicon oxynitride layer and the gate oxide layer form a composite layer structure.

[0016] The nitridation temperature is 850-925 °C and the time is 20-30 min.

[0017] The thickness of the gate oxide layer is

[0018] The upper end of the sidewall is flush with the upper end of the polysilicon gate.

[0019] There is metal inside the interlayer dielectric layer.

[0020] The width of the connection between the active region inside the P-well and the P+ active region is smaller than the width of the connection between the polysilicon gate and the P+ active region.

[0021] The polysilicon gate is located between the N+ low-voltage active region and the N+ high-voltage active region;

[0022] The N+ high-voltage active region is surrounded inside the P-well.

[0023] An STI region is formed inside the P-well, and the STI region is located between the P+ active region and the N+ low-voltage active region.

[0024] A preparation method for an N-channel asymmetric DEMOS device structure includes the following steps:

[0025] Step 1: Oxidatively grow a silicon dioxide layer on the original silicon wafer;

[0026] Step 2: Photolithograph N buried and P buried on the silicon dioxide layer in sequence;

[0027] Step 3: Deposit an epitaxial layer, and grow silicon dioxide and silicon nitride on the epitaxial layer;

[0028] Step 4: Form an STI region 006 through dry etching;

[0029] Step 5: Perform P-well photolithography and implantation to form a P-well, and perform N-well photolithography and implantation to form an N-well;

[0030] Step 6: Oxidize to generate a gate oxide layer, and form a silicon oxynitride gate after subjecting the gate oxide layer to nitridation annealing;

[0031] Step 7: Deposit polycrystal on the silicon oxynitride gate, and perform photolithography on the polycrystal to form a polysilicon gate;

[0032] Step 8: Deposit silicon dioxide and silicon nitride to form a sidewall oxide layer, and etch the sidewall to form a sidewall;

[0033] Step 9: Perform N-type photolithography and implantation to form an N-type source-drain region;

[0034] Step 10: Perform P-type lithography and implantation to form P-type source / drain regions;

[0035] Step 11: Perform the back-end process flow of the DEMOS device manufacturing process.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The present invention discloses an N-channel asymmetric DEMOS device structure, which increases the P-well pattern area. A gate oxide layer, a silicon oxynitride layer, and a polysilicon gate are sequentially stacked above the P-well. The gate oxide layer structure becomes a composite structure of a silicon oxynitride layer and a silicon dioxide layer, which can convert the Si-H bonds and Si dangling bonds in the original gate oxide layer into more stable Si-N bonds to form silicon oxynitride, thereby improving the radiation resistance of the gate oxide. At the same time, the active region and the polysilicon gate inside the P-well are both connected to the P+ active region, which can separate the STI thick oxide region between the high-voltage N-type region and the low-voltage N-type region. The leakage channel generated by the STI thick oxide after radiation is blocked, reducing the leakage level of the N-type DEMOS device after radiation.

[0038] Further, in the present invention, the silicon oxynitride layer is formed after nitridation annealing of the gate oxide. The silicon oxynitride layer and the gate oxide layer form a composite layer structure to form silicon oxynitride, thereby improving the radiation resistance of the gate oxide and reducing the risk of leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0040] Figure 1 It is a top view of the radiation-hardened N-type DEMOS device disclosed by the present invention;

[0041] Figure 2 It is a cross-sectional view along AA' of the radiation-hardened N-type DEMOS device disclosed by the present invention;

[0042] Figure 3 It is a cross-sectional view along BB' of the radiation-hardened N-type DEMOS device disclosed by the present invention.

[0043] Wherein: 001 - P well, 002 - N well, 003 - P+ active region, 004 - low - voltage N+ active region, 004' - high - voltage N+ active region, 005 - polysilicon gate, 006 - STI region, 007 - gate oxide layer, 008 - sidewall, 009 - interlayer dielectric, 010 - interconnecting metal, 011 - P implant, 012 - N implant, 013 - silicon oxynitride. Detailed implementation manners

[0044] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0045] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0046] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0047] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper", "lower", "horizontal", "inner", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention. In addition, terms such as "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0048] In addition, if the term "horizontal" appears, it does not mean that the component is required to be absolutely horizontal, but it can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but it can be slightly inclined.

[0049] In the description of the embodiments of the present invention, it should also be noted that unless otherwise clearly specified and limited, if the terms "set", "installed", "connected", and "coupled" are used, they should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0050] The following further describes the present invention in detail with reference to the accompanying drawings:

[0051] See Figures 1 to 3 , this embodiment discloses an N-channel asymmetric DEMOS device structure. By adjusting the layout structures of the N-well, P-well, active region, and polysilicon, and modifying the process conditions for gate oxide growth during manufacturing, a nitrogen-oxygen-silicon gate dielectric structure with stronger radiation resistance is formed, which specifically includes the following structures:

[0052] Embodiment 1

[0053] This embodiment discloses an N-channel asymmetric DEMOS device structure, including a P-buried 011 and an N-buried 012 formed in parallel; a P-well 001 and an N-well 002 are formed in parallel above the P-buried 011 and the N-buried 012; a P+ active region 003 and an N+ low-voltage active region 004 are formed inside the P-well 001. Above the P-well 001, a gate oxide layer 007, a nitrogen-oxygen-silicon layer 013, and a polysilicon gate 005 are sequentially stacked. Sidewalls 008 are formed on both sides of the gate oxide layer 007; both the active region inside the P-well 001 and the polysilicon gate 005 are connected to the P+ active region 003; STI regions 006 are provided on both sides of the N-well 002, and an N+ high-voltage active region 004' is inside the N-well 002; an interlayer dielectric layer 009 is formed on the P-well 001, the STI region 006, and the polysilicon gate 005.

[0054] Further, see Figure 1 , from the top view, it can be seen that the P-well 001 surrounds the N+ high-voltage active region 004', and both the upper and lower ends of the polysilicon gate 005 have extension parts that extend until they are connected to the P+ active region 003; moreover, the active region also has extension parts that extend until they are connected to the P+ active region 003. At the same time, the extension part of the polysilicon gate 005 covers the extension part of the active region. This structural layout enables the polysilicon gate 005 and the active region to cooperate to separate the STI thick-oxide region between the high-voltage N-type region and the low-voltage N-type region. The leakage channel generated by the STI thick-oxide after radiation is blocked, thereby reducing the leakage level of the N-type DEMOS device after radiation.

[0055] Specifically, see Figure 1, both the polysilicon gate 005 and the extension of the active region are rectangular. Among them, the width of the extension of the active region is 0.2 μm to 0.3 μm, and the width of the extension of the polysilicon gate 005 is 0.2 μm to 0.3 μm larger than the width of the extension of the active region.

[0056] Further, referring to Figure 2 , the polysilicon gate 005 is located between the N+ low-voltage active region 004 and the N+ high-voltage active region 004'.

[0057] The structure disclosed in this embodiment increases the area of the P-well pattern. A gate oxide layer, a silicon oxynitride layer, and a polysilicon gate are sequentially stacked above the P-well. The gate oxide layer structure becomes a composite structure of a silicon oxynitride layer and a silicon dioxide layer, which can convert the Si-H bonds and Si dangling bonds in the original gate oxide layer into stronger Si-N bonds to form silicon oxynitride, thereby improving the radiation resistance of the gate oxide. At the same time, the active regions and polysilicon gates inside the P-well are both connected to the P+ active region, which can separate the STI thick oxide region between the high-voltage N-type region and the low-voltage N-type region. The leakage channel generated by the STI thick oxide after radiation is blocked, reducing the leakage level of the N-type DEMOS device after radiation.

[0058] Further, in this embodiment, an interlayer dielectric layer 009 is formed on the P-well 001, the STI region 006, and the polysilicon gate 005, and there is metal 010 inside the interlayer dielectric layer 009.

[0059] Further, the upper end of the sidewall 008 in this embodiment is flush with the upper end of the polysilicon gate 005.

[0060] Embodiment 2

[0061] This embodiment discloses an N-channel asymmetric DEMOS device structure, including a P-buried 011 and an N-buried 012 formed side by side; a P-well 001 and an N-well 002 are formed side by side above the P-buried 011 and the N-buried 012; a P+ active region 003 and an N+ low-voltage active region 004 are formed inside the P-well 001. A gate oxide layer 007, a silicon oxynitride layer 013, and a polysilicon gate 005 are sequentially stacked above the P-well 001. Sidewalls 008 are formed on both sides of the gate oxide layer 007; the active regions and the polysilicon gate 005 inside the P-well 001 are both connected to the P+ active region 003; there are STI regions 006 on both sides of the N-well 002, and an N+ high-voltage active region 004' is inside the N-well 002; an interlayer dielectric layer 009 is formed on the P-well 001, the STI region 006, and the polysilicon gate 005. The silicon oxynitride layer 013 is formed after nitridation annealing of the gate oxide layer 007. The silicon oxynitride layer 013 and the gate oxide layer 007 form a composite layer structure. The nitridation temperature is 850 to 925 °C, and the time is 20 to 30 min. The thickness of the gate oxide layer 007 is

[0062] Further, the silicon oxynitride layer 013 is formed after nitridation annealing of the gate oxide layer 007. The silicon oxynitride layer 013 and the gate oxide layer 007 form a composite layer structure. Specifically:

[0063] During the main oxidation process, the auxiliary gas DCE (dichloroethylene) is removed. The temperature of the main process oxidation reaction is generally 800 - 1000 °C, and the thickness of the silicon dioxide gate oxide thick layer is generally After the growth of the gate oxide layer, nitridation annealing is carried out in an atmosphere of nitrogen, nitric oxide or nitrous oxide to form a silicon oxynitride layer. The temperature of nitridation is generally 850 - 925 °C, and the time is 20 - 30 min. The structure area of the oxide layer after growth is as Figure 2 shown. The gate oxide layer structure of the existing conventional device is a single-layer silicon dioxide. After the gate oxide growth process disclosed in this embodiment, the gate oxide layer structure of the radiation-hardened N-type DEMOS device becomes a composite structure of a silicon oxynitride layer and a silicon dioxide layer. Nitridation can convert the Si-H bonds and Si dangling bonds in the original gate oxide layer into stronger Si-N bonds to form silicon oxynitride, thereby improving the radiation resistance of the gate oxide.

[0064] This embodiment also discloses a preparation method of an N-channel asymmetric DEMOS device structure, including the following steps:

[0065] Step 1: Oxidative growth on the original silicon wafer Silicon dioxide layer;

[0066] Step 2: Lithography of the N-well 012 pattern, perform N-well implantation, and remove the photoresist after implantation;

[0067] Step 3: Lithography of the P-well 011 pattern, perform P-well implantation, and remove the photoresist after implantation;

[0068] Step 4: Deposition of the epitaxial layer, and the thickness of the epitaxial layer deposition is 3 - 4 μm;

[0069] Step 5: Oxidative growth on the epitaxial layer Silicon dioxide layer, CVD deposition growth Silicon nitride;

[0070] Step 6: Perform active area lithography according to the active area 004 pattern of the present invention, and the dry etching depth is for shallow trench isolation (STI), and remove the photoresist after etching;

[0071] Step 7: CVD fill the shallow trench isolation, and perform chemical mechanical polishing for planarization with silicon nitride as the stop layer;

[0072] Step 8: Completely strip the silicon nitride;

[0073] Step 9: Perform P-well lithography according to the P-well 001 pattern of the present invention, and perform well implantation for the N-type DEMOS, including P-well implantation, punch-through implantation, and threshold implantation. After implantation, remove the photoresist;

[0074] Step 10: Perform N-well lithography according to the N-well 002 pattern of the present invention, and perform well implantation for the N-type DEMOS, including N-well implantation, punch-through implantation, and threshold implantation. After implantation, remove the photoresist;

[0075] Step 11: According to the oxidation layer growth process of the present invention, form a thin gate oxide of SiO2 by dry oxidation or wet oxidation. Remove the DEC auxiliary gas in the main oxidation process step. After the main process oxidation, perform high-temperature nitridation annealing on the gate dielectric layer at a temperature of 900 °C for 20 min in a nitrogen-containing atmosphere (nitrogen, nitric oxide, or nitrous oxide) to form the silicon oxynitride gate 013 of the present invention; SiO2 thin gate oxide, and perform high-temperature nitridation annealing on the gate dielectric layer at a temperature of 900 °C for 20 min in a nitrogen-containing atmosphere (nitrogen, nitric oxide, or nitrous oxide) after the main process oxidation to form the silicon oxynitride gate 013 of the present invention;

[0076] Step 12: Deposit polycrystalline silicon by CVD and perform implantation doping;

[0077] Step 13: Perform lithography according to the polycrystalline silicon gate 005 pattern of the present invention, and perform etching. After etching, remove the photoresist;

[0078] Step 14: Perform light-doped source / drain lithography and implantation. After implantation, remove the photoresist;

[0079] Step 15: Deposit silicon dioxide and silicon nitride by CVD to form a sidewall oxide layer, and perform sidewall etching to form the polycrystalline silicon gate sidewall 008;

[0080] Step 16: Perform lithography and implantation according to the N-type source / drain 004 pattern. After implantation, remove the photoresist;

[0081] Step 17: Perform lithography and implantation according to the P-type source / drain 003 pattern. After implantation, remove the photoresist;

[0082] Step 18: Deposit Co silicide, perform rapid annealing and cleaning of Co silicide to form silicide on the exposed source / drain regions and the upper surface of the polycrystalline gate;

[0083] Step 19: Formation of the ILD layer 009, including depositing the USG layer, depositing silicon dioxide as the ILD layer, grinding off the silicon dioxide layer by CMP, depositing the PETEOS layer, so that the equivalent ILD thickness on the active region is

[0084] Step 20: Perform ohmic contact hole lithography and etching. After etching, remove the photoresist;

[0085] Step 21: Filling the holes, including sputtering titanium and titanium nitride, CVD deposition tungsten metal layer, chemical mechanical polishing tungsten metal layer;

[0086] Step 22: Formation of Metal 010, including sputtering titanium and titanium nitride, sputtering to form aluminum copper;

[0087] Step 23: Lithography and etching of Metal 010, and removing the photoresist after etching;

[0088] Step 24: Formation of IMD1, including CVD deposition to form silicon oxide, CMP to grind off silicon oxide, CVD deposition silicon oxide;

[0089] Step 25: Lithography and etching of via 1, and removing the photoresist after etching;

[0090] Step 26: Filling of via 1, including sputtering titanium and titanium nitride, CVD deposition tungsten metal layer, chemical mechanical polishing tungsten metal layer;

[0091] Step 27: Sputtering titanium and titanium nitride, sputtering to form aluminum copper metal 2;

[0092] Step 28: Lithography and etching of Metal 2, and removing the photoresist after etching;

[0093] Step 29: Repeat the materials, thickness and process of IMD1 for IMD2 - IMD5, and repeat the materials, thickness and process of Metal 2 for Metal 3 - Metal 6;

[0094] Step 30: CVD deposition to form silicon dioxide / silicon nitride passivation layer;

[0095] Step 31: Lithography and etching of the passivation layer, and removing the photoresist after etching;

[0096] Step 32: Alloying;

[0097] Step 33: Testing and wafer dicing.

[0098] A radiation hardening structure of an N-type DEMOS device in a 0.18μm BCD process platform disclosed in this embodiment. This layout structure can effectively block the first leakage path and the second leakage path caused by radiation effects.

[0099] At the same time, by adjusting the gate oxide growth process, during the gate oxide oxidation process, DEC gas is no longer introduced, and high-temperature nitridation annealing is added to the gate dielectric layer before polysilicon deposition, reducing the defects and traps in the oxide layer, which can further improve the reliability of the gate oxide and reduce the threshold voltage drift of the device after total dose radiation, thereby improving the radiation resistance of the N-type DEMOS device.

[0100] Through the total dose of 500Krad(Si) radiation experiment, it can be obtained that the threshold voltage change of the strengthened asymmetric N-type DEMOS is less than 0.1mV, and the leakage current increase is less than 0.3pA / μm. While for the unstrengthened asymmetric N-type DEMOS, the threshold voltage change is close to 0.25mV, and the leakage current increase is close to 0.9pA / μm. The threshold voltage change of the strengthened asymmetric N-type DEMOS device is smaller, and the increase in leakage current is smaller.

[0101] During the processing, after the gate oxide layer is grown, nitridation annealing is carried out in an atmosphere of nitrogen, nitric oxide or nitrous oxide to form a silicon oxynitride layer. The nitridation temperature is generally 850 - 925°C, and the time is 20 - 30min. The structure area of the oxide layer after growth is as Figure 2 shown. The gate oxide layer structure of the existing conventional device is a single-layer silicon dioxide. After the gate oxide growth process disclosed in this embodiment, the gate oxide layer structure of the radiation-hardened N-type DEMOS device becomes a composite structure of a silicon oxynitride layer and a silicon dioxide layer. Nitridation can convert the Si-H bonds and Si dangling bonds in the original gate oxide layer into stronger Si-N bonds to form silicon oxynitride, thereby improving the radiation resistance of the gate oxide.

[0102] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An N-channel asymmetric DEMOS device structure, characterized in that: Including P buried (011) and N buried (012) formed in parallel; A P well (001) and an N well (002) are formed in parallel above the P buried (011) and the N buried (012); A P+ active region (003) and an N+ low-voltage active region (004) are formed inside the P well (001), a gate oxide layer (007), a silicon oxynitride layer (013) and a polysilicon gate (005) are sequentially stacked above the P well (001), and sidewalls (008) are formed on both sides of the gate oxide layer (007); The active area and the polysilicon gate (005) inside the P well (001) are both connected to the P+ active area (003); There are STI regions (006) on both sides of the N well (002), and there is an N+ high voltage active region (004') inside the N well (002); An interlayer dielectric layer (009) is formed on the P well (001), the STI region (006) and the polysilicon gate (005).

2. An N-channel asymmetric DEMOS device structure according to claim 1, characterized in that: The silicon oxynitride layer (013) is formed after the gate oxide layer (007) is subjected to nitridation annealing, and the silicon oxynitride layer (013) and the gate oxide layer (007) form a composite layer structure.

3. An N-channel asymmetric DEMOS device structure according to claim 2, characterized in that: The nitriding temperature is 850-925° C., and the time is 20-30 minutes.

4. The N-channel asymmetric DEMOS device structure according to claim 2, characterized in that: The thickness of the gate oxide layer (007) is 5. The N-channel asymmetric DEMOS device structure according to claim 1, characterized in that: The upper end of the sidewall (008) is flush with the upper end of the polysilicon gate (005).

6. The N-channel asymmetric DEMOS device structure according to claim 1, characterized in that: The interlayer dielectric layer (009) contains metal (010).

7. The N-channel asymmetric DEMOS device structure according to claim 1, characterized in that: The width of the connection between the active area inside the P well (001) and the P+ active area (003) is smaller than the width of the connection between the polysilicon gate (005) and the P+ active area (003).

8. The N-channel asymmetric DEMOS device structure according to claim 1, characterized in that: The polysilicon gate (005) is located between the N+ low voltage active region (004) and the N+ high voltage active region (004'); The N+ high voltage active region (004') is surrounded inside the P well (001).

9. The N-channel asymmetric DEMOS device structure according to claim 1, characterized in that: An STI region (006) is formed inside the P well (001), and the STI region (006) is located between the P+ active region (003) and the N+ low voltage active region (004).

10. A method for preparing an N-channel asymmetric DEMOS device structure, characterized in that: The following steps are involved: Step 1: Oxidation growth of a silicon dioxide layer on the original silicon wafer; Step 2: Photolithography N buried (012) and P buried (011) on the silicon dioxide layer in sequence; Step 3: depositing an epitaxial layer, and growing silicon dioxide and silicon nitride on the epitaxial layer; Step 4: forming the STI region 006 by dry etching; Step 5: Perform P-well photolithography and implantation to form a P-well (001), and perform N-well photolithography and implantation to form an N-well (002); Step 6: Oxidation generates a gate oxide layer (007), and nitridation annealing is performed on the gate oxide layer (007) to form a nitride-silicon gate (013); Step 7: depositing polycrystalline on the nitride silicon gate (013), and performing photolithography on the polycrystalline to form a polycrystalline silicon gate (005); Step 8: deposit silicon dioxide and silicon nitride to form a sidewall oxide layer, and etch the sidewall to form a sidewall (008); Step 9: Perform N-type photolithography and implantation to form N-type source and drain regions; Step 10: Perform P-type photolithography and implantation to form P-type source and drain regions; Step 11: Carry out the back-end process flow of the DEMOS device manufacturing process.

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