Power semiconductor device with shield gate trench structure and manufacturing method thereof

Abstract

The invention relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a shield gate trench structure and a manufacturing method thereof, and the power semiconductor device comprises a drain electrode located at the bottom, an N + substrate located on the upper end face of the drain electrode, an N-drift region located on the upper end face of the N + substrate, a P-type body region located on the upper end face of the N-drift region, and a source electrode located at the top. By introducing the nano-composite super-junction shielding structure, optimizing the shape and the size of the groove and integrating the micro-nano fin structure and the reconfigurable self-adaptive shielding grid structure, the electric field distribution in the device can be remarkably improved, and the nano-particles in the nano-composite super-junction shielding structure, the P columns and the N columns have a synergistic effect; the reconfigurable self-adaptive shield grid structure adjusts the electric field in real time according to the working state, and the measures effectively relieve the groove electric field aggregation effect, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and specifically to a power semiconductor device with a shielded gate trench structure and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices play a crucial role in modern power electronic systems and are widely used in multiple fields such as new energy vehicles, smart grids, and industrial automation. With the continuous development of power electronic technology, the performance requirements for power semiconductor devices are increasing day by day, such as higher breakdown voltage capabilities, lower on-resistance, faster switching speeds, and better heat dissipation performance, etc.

[0003] Traditional shielded gate trench structure power semiconductor devices have limitations in aspects such as electric field distribution and carrier regulation. The electric field in the drift region is prone to concentration, resulting in difficulty in improving the breakdown voltage of the device; the trench structure has insufficient ability to guide and control carriers, leading to a relatively large on-resistance and high switching losses; at the same time, conventional shielded gates are mostly fixed structures and are difficult to dynamically adjust according to the actual working state of the device. Under complex and variable working conditions, the device performance cannot be fully exerted, restricting the application expansion of power semiconductor devices in more fields. Summary of the Invention

[0004] The purpose of the present invention is to provide a power semiconductor device with a shielded gate trench structure and a manufacturing method thereof to solve the above-mentioned technical defects.

[0005] To achieve the above effects, the technical solution adopted by the present invention is: a power semiconductor device with a shielded gate trench structure, including: a drain located at the bottom, an N+ substrate located on the upper end surface of the drain, an N- drift region located on the upper end surface of the N+ substrate, a P-type body region located on the upper end surface of the N- drift region, and a source located at the top; a nano-composite superjunction shielding structure is provided in the N- drift region, and the nano-composite superjunction shielding structure is composed of a plurality of superjunction units arranged horizontally and equidistantly in the N- drift region. The superjunction unit is composed of a plurality of P-columns and a plurality of N-columns, and a plurality of P-columns and a plurality of N-columns are arranged alternately in the manner of "P-column - N-column - P-column". The distance between adjacent P-columns and N-columns is 0.8 - 2 μm, and nano-particles are attached to the surfaces of the P-columns and N-columns.

[0006] Preferably, the P-column is cylindrical or rectangular. The P-column is doped by ion implantation technology, with a doping concentration of 1017 - 1018 cm-3 and a width of 0.3 - 0.8 μm; the N-column is doped by ion implantation technology, with a doping concentration of 1016 - 1017 cm-3 and a width of 1.5 - 4 μm.

[0007] Preferably, the nanoparticles are one of oxide particles and nitride particles, and the nanoparticles are attached by a chemical vapor deposition process and an atomic layer deposition process; the bottom end of the P column is connected to the source electrode through a metal connection, and the metal connection is formed by depositing a layer of metal film at the bottom end of the P column using a metal sputtering process, and then undergoing a photolithography and etching process; the N column and the main N-drift region N-type doped region are seamlessly connected during the crystal growth process.

[0008] Preferably, a plurality of grooves are provided inside the N-drift region, and the plurality of grooves are alternately distributed between a plurality of super junction units arranged side by side to form a "groove-super junction unit-groove"; the groove adopts a T-shaped groove structure which is wide at the top and narrow at the bottom, the upper width of the groove is 1.5-3μm, and the lower width of the groove is 0.8-1.5μm, and a plurality of micro-nano fins are formed on the inner wall of the groove by photolithography technology, the height of the micro-nano fins is 50-200nm, the width is 20-100nm, and the spacing between adjacent fins is 50-150nm.

[0009] Preferably, an oxide isolation layer is provided on the inner wall of the trench, the thickness of the upper oxide isolation layer is 150-400 nm, the thickness of the lower oxide layer is 80-150 nm, and the interior of the trench is filled with polysilicon.

[0010] Preferably, the groove is processed by dry etching technology, using reactive ion etching. According to the pattern on the photoresist, the etching gas is chemically reacted with the wafer surface material to form the groove. During the etching process, the etching rate and etching selectivity are controlled by controlling parameters such as the type, flow rate, pressure and radio frequency power of the etching gas, and the in-situ monitoring technology is used to monitor the etching depth and sidewall morphology in real time.

[0011] Preferably, a grid plate is provided above the inside of the groove, an insulating sliding layer is provided below the inside of the groove, a shielding grid is provided inside the insulating sliding layer, and the shielding grid is composed of a plurality of independently movable or deformable microstructure units, each of which has a size of 20-50 μm in length, 5-15 μm in width, and 200-500 nm in thickness.

[0012] Preferably, the microstructure unit is made of a semiconductor material with high electron mobility, and the surface of the microstructure unit is coated, and the coating is a conductive coating of a metal-semiconductor-metal structure or a nanocomposite coating with low contact resistance characteristics; the microstructure unit is controlled by a driving mechanism based on micro-electromechanical system technology, and the driving mechanism adopts one or more of electrostatic drive, thermal drive, and electromagnetic drive.

[0013] Preferably, the shielding gate is insulated from the surrounding structures through an insulating sliding layer, which is made of silicon nitride material or silicon oxide material with a thickness of 30 - 80 nm. The insulating sliding layer is prepared by chemical vapor deposition process or atomic layer deposition process, and annealing treatment and surface modification are carried out after deposition.

[0014] Preferably, a manufacturing method for a power semiconductor device with a shielding gate trench structure includes the following steps: Formation of P pillars and N pillars: Prepare a wafer, coat photoresist, lithographically transfer the patterns of P pillars and N pillars, perform ion implantation doping, control the doping concentration of P pillars at 10^17 - 10^18 cm^-3 with a width of 0.3 - 0.8 μm, and the doping concentration of N pillars at 10^16 - 10^17 cm^-3 with a width of 1.5 - 4 μm. Etch out the shape and ensure a spacing of 0.8 - 2 μm; Attachment of nanoparticles: Select one of chemical vapor deposition or atomic layer deposition processes. In the former, nanoparticles are formed through the reaction of precursor gases and controlled to attach uniformly; in the latter, nanoparticles are precisely grown by periodic gas supply. Connection and joining treatment: At the bottom end of the P pillar, form a connection to the source electrode and ground through metal sputtering and lithographic etching, and use crystal growth to seamlessly connect the N pillar with the main body of the N-drift region. T-shaped trench processing: Coat the wafer with photoresist, lithographically transfer the T-shaped trench pattern, and use dry etching technology to chemically react the etching gas with the material on the wafer surface to remove the unnecessary parts and form a T-shaped trench. Formation of micro-nano fins: Pattern through electron beam lithography or extreme ultraviolet lithography, and then use inductively coupled plasma etching to form micro-nano fins on the inner wall of the T-shaped trench. Manufacture of microstructural units: Select a high electron mobility semiconductor material, define the pattern through lithography, etch out the shape, and the microstructural units are controlled by a driving mechanism based on microelectromechanical system technology. Preparation of the insulating sliding layer: Select one of silicon nitride material and silicon oxide material, and prepare the insulating sliding layer by chemical vapor deposition process or atomic layer deposition process, and perform annealing treatment on it after deposition. Overall assembly and testing: Precisely assemble the manufactured components according to the design requirements to form a complete power semiconductor device with a shielding gate trench structure.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. By introducing a nano-composite superjunction shielding structure, optimizing the trench shape and size, integrating a micro-nano fin structure, and a reconfigurable adaptive shielding gate structure, the electric field distribution inside the device can be significantly improved. The nanoparticles in the nano-composite superjunction shielding structure cooperate with the P-columns and N-columns, and the reconfigurable adaptive shielding gate structure adjusts the electric field in real time according to the working state. These measures effectively alleviate the trench electric field concentration effect, make the electric field distribution more uniform, and thus improve the breakdown voltage and reliability of the device.

[0016] 2. Through the combination of T-shaped trenches and micro-nano fin structures, the quality of polysilicon filling is optimized, the electric field intensity at the gate edge is alleviated. At the same time, the micro-nano fins greatly increase the inner wall surface area of the trench, enhance the ability to regulate carriers, guide the carriers to be evenly distributed, further improve the breakdown voltage resistance, reduce the on-resistance, effectively reduce the energy loss of the device, and improve the power conversion efficiency.

[0017] 3. Through the reconfigurable adaptive shielding gate structure, it can provide real-time feedback based on multiple parameters such as electric field, current, and temperature during device operation, and adjust the shape and position of the shielding gate through intelligent algorithms. In different working scenarios, such as high voltage and large current or high-frequency conditions, the electric field distribution can be optimized respectively, the parasitic capacitance can be reduced. Compared with the traditional fixed shielding gate structure, the breakdown voltage and switching speed of the device are effectively improved, the power consumption is reduced. At the same time, through material and surface treatment optimization, the comprehensive performance and service life of the device are further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic cross-sectional structure diagram of a power semiconductor device with a shielding gate trench structure according to an embodiment of the present invention; Figure 2 It is a schematic top view structure diagram of a power semiconductor device with a shielding gate trench structure according to an embodiment of the present invention; Figure 3 It is a schematic diagram of the trench structure in a power semiconductor device with a shielding gate trench structure according to an embodiment of the present invention.

[0020] In the figure, 1. Source electrode; 2. Drain electrode; 3. N+ substrate; 4. N- drift region; 5. P-type body region; 6. P-column; 7. N-column; 8. Trench; 9. Oxide isolation layer; 10. Polysilicon; 11. Gate plate; 12. Micro-nano fin; 13. Shielding gate; 14. Insulating sliding layer. Detailed Implementation Modes

[0021] The present invention will be further explained below in conjunction with the accompanying drawings and specific embodiments.

[0022] Embodiment 1 Please refer to Figures 1 to 3 As shown, this embodiment discloses a power semiconductor device with a shield gate trench structure, including: a drain disposed at the bottom, an N+ substrate disposed on the upper end surface of the drain, an N- drift region disposed on the upper end surface of the N+ substrate, a P-type body region disposed on the upper end surface of the N- drift region, and a source disposed at the top; A nano-composite superjunction shielding structure, the nano-composite superjunction shielding structure is disposed within the N- drift region, and the nano-composite superjunction shielding structure is composed of a plurality of superjunction units arranged horizontally and equidistantly within the N- drift region. The superjunction unit is composed of a plurality of P-columns and a plurality of N-columns, and the plurality of P-columns and the plurality of N-columns are arranged in an alternating manner of "P-column - N-column - P-column", and there is a spacing between adjacent P-columns and N-columns, and the spacing is 0.8 - 2 μm; Specifically, the P-column is cylindrical or rectangular, and is represented by a rectangle in the figure. The P-column is doped by ion implantation technology, and its doping concentration is 1017 - 1018 cm-3, and the width is 0.3 - 0.8 μm; the N-column is also doped by ion implantation technology, and its doping concentration is 1016 - 1017 cm-3, and the width is 1.5 - 4 μm. Regular periodic superjunction units are formed by the alternating arrangement of P-columns and N-columns.

[0023] Furthermore, nano-particles are attached to the surfaces of both the P-column and the N-column, and the nano-particles are one of oxide particles and nitride particles. The method of attaching the nano-particles is one of chemical vapor deposition process and atomic layer deposition process. Specifically, when using the chemical vapor deposition process, a gas containing an oxide or nitride precursor is introduced into the reaction chamber. Under high temperature and specific gas flow conditions, the precursor gas decomposes and undergoes a chemical reaction on the surfaces of the P-column and the N-column to form nano-particles with a particle size of 5 - 20 nm. By controlling parameters such as reaction temperature, gas flow rate, and deposition time, the nano-particles are uniformly and densely attached to the surfaces of the P-column and the N-column. When using atomic layer deposition, by periodically introducing reaction gases and inert gases, the precursor gas undergoes a self-limiting chemical reaction on the surfaces of the P-column and the N-column, and the nano-particles are precisely grown layer by layer, better controlling the particle size and coverage uniformity of the nano-particles.

[0024] Furthermore, the bottom end of the P column is connected to the source electrode. A metal thin film is deposited on the bottom end of the P column by using a metal sputtering process, and then a metal connection line is formed through photolithography and etching processes to connect the P column and the source electrode, achieving grounding; the N column and the main N-type doping region of the N-drift region are seamlessly connected during the crystal growth process. By controlling parameters such as the temperature gradient and impurity concentration of the crystal growth, the perfect fusion of the N column and the main body of the N-drift region at the atomic level is ensured, without additional connection.

[0025] In a specific embodiment, when a voltage is applied to the device, the external electric field acts on the nanocomposite superjunction shielding structure. Due to its unique electronic structure and surface properties, the nanoparticles will have a strong interaction with the carriers in the P column and the N column. From the perspective of quantum mechanics, the electron clouds of the nanoparticles overlap with the electron clouds of the P column and the N column, changing the wave functions of the carriers; the wave functions of the electrons near the nanoparticles will be distorted, resulting in a change in their motion trajectories and increasing the scattering probability of the electrons on the surfaces of the P column and the N column. This scattering causes the electric field lines to bend and spread around the nanoparticles, thereby dispersing the electric field intensity originally concentrated in certain regions and effectively alleviating the electric field concentration phenomenon.

[0026] Under the action of the electric field, the charge transfer between the nanoparticles and the P column and the N column is a dynamic equilibrium process; taking oxide nanoparticles as an example, when electrons are adsorbed on the surface of the nanoparticles, a negative charge layer will be formed on its surface. This negative charge layer will affect the carrier distribution in the surrounding P column and N column through Coulomb force; on the one hand, it will repel the holes in the P column to approach it, and on the other hand, it will attract the electrons in the N column, promoting the redistribution of charges between the P column and the N column. As the charges are redistributed, the electric field distribution will also change accordingly, realizing the dynamic regulation of the electric field. At the same time, the charge transfer rate between the nanoparticles and the P column and the N column will also be affected by factors such as the electric field intensity and temperature. At high electric field intensities, the charge transfer rate increases, enabling a more rapid response to external voltage changes and optimizing the electric field distribution.

[0027] The presence of the nanoparticles significantly enhances the charge coupling efficiency between the P column and the N column. In the traditional superjunction structure, the charge coupling between the P column and the N column mainly depends on the carrier diffusion and drift under the concentration gradient and the electric field. In the nanocomposite superjunction shielding structure, the nanoparticles, as the "bridge" for charge transfer, can accelerate the transfer of carriers between the P column and the N column; the nanoparticles can adsorb the holes in the P column and then quickly transfer the holes to the N column through the change of their own electronic structure, and vice versa. This accelerated charge transfer process enables the P column and the N column to reach the charge balance state in a shorter time, thereby more effectively coordinating and regulating the electric field distribution in the N-drift region.

[0028] Further, a plurality of grooves are provided inside the N-drift region, and the plurality of grooves are alternately distributed between a plurality of superjunction units arranged side by side, forming "groove-superjunction unit-groove"; wherein, the groove adopts a T-shaped groove structure with a wider upper part and a narrower lower part, the upper width of the groove is 1.5 - 3 μm, the lower width of the groove is 0.8 - 1.5 μm, and a plurality of micro-nano fins are formed on the inner wall of the groove by photolithography technology, where the photolithography technology adopts one of electron beam lithography and extreme ultraviolet lithography, the height of the micro-nano fins is 50 - 200 nm, the width is 20 - 100 nm, and the distance between adjacent fins is 50 - 150 nm; the surface area of the inner wall of the groove is increased by the micro-nano fins, the ability to regulate carriers is enhanced, the movement of carriers is guided, and the electric field distribution is optimized.

[0029] Further, an oxidation isolation layer is also provided on the inner wall of the groove, the thickness of the upper oxidation isolation layer is 150 - 400 nm, and the thickness of the lower oxidation layer is 80 - 150 nm. The inside of the groove is filled with polysilicon; the use of the T-shaped groove makes the filling of polysilicon easier, improves the filling quality, and the T-shaped field plate alleviates the electric field intensity from the N-drift region to the gate edge, improving the hot carrier effect.

[0030] It should be further noted that the P-columns and N-columns are perpendicular to the chip surface, and the depths of the P-columns and N-columns are flush with or deeper than the gates provided in the grooves, specifically 80% - 100% of the groove depth.

[0031] Specifically, the processing method of the T-shaped groove is as follows: The dry etching technology is adopted, such as reactive ion etching. According to the pattern on the photoresist, the etching gas reacts chemically with the material on the wafer surface to precisely remove the unnecessary parts and form a T-shaped groove. During the etching process, by controlling parameters such as the type, flow rate, pressure, and radio frequency power of the etching gas, precise control of the etching rate and etching selectivity is achieved. For the case where the thickness of the upper oxidation layer is 150 - 400 nm and the thickness of the lower oxidation layer is 80 - 150 nm, by adjusting the etching parameters, the etching thickness error of the oxidation layer is controlled within ±5 nm to ensure the dimensional accuracy of the T-shaped groove. At the same time, during the etching process, in-situ monitoring technology is adopted to monitor the etching depth and sidewall morphology in real time, and the etching parameters are adjusted in a timely manner to ensure that the sidewalls of the T-shaped groove are vertical and the surface is smooth, avoiding over-etching or under-etching phenomena.

[0032] In a specific embodiment, the upper-wide and lower-narrow structure adopted for the T-shaped groove in the present invention facilitates the polysilicon filling. During the polysilicon filling process, chemical vapor deposition technology is used. Since the upper part of the T-shaped groove is wider, the polysilicon precursor gas is more likely to enter the groove interior and its diffusion in the groove is more uniform. At the same time, the structure of the T-shaped groove helps to reduce the voids and defects generated during the filling process. During the chemical vapor deposition process, by precisely controlling parameters such as reaction temperature, gas flow rate, and pressure, polysilicon can be uniformly deposited in the T-shaped groove, and the filling quality is significantly improved. Compared with the traditional straight groove structure, the polysilicon filling void ratio of the T-shaped groove structure is reduced by more than 50%, effectively improving the electrical performance and reliability of the device.

[0033] The micro-nano fin structure increases the surface area of the groove inner wall and greatly enhances the ability to regulate carriers. Under the action of an electric field, when carriers (electrons or holes) move in the groove, they will interact with the surface of the micro-nano fins. The charge distribution and electric field characteristics on the surface of the micro-nano fins will exert an additional force on the carriers, guiding the movement direction of the carriers. When electrons move in the groove, the positive charges on the surface of the micro-nano fins will attract the electrons, making them approach the surface of the micro-nano fins, thereby changing the movement trajectory of the electrons. In this way, the micro-nano fins can make the distribution of carriers in the groove more uniform and optimize the electric field distribution.

[0034] Furthermore, a gate plate is provided above the interior of the groove, and an insulating sliding layer is also provided below the interior of the groove. A shielding gate is arranged inside the insulating sliding layer. The shielding gate is composed of multiple microstructural units that can move or deform independently, and each microstructural unit is made of a semiconductor material with high electron mobility, specifically, one of silicon carbide or gallium nitride can be used, and a coating treatment is performed on the surface of each microstructural unit. The specific treatment is as follows: depositing a conductive coating with a metal-semiconductor-metal structure or a nano-composite coating with low contact resistance characteristics; through these coatings, the surface electrical properties of the microstructural units can be improved, the contact resistance can be reduced, and the electrical contact performance between the microstructural units and other electrodes can be enhanced. At the same time, the coatings can also improve the corrosion resistance and mechanical stability of the microstructural units, extending the service life of the device. The size of each microstructural unit is 20 - 50 μm in length, 5 - 15 μm in width, and 200 - 500 nm in thickness; among them, these microstructural units are manufactured by semiconductor micro-nano processing technology to ensure dimensional accuracy and performance consistency.

[0035] Specifically, the microstructural units are controlled by a driving mechanism based on microelectromechanical system technology, and the driving mechanism can adopt one or more of electrostatic driving, thermal driving, and electromagnetic driving.

[0036] Electrostatic actuation is achieved by applying a voltage between the microstructural unit and the fixed electrode, and using electrostatic attraction or repulsion to move the microstructural unit. To improve the efficiency and precision of electrostatic actuation, the surfaces of the microstructural unit and the fixed electrode are specially treated, such as depositing an insulating film with a high dielectric constant to enhance the electric field strength. At the same time, by optimizing the shape and layout of the electrodes, precise control of the movement direction and displacement of the microstructural unit is realized.

[0037] Thermal actuation is achieved by heating the microstructural unit or a thermal actuation element near it to expand or contract, thereby generating displacement. The thermal actuation element can be made of a material with a high coefficient of thermal expansion, such as a shape memory alloy or a specific polymer material. During thermal actuation, precise control of the heating current or heating power is used to achieve precise control of the displacement of the microstructural unit.

[0038] Electromagnetic actuation uses electromagnetic force to drive the microstructural unit. A tiny electromagnetic coil or permanent magnet is integrated into the microstructural unit, and electromagnetic force is generated by changes in an external magnetic field or current to drive the microstructural unit to move or deform.

[0039] Furthermore, the shielding gate is insulated from the surrounding structure through an insulating sliding layer, where the insulating sliding layer is made of one of silicon nitride material and silicon oxide material, and the thickness of the insulating sliding layer is 30 - 80 nm; the preparation of the insulating sliding layer uses chemical vapor deposition process or atomic layer deposition process. Taking the chemical vapor deposition process as an example, a mixed gas containing a silicon source gas and a nitrogen source gas (or an oxygen source gas) is introduced into the reaction chamber. Under high temperature and specific gas flow conditions, the gas undergoes a chemical reaction, and an insulating sliding layer is deposited on the contact surface between the shielding gate and the surrounding structure. By controlling parameters such as reaction temperature, gas flow rate, and deposition time, precise control of the thickness and quality of the insulating sliding layer is achieved, with its thickness error controlled within ±5 nm, and ensuring the uniformity and density of the insulating sliding layer.

[0040] To further improve the performance of the insulating sliding layer, annealing treatment is performed on it after deposition to improve the crystal structure and interface quality of the material, reduce the defect density, improve the insulation performance and mechanical strength. At the same time, the surface of the insulating sliding layer is modified by depositing an ultra-thin self-lubricating film to reduce the friction when the shielding gate moves, and improve the smoothness and reliability of its movement.

[0041] Example 2 Specifically, this example also discloses a manufacturing method of a power semiconductor device with a shielding gate trench structure, including the following steps: Formation of P-columns and N-columns: A photoresist is coated on the wafer surface. Lithography technology is used to accurately transfer the patterns of P-columns and N-columns to the photoresist. During lithography, the parameters of the lithography equipment are strictly controlled. For example, the exposure time is accurate to ±0.1 second, and the exposure intensity error is controlled within ±2% to ensure the pattern accuracy and clarity. The P-columns and N-columns are doped using ion implantation technology. The doping concentration of the P-columns is accurately controlled at 10^17 - 10^18 cm^-3, with a width of 0.3 - 0.8 μm; the N-columns are also doped through ion implantation technology, with a doping concentration of 10^16 - 10^17 cm^-3 and a width of 1.5 - 4 μm. Subsequently, through the etching process, the shapes of the P-columns and N-columns are etched according to the photoresist pattern. During the etching process, parameters such as the type, flow rate, pressure, and etching time of the etching gas are precisely controlled to ensure the shape and size accuracy, and the distance between adjacent P-columns and N-columns is maintained at 0.8 - 2 μm to form regular periodic superjunction units; Attachment of nanoparticles: The chemical vapor deposition process or atomic layer deposition process is selected to attach nanoparticles. If the chemical vapor deposition process is used, a gas containing an oxide or nitride precursor is introduced into the reaction chamber. Under high temperature and specific gas flow conditions, the precursor gas decomposes and reacts on the surfaces of the P-columns and N-columns to form nanoparticles with a particle size of 5 - 20 nm. By precisely controlling parameters such as the reaction temperature, gas flow rate, and deposition time, uniform and dense attachment of the nanoparticles is achieved. If the atomic layer deposition process is used, the reaction gas and inert gas are periodically introduced, enabling self-limiting chemical reactions of the precursor gas on the surfaces of the P-columns and N-columns. By precisely controlling parameters such as the introduction time and flow rate of the reaction gas and inert gas, precise control of the particle size and coverage uniformity of the nanoparticles is achieved; Connection and joining treatment: For the connection between the bottom end of the P-column and the source electrode, first, a metal thin film is deposited on the bottom end of the P-column using the metal sputtering process, and then a metal wire is formed through the lithography and etching processes to achieve a reliable connection between the P-column and the source electrode and grounding. During the crystal growth process, parameters such as the temperature gradient and impurity concentration are controlled to enable seamless joining between the N-column and the main N-type doped region of the N-drift region, ensuring perfect atomic-level fusion without additional connection.

[0042] T-shaped groove processing: A photoresist is coated on the surface of the wafer on which the nano-composite superjunction shielding structure has been fabricated. The T-shaped groove pattern is transferred onto the photoresist using photolithography technology. A dry etching technique is employed, and according to the photoresist pattern, chemical reactions occur between the etching gas and the wafer surface material to form the T-shaped groove. During the etching process, parameters such as the type, flow rate, pressure, and radio frequency power of the etching gas are controlled to precisely control the etching rate and etching selectivity. For the case where the upper oxide layer thickness is 150 - 400 nm and the lower oxide layer thickness is 80 - 150 nm, by adjusting the etching parameters, the etching thickness error of the oxide layer is controlled within ±5 nm to ensure the dimensional accuracy of the T-shaped groove. Meanwhile, during the etching process, in-situ monitoring technology is used to monitor the etching depth and sidewall morphology in real time, and the etching parameters are adjusted in a timely manner to ensure that the sidewalls of the T-shaped groove are vertical and the surface is smooth, avoiding over-etching or under-etching phenomena.

[0043] Micro-nano fin formation: Electron beam lithography or extreme ultraviolet lithography technology is used to lithograph the micro-nano fin pattern on the inner wall of the T-shaped groove. Taking electron beam lithography as an example, the exposure dose and scanning path of the electron beam are precisely controlled to lithograph a micro-nano fin pattern with a height of 50 - 200 nm, a width of 20 - 100 nm, and a pitch of 50 - 150 nm on the inner wall of the groove. Then, an inductively coupled plasma etching technique is used to etch the inner wall of the groove according to the lithography pattern to form a micro-nano fin structure. During the etching process, by adjusting the composition and ratio of the etching gas, a mixed gas of fluorine-containing gas and carbon-containing gas is used to achieve precise etching of the micro-nano fins, ensuring the consistency of their shape and size. Meanwhile, by controlling the etching time and etching power, the height and width of the micro-nano fins are precisely controlled to keep their dimensional error within ±5 nm.

[0044] Microstructure unit manufacturing: A semiconductor material with high electron mobility, such as silicon carbide or gallium nitride, is selected as the main material of the microstructure unit. The pattern of the microstructure unit is defined on the wafer using photolithography technology. Extreme ultraviolet lithography or electron beam lithography is used to ensure that the pattern accuracy reaches the nanometer level and the pattern dimensional error is controlled within ±5 nm. One of reactive ion etching or inductively coupled plasma etching is used to precisely etch the shape of the microstructure unit. During the etching process, parameters such as the composition, flow rate, pressure, and radio frequency power of the etching gas are precisely controlled to achieve precise control of the size and shape of the microstructure unit, keeping its dimensional error within ±5 nm. The size of each microstructure unit is 20 - 50 μm in length, 5 - 15 μm in width, and 200 - 500 nm in thickness.

[0045] Drive mechanism integration: According to the design requirements, single or multiple drive methods such as electrostatic drive, thermal drive, and electromagnetic drive can be selected. If electrostatic drive is adopted, a voltage is applied between the microstructural unit and the fixed electrode, and the movement of the microstructural unit is achieved by using electrostatic attraction or repulsion. To improve the efficiency and accuracy of electrostatic drive, the surfaces of the microstructural unit and the fixed electrode are specially treated, such as depositing an insulating film with a high dielectric constant, precisely controlling the film thickness and dielectric constant. At the same time, by optimizing the shape and layout of the electrodes, such as adopting a comb-shaped electrode structure, precisely controlling the tooth pitch and tooth width of the electrodes, precise control of the movement direction and displacement of the microstructural unit is achieved; if thermal drive is adopted, the microstructural unit or the thermal drive element near it expands or contracts by heating, thereby generating displacement. The thermal drive element uses a material with a high coefficient of thermal expansion, such as shape memory alloy or a specific polymer material, precisely controlling the composition ratio of the thermal drive element. During the thermal drive process, by precisely controlling the heating current or heating power, precise control of the displacement of the microstructural unit is achieved, and the displacement accuracy reaches within ±10 nm; if electromagnetic drive is adopted, a tiny electromagnetic coil or permanent magnet is integrated into the microstructural unit, and an electromagnetic force is generated by the change of an external magnetic field or current to drive the microstructural unit to move or deform. A high-performance magnetic material, such as nanocrystalline soft magnetic material, is used as the magnetic core of the electromagnetic coil, precisely controlling the size and magnetic permeability of the magnetic core. At the same time, the design of the electromagnetic coil is optimized, precisely controlling the number of turns and wire diameter of the coil, improving the efficiency and response speed of electromagnetic drive.

[0046] Insulating sliding layer preparation: Materials such as silicon nitride or silicon oxide are selected as the materials for the insulating sliding layer, and the insulating sliding layer is prepared by chemical vapor deposition or atomic layer deposition process. Taking the chemical vapor deposition process as an example, a mixed gas containing a silicon source gas and a nitrogen source gas is introduced into the reaction chamber. Under high temperature and specific gas flow conditions, the gas undergoes a chemical reaction, and an insulating sliding layer is deposited on the contact surface between the shielding gate and the surrounding structure. By precisely controlling parameters such as the reaction temperature, gas flow, and deposition time, precise control of the thickness and quality of the insulating sliding layer is achieved, with its thickness error controlled within ±5 nm, and ensuring the uniformity and denseness of the insulating sliding layer. To further improve the performance of the insulating sliding layer, an annealing treatment is carried out after deposition, precisely controlling parameters such as the annealing temperature and annealing time, improving the crystal structure and interface quality of the material, reducing the defect density, improving the insulation performance and mechanical strength. At the same time, the surface of the insulating sliding layer is modified, such as depositing an ultra-thin self-lubricating film, precisely controlling the film thickness, reducing the friction when the shielding gate moves, and improving the smoothness and reliability of its movement.

[0047] Overall assembly and testing: Assemble the manufactured components precisely according to the design requirements, ensuring that the position accuracy error of each component is controlled within ±5μm to form a complete power semiconductor device with a shielded gate trench structure. Conduct comprehensive performance tests on the assembled device, including electrical performance tests, thermal performance tests, and reliability tests, etc. According to the test results, make necessary adjustments and optimizations to the device to ensure that its performance meets the design requirements and actual application needs.

[0048] Meanwhile, the content not described in detail in this specification belongs to the prior art well-known to those skilled in the art.

[0049] The present invention is not limited to the above optional embodiments, and anyone can obtain other various forms of products under the inspiration of the present invention. The above specific embodiments should not be construed as limiting the protection scope of the present invention, and the protection scope of the present invention should be defined by the claims, and the specification can be used to interpret the claims.

Claims

1. A power semiconductor device having a shield gate trench structure, characterized in that include: A drain at the bottom, an N+ substrate at the upper end surface of the drain, an N-drift region at the upper end surface of the N+ substrate, a P-type body region at the upper end surface of the N-drift region, and a source at the top; a nanocomposite superjunction shielding structure is arranged in the N-drift region, the nanocomposite superjunction shielding structure is composed of a plurality of superjunction units arranged horizontally and equidistantly in the N-drift region, the superjunction unit is composed of a plurality of P columns and a plurality of N columns, and the plurality of P columns and the plurality of N columns are arranged alternately in a "P column-N column-P column" manner, the spacing between adjacent P columns and N columns is 0.8-2μm, and nanoparticles are attached to the surfaces of the P columns and the N columns.

2. The power semiconductor device with a shield gate trench structure according to claim 1, characterized in that, The P column is cylindrical or rectangular, and the P column is doped by ion implantation technology with a doping concentration of 10 17 -10 18 cm -3 , with a width of 0.3 - 0.8 μm; the N column is doped by ion implantation technology with a doping concentration of 10 16 -10 17 cm -3 , with a width of 1.5 - 4 μm.

3. The power semiconductor device with a shield gate trench structure according to claim 1, characterized in that, The nanoparticles are one of oxide particles and nitride particles, and the attachment method of the nanoparticles is one of a chemical vapor deposition process and an atomic layer deposition process; the bottom end of the P column is connected to the source electrode through a metal connection line, and the metal connection line is formed by depositing a layer of metal film at the bottom end of the P column using a metal sputtering process, and then undergoing a photolithography and etching process; the N column and the main N-drift region N-type doped region are seamlessly connected during the crystal growth process.

4. The power semiconductor device with a shield gate trench structure according to claim 1, characterized in that, A plurality of grooves are provided inside the N-drift region, and the plurality of grooves are alternately distributed between a plurality of super junction units arranged side by side to form a "groove-super junction unit-groove"; the groove adopts a T-shaped groove structure which is wide at the top and narrow at the bottom, the upper width of the groove is 1.5-3μm, and the lower width of the groove is 0.8-1.5μm. A plurality of micro-nano fins are formed on the inner wall of the groove by photolithography technology, the height of the micro-nano fins is 50-200nm, the width is 20-100nm, and the spacing between adjacent fins is 50-150nm.

5. The power semiconductor device with a shield gate trench structure according to claim 4, characterized in that, An oxide isolation layer is provided on the inner wall of the trench, the thickness of the upper oxide isolation layer is 150-400nm, the thickness of the lower oxide layer is 80-150nm, and the interior of the trench is filled with polysilicon.

6. The power semiconductor device with a shield gate trench structure according to claim 4, characterized in that, The grooves are processed by dry etching technology, which uses reactive ion etching. According to the pattern on the photoresist, the etching gas is chemically reacted with the wafer surface material to form grooves. During the etching process, the etching rate and etching selectivity are controlled by controlling parameters such as the type, flow rate, pressure and radio frequency power of the etching gas, and the in-situ monitoring technology is used to monitor the etching depth and sidewall morphology in real time.

7. The power semiconductor device with a shield gate trench structure according to claim 4, characterized in that, A grid plate is provided above the inside of the groove, an insulating sliding layer is provided below the inside of the groove, a shielding grid is provided inside the insulating sliding layer, and the shielding grid is composed of a plurality of independently movable or deformable microstructure units, each of which has a size of 20-50 μm in length, 5-15 μm in width, and 200-500 nm in thickness.

8. The power semiconductor device with a shield gate trench structure according to claim 7, characterized in that, The microstructure unit is made of a semiconductor material with high electron mobility, and the surface of the microstructure unit is coated, and the coating is a conductive coating of a metal-semiconductor-metal structure or a nanocomposite coating with low contact resistance characteristics; The microstructure unit is controlled by a driving mechanism based on micro-electromechanical system technology, and the driving mechanism adopts one or more of electrostatic driving, thermal driving, and electromagnetic driving.

9. The power semiconductor device with a shield gate trench structure according to claim 7, characterized in that, The shielding gate is insulated from the surrounding structures through an insulating sliding layer, which is made of silicon nitride material or silicon oxide material with a thickness of 30 - 80 nm. The insulating sliding layer is prepared by chemical vapor deposition process or atomic layer deposition process, and annealing treatment and surface modification are carried out after deposition.

10. A manufacturing method for a power semiconductor device with a shield gate trench structure according to any one of claims 1-9, characterized in that, It includes the following steps: Formation of P-columns and N-columns: Prepare the wafer, apply photoresist, lithographically transfer the patterns of P-columns and N-columns, perform ion implantation doping, and control the doping concentration of P-columns at 10 17 -10 18 cm -3 , with a width of 0.3 - 0.8 μm, and the doping concentration of N-columns at 10 16 -10 17 cm -3 , with a width of 1.5 - 4 μm, etch out the shape, and ensure a spacing of 0.8 - 2 μm; Nanoparticle attachment: Select one of the chemical vapor deposition or atomic layer deposition processes. The former forms nanoparticles through the reaction of precursor gases and controls uniform attachment; the latter precisely grows nanoparticles by periodic gas supply. Connection and joining treatment: At the bottom end of the P pillar, a connection is formed to connect the source electrode to the ground through metal sputtering and photolithographic etching, and the N pillar is seamlessly joined with the N-drift region body by crystal growth. T-shaped trench processing: The wafer is coated with photoresist, and the T-shaped trench pattern is transferred by photolithography. Using dry etching technology, a chemical reaction occurs between the etching gas and the wafer surface material to remove the unnecessary parts and form a T-shaped trench. Micro-nano fin formation: Patterns are drawn by electron beam lithography or extreme ultraviolet lithography, and then inductively coupled plasma etching is used to form micro-nano fins on the inner wall of the T-shaped trench. Microstructure unit manufacturing: Select a high electron mobility semiconductor material, define the pattern by photolithography, dry-etch the shape, and the microstructure unit is controlled by a driving mechanism based on microelectromechanical system technology. Insulating sliding layer preparation: Select one of silicon nitride material and silicon oxide material, and use chemical vapor deposition process or atomic layer deposition process to prepare the insulating sliding layer, and perform annealing treatment on it after deposition. Overall assembly and testing: Assemble the manufactured components precisely according to the design requirements to form a complete power semiconductor device with a shielding gate trench structure.

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