Semiconductor structure and method for forming the same

Abstract

The embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are at least beneficial for improving the isolation performance of the top gate structure. The semiconductor structure includes: a semiconductor substrate, and a top gate structure located on the semiconductor substrate; an isolation structure, which is arranged around the sidewall of the top gate structure; the isolation structure includes: a first protective layer, a first isolation layer, a second protective layer, and a second isolation layer, wherein the first protective layer is arranged around the sidewall of the top gate structure; the first isolation layer is arranged around the sidewall of the first protective layer away from the top gate structure; the second protective layer is arranged around the sidewall of the first isolation layer away from the first protective layer and covers the top of the top gate structure; the second isolation layer is arranged around the sidewall of the second protective layer away from the first isolation layer, and the height of the second isolation layer is lower than the height of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate; and a third protective layer covers the top of the second protective layer and the top of the second isolation layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Semiconductor components are indispensable in many modern applications. Among them, transistors, as an important semiconductor component, are widely used in various fields.

[0003] As electronic technology advances, semiconductor components are becoming smaller and smaller in size. However, when scaling down semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) through various technology nodes, device density and performance are challenged by device layout and required isolation.

[0004] For metal oxide semiconductor field effect transistors formed based on a top gate structure in a memory, the isolation performance of the top gate structure needs to be improved when the size of semiconductor components is further reduced. Summary of the Invention

[0005] The present disclosure provides a semiconductor structure and a method for forming the same, which are at least beneficial to improving the isolation performance of the top gate structure.

[0006] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, comprising: a semiconductor substrate, and a top gate structure located on the semiconductor substrate; an isolation structure, which is arranged around the side wall of the top gate structure; the isolation structure comprises: a first protective layer, a first isolation layer, a second protective layer, and a second isolation layer, wherein the first protective layer is arranged around the side wall of the top gate structure; the first isolation layer is arranged around the side wall of the first protective layer away from the top gate structure; the second protective layer is arranged around the side wall of the first isolation layer away from the first protective layer, and covers the top of the top gate structure; the second isolation layer is arranged around the side wall of the second protective layer away from the first isolation layer, and the height of the second isolation layer is lower than the height of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate; and a third protective layer covers the top of the second protective layer and the top of the second isolation layer.

[0007] In some embodiments, in a direction perpendicular to the sidewall of the top gate structure, the thickness of the first protection layer is 1 nm to 100 nm, the thickness of the first isolation layer is 1 nm to 100 nm, and the thickness of the second protection layer is 1 nm to 100 nm.

[0008] In some embodiments, in a direction perpendicular to the sidewall of the top gate structure, the thickness of the second isolation layer is used to adjust the size of the semiconductor structure.

[0009] In some embodiments, the second isolation layer has a thickness of 0.1 nm to 100 nm.

[0010] In some embodiments, the material of the first isolation layer is the same as the material of the second isolation layer.

[0011] In some embodiments, the material of the first protective layer, the material of the second protective layer, and the material of the third protective layer are the same.

[0012] In some embodiments, the top gate structure includes: a channel layer located on the top of the semiconductor substrate; a gate isolation layer located on the top of a side of the channel layer away from the semiconductor substrate; a gate conductive layer located on the top of a side of the gate isolation layer away from the channel layer; and a gate cap layer located on the top of a side of the gate conductive layer away from the gate conductive layer.

[0013] A second aspect of an embodiment of the present disclosure also provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate and forming a top gate structure on the semiconductor substrate; forming a first protective layer and a first isolation layer, wherein the first protective layer is arranged around the side wall of the top gate structure, and the first isolation layer is arranged around the side wall of the first protective layer away from the top gate structure; depositing to form a second protective layer, wherein the second protective layer is located on the side wall of the first isolation layer away from the first protective layer and covers the top of the top gate structure; forming a second isolation layer, wherein the second isolation layer is located on the side wall of the second protective layer away from the first isolation layer, and in a direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure; forming a third protective layer, wherein the third protective layer covers the top of the second protective layer and the top of the second isolation layer.

[0014] In some embodiments, the method of forming the first protective layer and the first isolation layer includes: depositing a first protective film on the surface of the semiconductor substrate and the top gate structure; depositing a first isolation film on the surface of the first protective film; etching and removing the first protective film and the first isolation film located on the top of the top gate structure and the top of the semiconductor substrate, and the remaining first protective film located on the side wall of the top gate structure forms the first protective layer, and the remaining first isolation film located on the side wall of the first protective layer forms the first isolation layer.

[0015] In some embodiments, the method for forming the second isolation layer includes: depositing a second isolation film on the surface of the second protective layer, and spin coating the surface of the second isolation film to form a carbon coating; etching the carbon coating to expose the top surface of the second isolation film, and etching the second isolation film until the height of the second isolation film is lower than the height of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate, and the remaining second isolation film constitutes the second isolation layer.

[0016] In some embodiments, the method for forming a third protective layer includes: forming a third protective film, wherein the third protective film is located on the top of the second isolation layer and the top of the second protective layer; patterning the third protective film to expose the carbon coating located on the side wall of the second isolation layer; removing the carbon coating; etching the top of the semiconductor substrate and the top gate structure based on an etching process to expose the semiconductor substrate, and the remaining third protective film constitutes the third protective layer.

[0017] In some embodiments, the etching process has an etching selectivity ratio of 3:1 to 10:1 for the second isolation layer and the third protection layer.

[0018] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0019] (1) The sidewall of the top gate structure has a four-layer isolation structure consisting of a first protective layer, a first isolation layer, a second protective layer and a second isolation layer, which has better insulation performance and can effectively prevent ion diffusion in the top gate structure.

[0020] (2) The second protective layer and the third protective layer are also located on the top of the top gate structure to form a "cap-shaped" structure to prevent the top gate structure from being ground back in subsequent processes after the semiconductor structure is formed, and to prevent the etching solution of subsequent processes from remaining in the isolation structure and the gap between the top gate structure and the isolation structure, thereby causing the semiconductor structure to be damaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1A schematic cross-sectional view of a semiconductor substrate and a top gate structure provided in one embodiment of the present disclosure;

[0023] Figure 2 A schematic cross-sectional view of a top gate structure provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic cross-sectional structure diagram of a first protective film and a first isolation film provided in one embodiment of the present disclosure;

[0025] Figure 4 A schematic cross-sectional structure diagram of a first protective layer and a first isolation layer provided in one embodiment of the present disclosure;

[0026] Figure 5 A schematic cross-sectional structure diagram of a second protective layer provided in one embodiment of the present disclosure;

[0027] Figure 6 A schematic cross-sectional view of a second isolation film according to an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of the cross-sectional structure of a carbon coating provided in one embodiment of the present disclosure;

[0029] Figure 8 A schematic cross-sectional view of a second isolation layer according to an embodiment of the present disclosure;

[0030] Figure 9 A schematic cross-sectional view of a third protective film according to an embodiment of the present disclosure;

[0031] Figure 10 A schematic diagram of the cross-sectional structure of the third protective film after the carbon coating is removed according to an embodiment of the present disclosure;

[0032] Figure 11 A schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are used solely to distinguish between different objects and should not be understood to indicate or imply relative importance or to implicitly specify the quantity, specific order, or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present disclosure, "plurality" means more than two, unless otherwise specifically defined.

[0034] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0036] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0037] In the description of the embodiments of the present disclosure, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure.

[0038] In the description of the embodiments of the present disclosure, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and they can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present disclosure based on specific circumstances.

[0039] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of ​​layers are exaggerated for better understanding and ease of description. When a component (such as a layer, film, region, or substrate) is described as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. Conversely, when a component is described as being on the surface of another component, or as being formed or disposed on the surface of one component, it indicates that there is no third component between the two components. Furthermore, when a component is described as being "substantially" formed on another component, this means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0040] In the description of the embodiments of the present disclosure, when a component is referred to as "including" another component, unless otherwise specified, this does not exclude other components, and other components may further be included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them) or another component may be present between them. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, this means that no other components are located between them.

[0041] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0042] As known from the background art, for a metal oxide semiconductor field effect transistor formed based on a top gate structure in a memory, when the size of semiconductor components is further reduced, the isolation performance of the top gate structure needs to be improved.

[0043] An embodiment of the present disclosure provides a semiconductor structure, a semiconductor substrate, and a top gate structure located on the semiconductor substrate; an isolation structure, which is arranged around the side wall of the top gate structure; the isolation structure includes: a first protective layer, a first isolation layer, a second protective layer, and a second isolation layer, wherein the first protective layer is arranged around the side wall of the top gate structure; the first isolation layer is arranged around the side wall of the first protective layer away from the top gate structure; the second protective layer is arranged around the side wall of the first isolation layer away from the first protective layer, and covers the top of the top gate structure; the second isolation layer is arranged around the side wall of the second protective layer away from the first isolation layer, and the height of the second isolation layer is lower than the height of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate; and a third protective layer covers the top of the second protective layer and the top of the second isolation layer.

[0044] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0045] refer to Figure 2 and Figure 11 , Figure 2 A schematic cross-sectional view of a top gate structure provided in some embodiments. Figure 11 Schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments. In some embodiments, the semiconductor structure includes a semiconductor substrate 101 and a top gate structure 102 located on the semiconductor substrate 101 .

[0046] Regarding the semiconductor substrate 101 , in some embodiments, the semiconductor substrate 101 includes a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0047] The semiconductor structure further includes an isolation structure, which is disposed around the sidewalls of the top gate structure 102. The isolation structure includes a first protection layer 301, a first isolation layer 302, a second protection layer 303 and a second isolation layer 304.

[0048] The first protection layer 301 is disposed around the sidewalls of the top gate structure 102 .

[0049] The first isolation layer 302 is disposed around a sidewall of the first protection layer 301 away from the top gate structure 102 .

[0050] As for the first protective layer 301 , the material of the first protective layer 301 is a semiconductor material with insulating properties, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. In some embodiments, the material of the first protective layer 301 is silicon oxide.

[0051] The first isolation layer 302 is also made of a semiconductor material with insulating properties, such as silicon oxide, silicon nitride, or silicon oxynitride. However, the material of the first isolation layer 302 must be different from that of the first protective layer 301 to form insulating layers of different materials. In some embodiments, the material of the first isolation layer 302 is NIT (primarily composed of silicon nitride (SiN) and aluminum nitride (AlN)).

[0052] During semiconductor manufacturing, the thermal stability of NIT materials ensures that devices can withstand high-temperature operating environments. NIT materials can improve semiconductor interface properties and reduce the impact of interface defects on performance. In advanced semiconductor processes, NIT materials help reduce leakage current and enhance circuit reliability. NIT materials used in semiconductor manufacturing exhibit excellent chemical stability and resist various chemical attacks. NIT materials can optimize the crystal structure of semiconductors and improve the material's crystal quality. They can enhance the optical properties of semiconductors, creating favorable conditions for the manufacture of optoelectronic devices. During semiconductor manufacturing, NIT materials help increase device integration. NIT materials can reduce semiconductor resistance and minimize energy loss.

[0053] It should be noted that in Figure 11 In the corresponding example, at the contact interface between the semiconductor substrate 101 and the top-gate structure 102, the first protective layer 301 is in an "L" shape at the contact interface, and the first isolation layer 302 is located on the first protective layer 301. This is formed based on a corresponding formation process (after sequentially depositing the film layers corresponding to the first protective layer 301 and the first isolation layer 302, etching to form the first protective layer 301 and the first isolation layer 302), and does not constitute a limitation of this embodiment. In other embodiments, at the contact interface between the semiconductor substrate 101 and the top-gate structure 102, the first isolation layer 302 is parallel to the first protective layer 301, and both are in an "I" shape at the contact interface. In this case, the corresponding formation process is: depositing a film layer corresponding to the first protective layer 301, then etching to form the first protective layer 301, and then depositing a film layer corresponding to the first isolation layer 302, then etching to form the first isolation layer 302.

[0054] The second protection layer 303 is disposed around a sidewall of the first isolation layer 302 away from the first protection layer 301 and covers the top of the top gate structure 102 .

[0055] For the second protective layer 303, the material of the first protective layer 301 is a semiconductor material with insulating properties, such as silicon oxide, silicon nitride, or silicon oxynitride. However, the material of the second protective layer 303 must be different from that of the first isolation layer 302 to form insulating layers of different materials. In some embodiments, the material of the first protective layer 301 is silicon oxide.

[0056] It should be noted that in Figure 11 In the corresponding example, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is "L"-shaped at the contact interface, that is, the next process is directly performed after the second protective layer 303 is deposited and formed, and the second protective layer 303 is still located on the semiconductor substrate 101. In other embodiments, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is "I"-shaped at the contact interface, that is, after the second protective layer 303 is deposited and formed, the second protective layer 303 is etched in an area located on the top surface of the semiconductor substrate 101.

[0057] The second isolation layer 304 surrounds a sidewall of the second protection layer 303 away from the first isolation layer 302 . In a direction perpendicular to the top surface of the semiconductor substrate 101 , the height of the second isolation layer 304 is lower than that of the top gate structure 102 .

[0058] The second isolation layer 304 is also made of a semiconductor material with insulating properties, such as silicon oxide, silicon nitride, or silicon oxynitride. However, the material of the second isolation layer 304 must be different from that of the second protective layer 303 to form insulating layers of different materials. In some embodiments, the material of the second isolation layer 304 is NIT.

[0059] It should be noted that in Figure 11 In the corresponding example, since the second protective layer 303 is "L"-shaped at the contact interface, the second isolation layer 304 is located on the second protective layer 303 at the contact interface; in other embodiments, if the second protective layer 303 is "I"-shaped at the contact interface, the second isolation layer 304 is located on the semiconductor substrate 101 at the contact interface.

[0060] The semiconductor structure further includes a third protection layer 306 , which covers a top portion of the second protection layer 303 and a top portion of the second isolation layer 304 .

[0061] For the above-mentioned semiconductor structure, the sidewalls of the top gate structure 102 have a four-layer isolation structure consisting of a first protective layer 301, a first isolation layer 302, a second protective layer 303, and a second isolation layer 304, which has better insulation performance and can effectively prevent ion diffusion in the top gate structure 102. In addition, the second protective layer 303 and the third protective layer 306 are also located on top of the top gate structure 102 to form a "cap-shaped" structure to prevent the top gate structure from being polished back in subsequent processes after the semiconductor structure is formed, and to prevent etching solution from subsequent processes from remaining in the isolation structure and in the gap between the top gate structure 102 and the isolation structure, thereby causing damage to the semiconductor structure.

[0062] In some embodiments, the material of the first isolation layer 302 and the material of the second isolation layer 304 are the same.

[0063] In some embodiments, the material of the first protection layer 301 , the material of the second protection layer 303 , and the material of the third protection layer 306 are the same.

[0064] In some embodiments, in a direction perpendicular to the sidewalls of the top gate structure 102, the thickness of the first protection layer 301 is 1 nm to 100 nm, the thickness of the first isolation layer 302 is 1 nm to 100 nm, and the thickness of the second protection layer 303 is 1 nm to 100 nm. For example, the thickness of the first protection layer 301, the thickness of the first isolation layer 302, and the thickness of the first protection layer 301 can be 3 nm, 5 nm, 7 nm, and 9 nm, respectively.

[0065] In some embodiments, the thickness of the first protective layer 301, the thickness of the first isolation layer 302, and the thickness of the first protective layer 301 may be the same, partially the same, or completely different. For example, the thickness of the three may be the same, or two of them may be the same, while the thickness of the other one may be different from the other two, or the thickness of the three may be different.

[0066] It should be noted that those skilled in the art can expand the isolation structure to more layers based on the 4-layer isolation structure of this embodiment, but must ensure that the third protection layer can cover the isolation structure.

[0067] In addition, as the number of layers of the isolation structure increases, in the direction perpendicular to the side wall of the top gate structure 102, in order to ensure the overall thickness of the isolation structure, the more layers of the isolation structure there are, the thickness of each protective layer / isolation layer in the isolation structure needs to be thinner accordingly to adapt to the overall size of the semiconductor structure.

[0068] In some embodiments, the thickness of the second isolation layer 304 in a direction perpendicular to the sidewall of the top gate structure 102 is used to adjust the size of the semiconductor structure.

[0069] For example, if the semiconductor structures to be formed in the memory include three sizes of a, b, and c, for the semiconductor structure provided in the embodiment of the present disclosure, regardless of whether the semiconductor structures are of sizes a, b, or c, the corresponding top gate structure 102, as well as the first protective layer 301, the first isolation layer 302, and the second protective layer 303 can be formed based on the same process. Then, based on the sizes of the three sizes a, b, and c, the size of the second isolation layer 304 is adaptively adjusted to form semiconductor structures of sizes a, b, and c, and the similarity of the isolation effect of the top gate structure 102 in semiconductor structures of different sizes is ensured.

[0070] In some embodiments, the thickness of the second isolation layer 304 is 0.1 nm to 100 nm. Based on the foregoing, it can be seen that in practice, the thickness of the second isolation layer 304 is adjusted accordingly based on the required size of the semiconductor structure to adaptably form a semiconductor structure of the required size, thereby improving the adaptability of the semiconductor structure provided by the embodiments of the present disclosure.

[0071] Regarding the top gate structure 102 , in some embodiments, the top gate structure 102 includes a channel layer 201 , a gate isolation layer 202 , a gate conductive layer 203 , and a gate capping layer 204 .

[0072] Among them, the channel layer 201 is located at the top of the semiconductor substrate 101, the gate isolation layer 202 is located at the top of the side of the channel layer 201 away from the semiconductor substrate 101, the gate conductive layer 203 is located at the top of the side of the gate isolation layer 202 away from the channel layer 201, and the gate cap layer 204 is located at the top of the side of the gate conductive layer 203 away from the gate isolation layer 202.

[0073] The channel layer 201 is used to form a conductive channel between a source region and a drain region in a transistor corresponding to the top gate structure 102. In some embodiments, the material of the channel layer 201 includes silicon, germanium, silicon germanium, etc.

[0074] The gate isolation layer 202 serves as the gate oxide structure of the top gate structure 102. In some embodiments, the material of the gate isolation layer 202 includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, anti-ferroelectric material, or a combination thereof. For example, the gate dielectric layer may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON.

[0075] The gate conductive layer 203 is used to receive a corresponding gate control signal to form a conductive channel in the channel layer 201 based on the gate control signal, thereby connecting the source region and the drain region in the transistor corresponding to the top gate structure 102 .

[0076] To optimize the conductive performance of the gate conductive layer 203 , in some embodiments, the gate conductive layer 203 includes a high dielectric constant (high-K) layer 210 , a work function layer 220 , a non-metallic conductive layer 230 , an adhesion layer 240 and a metal conductive layer 250 .

[0077] The high-k dielectric layer 210 is used to increase the dielectric constant of the gate conductive layer 203. In some embodiments, the high-k dielectric layer 210 comprises a HfSiON (Hafnium Silicon Oxynitride) high-k gate dielectric layer. The performance of HfSiON can be controlled by adjusting the ratio of elements such as Hf, Si, O, and N. Different compositions may affect the dielectric constant, band gap, and other properties of the high-k dielectric layer 210.

[0078] The work function layer 220 is used to increase the work function of the gate conductive layer 203. In some embodiments, the material of the work function layer 220 includes titanium nitride (TiN). The work function layer 220 formed based on titanium nitride is used to increase the work function of the gate conductive layer 203. In addition, based on the adhesiveness and conductive properties of titanium nitride, the work function layer 220 can form an interface with low contact resistance and strong adhesion.

[0079] In some embodiments, the material of the non-metallic conductive layer 230 includes silicon, germanium, silicon germanium, etc.

[0080] Adhesion layer 240 is disposed between non-metallic conductive layer 230 and metal conductive layer 250 to ensure adhesion and conductive contact between non-metallic conductive layer 230 and metal conductive layer 250. In some embodiments, the material of adhesion layer 240 includes titanium nitride (TiN).

[0081] In some embodiments, the material of the metal conductive layer 250 includes a single metal material such as tungsten, copper, aluminum, silver, or an alloy material formed by a combination thereof.

[0082] The gate capping layer 204 is used for top insulation of the top gate structure 102 and structural protection of the top gate structure 102. In some embodiments, the material of the gate capping layer 204 is the same as that of the first isolation layer 302 and the second isolation layer 304.

[0083] As can be seen from the foregoing, in a direction perpendicular to the top surface of the semiconductor substrate 101, the height of the second isolation layer 304 is lower than the height of the top gate structure 102. In this embodiment, the height of the second isolation layer 304 is lower than the height of the top surface of the gate cap layer 304 and higher than the height of the bottom surface of the gate cap layer 204. By maintaining the height of the second isolation layer 304 higher than the height of the bottom surface of the gate cap layer 204, the isolation performance of the second isolation layer 304 with respect to the top gate structure 102 is ensured.

[0084] For the semiconductor structure provided in the embodiment of the present disclosure, the sidewalls of the top gate structure 102 have a four-layer isolation structure consisting of a first protective layer 301, a first isolation layer 302, a second protective layer 303, and a second isolation layer 304, which has better insulation performance and can effectively prevent ion diffusion in the top gate structure 102. In addition, the second protective layer 303 and the third protective layer 306 are also located on top of the top gate structure 102 to form a "cap-shaped" structure to prevent the top gate structure from being re-grinded in subsequent processes after the semiconductor structure is formed, and to prevent the etching solution in subsequent processes from remaining in the isolation structure and in the gap between the top gate structure 102 and the isolation structure, thereby causing damage to the semiconductor structure.

[0085] It should be noted that, in the absence of conflict, the features disclosed in the semiconductor structures provided in the above embodiments can be randomly combined to obtain new semiconductor structure embodiments.

[0086] Another embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate and forming a top gate structure on the semiconductor substrate; forming a first protective layer and a first isolation layer, wherein the first protective layer is arranged around the side wall of the top gate structure, and the first isolation layer is arranged around the side wall of the first protective layer away from the top gate structure; depositing to form a second protective layer, wherein the second protective layer is located on the side wall of the first isolation layer away from the first protective layer and covers the top of the top gate structure; forming a second isolation layer, wherein the second isolation layer is located on the side wall of the second protective layer away from the first isolation layer, and in a direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure; forming a third protective layer, wherein the third protective layer covers the top of the second protective layer and the top of the second isolation layer.

[0087] The following will describe in detail the various embodiments of the present disclosure in conjunction with the accompanying drawings. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding descriptions of the above embodiments, and will not be described in detail below.

[0088] In some embodiments, a method for forming a semiconductor structure includes the following steps:

[0089] In step S1 , a semiconductor substrate is provided, and a top gate structure is formed on the semiconductor substrate.

[0090] refer to Figure 1 and Figure 2 , Figure 1 Schematic diagram of the cross-sectional structure of the semiconductor substrate and the top gate structure provided in some embodiments, Figure 2 Schematic diagram of the cross-sectional structure of a top gate structure provided in some embodiments.

[0091] For the top gate structure 102, in some embodiments, the method of forming the top gate structure 102 includes: depositing a channel layer 201 on the top surface of the semiconductor substrate 101, depositing a gate isolation layer 202 on the top surface of the channel layer 201, depositing a gate conductive layer 203 on the top surface of the gate isolation layer 202, and depositing a gate cap layer 204 on the top surface of the gate conductive layer 203.

[0092] In some embodiments, the method of forming the gate conductive layer 203 includes: sequentially depositing a high dielectric constant (high-K) layer 210 , a work function layer 220 , a non-metallic conductive layer 230 , an adhesion layer 240 and a metal conductive layer 250 on the top surface of the gate isolation layer 202 .

[0093] It should be noted that the “deposition” mentioned in the embodiments of the present disclosure refers to a deposition process that facilitates the formation of a corresponding material layer on a substrate, wherein the deposition process can be physical vapor deposition (PVD), spin coating, chemical vapor deposition (CVD), and epitaxy (EPI).

[0094] Step S2 , forming a first protection layer and a first isolation layer, wherein the first protection layer is disposed around the sidewall of the top gate structure, and the first isolation layer is disposed around the sidewall of the first protection layer away from the top gate structure.

[0095] refer to Figure 3 and Figure 4 , Figure 3 Schematic diagram of the cross-sectional structure of the first protective film and the first isolation film provided in some embodiments, Figure 4 Schematic diagram of the cross-sectional structure of the first protective layer and the first isolation layer provided in some embodiments. In some embodiments, the method of forming the first protective layer 301 and the first isolation layer 302 includes: depositing a first protective film 310 on the surface of the semiconductor substrate 101 and the top gate structure 102; depositing a first isolation film 320 on the surface of the first protective film 310; etching away the first protective film 310 and the first isolation film 320 located on the top of the top gate structure 102 and the top of the semiconductor substrate 101, leaving the first protective film 310 located on the sidewalls of the top gate structure 102 to form the first protective layer 301, and the remaining first isolation film 320 located on the sidewalls of the first protective layer 301 to form the first isolation layer 302.

[0096] It should be noted that due to Figure 3 and Figure 4In the example, the first isolation film 320 is formed directly after the first protective film 310 is formed. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, the subsequently formed first isolation layer 302 is located on the first protective layer 301, and the first protective layer 301 is "L"-shaped at the contact interface. In some embodiments, after the first protective film 310 is formed, the first protective layer 301 is first etched to form the first protective layer 301, and then the first isolation film 320 is formed. In this case, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the subsequently formed first isolation layer 302 is parallel to the first protective layer 301, and both are "I"-shaped at the contact interface.

[0097] Step S3, forming a second protective layer, the second protective layer is located on the sidewall of the first isolation layer away from the first protective layer and covers the top of the top gate structure. Figure 5 , Figure 5 Schematic diagram of the cross-sectional structure of the second protective layer provided in some embodiments.

[0098] It should be noted that Figure 5 In this example, the second protective layer 303 is also located on the top surface of the semiconductor substrate 101. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is in an "L" shape at the contact interface. In other embodiments, the second protective layer 303 located on the top surface of the semiconductor substrate 101 may be removed. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is in an "I" shape at the contact interface.

[0099] Step S4 , forming a second isolation layer, which is located on a sidewall of the second protection layer away from the first isolation layer, and has a height lower than that of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate.

[0100] refer to Figures 6 to 8 , Figure 6 Schematic diagram of the cross-sectional structure of the second isolation film provided in some embodiments, Figure 7 Schematic diagram of the cross-sectional structure of the carbon coating provided in some embodiments, Figure 8 A schematic diagram of a cross-sectional structure of a second isolation layer provided in some embodiments. In some embodiments, a method for forming the second isolation layer 304 includes: depositing a second isolation film 340 on the surface of the second protective layer 303, spin-coating a carbon coating (SOC) on the surface of the second isolation film 340, etching to expose the top surface of the second isolation film 340, and etching the second isolation film 340 until the height of the second isolation film 340 is lower than the height of the top gate structure 102 in a direction perpendicular to the top surface of the semiconductor substrate 101, and the remaining second isolation film 340 constitutes the second isolation layer 304.

[0101] It should be noted that due to Figures 6 to 8 In the embodiment, a spin coating process is directly performed to form a carbon coating 305 after forming the second isolation film 340. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, a second isolation layer 304 formed subsequently is in an "L" shape at the contact interface.

[0102] In some embodiments, after forming the second isolation film 340, the second isolation film 340 located on the top of the semiconductor substrate 101 is first etched and then a spin coating process is directly performed to form a carbon coating 305. At this time, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the subsequently formed second isolation layer 304 is in an "I" shape at the contact interface.

[0103] In addition, reference Figure 1 、 Figure 2 and Figure 8 If the top gate structure 102 includes the channel layer 201, the gate isolation layer 202, the high dielectric constant (high-K) layer 210, the work function layer 220, the non-metallic conductive layer 230, the adhesion layer 240, the metal conductive layer 250, and the gate cap layer 204 stacked in sequence as described above, the height of the second isolation layer 304 is lower than the height of the top surface of the gate cap layer 204 and higher than the height of the bottom surface of the gate cap layer 204.

[0104] Step S5 , forming a third protective layer, wherein the third protective layer covers the top of the second protective layer and the top of the second isolation layer.

[0105] refer to Figures 9 to 11 , Figure 9 Schematic diagram of the cross-sectional structure of the third protective film provided in some embodiments, Figure 10 Schematic diagram of the cross-sectional structure of the third protective film after removing the carbon coating provided in some embodiments, Figure 11 Schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments. In some embodiments, a method for forming a third protective layer 306 includes: forming a third protective film 360, the third protective film 360 being located on top of the second isolation layer 304 and the second protective layer 303; patterning the third protective film 360 to expose the carbon coating 305 located on the sidewalls of the second isolation layer 304; removing the carbon coating 305; and etching the top of the semiconductor substrate 101 and the top gate structure 102 using an etching process to expose the semiconductor substrate 101. The remaining third protective film 360 constitutes the third protective layer 306.

[0106] In some embodiments, the etching process has an etching selectivity ratio of 3:1 to 10:1 for the second isolation layer and the third protective layer. In specific applications, the etching process can have an etching selectivity ratio of 4:1, 5:1, 6:1, 7:1, 8:1, or 9:1. By controlling the etching selectivity of the etching process, the etching rate for the second isolation layer is faster and the etching rate for the third protective layer is slower. In this way, after etching the top of the semiconductor substrate 101 to expose the top surface of the semiconductor substrate 101, the third protective film 360 still remains on the top of the top gate structure 102. That is, the third protective layer 306 formed by the remaining third protective film 360 covers the top of the second protective layer 303 and the top of the second isolation layer 304.

[0107] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above and will not be repeated here.

[0108] While the basic concepts have been described above, it will be apparent to those skilled in the art that the detailed disclosure is merely illustrative and does not limit the present disclosure. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and revisions to the present disclosure. Such modifications, improvements, and revisions are suggested in the present disclosure and remain within the spirit and scope of the exemplary embodiments of the present disclosure.

[0109] The above is a detailed introduction to a semiconductor structure and a method for forming the same provided in an embodiment of the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and core ideas of the present disclosure. At the same time, for those skilled in the art, based on the ideas of the present disclosure, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A semiconductor substrate, and a top gate structure located on the semiconductor substrate; An isolation structure, arranged around a sidewall of the top gate structure; The isolation structure includes: a first protective layer, a first isolation layer, a second protective layer, and a second isolation layer, wherein the first protective layer is disposed around the sidewall of the top gate structure; the first isolation layer is disposed around the sidewall of the first protective layer away from the top gate structure; the second protective layer is disposed around the sidewall of the first isolation layer away from the first protective layer and covers the top of the top gate structure; the second isolation layer is disposed around the sidewall of the second protective layer away from the first isolation layer, and in a direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure; The third protection layer only covers the top of the second protection layer and the top of the second isolation layer, fills the height difference between the second isolation layer and the top gate structure, and exposes the sidewall of the second isolation layer away from the second protection layer.

2. The semiconductor structure according to claim 1, wherein: In a direction perpendicular to the sidewall of the top gate structure, the thickness of the first protection layer is 1 nm to 100 nm, the thickness of the first isolation layer is 1 nm to 100 nm, and the thickness of the second protection layer is 1 nm to 100 nm.

3. The semiconductor structure according to claim 1, wherein: In a direction perpendicular to the sidewall of the top gate structure, the thickness of the second isolation layer is used to adjust the size of the semiconductor structure.

4. The semiconductor structure according to claim 3, wherein: The thickness of the second isolation layer is 0.1 nm to 100 nm.

5. The semiconductor structure according to claim 1, wherein: The material of the first isolation layer is the same as that of the second isolation layer. The semiconductor structure according to claim 1 , wherein: The material of the first protective layer, the material of the second protective layer, and the material of the third protective layer are the same.

7. The semiconductor structure according to claim 1, wherein: The top gate structure includes: a channel layer, located on top of the semiconductor substrate; a gate isolation layer, located on a top portion of a side of the channel layer away from the semiconductor substrate; a gate conductive layer, located on a top portion of a side of the gate isolation layer away from the channel layer; The gate cap layer is located on the top of a side of the gate conductive layer away from the gate conductive layer.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate and forming a top gate structure on the semiconductor substrate; forming a first protective layer and a first isolation layer, wherein the first protective layer is disposed around a sidewall of the top gate structure, and the first isolation layer is disposed around a sidewall of the first protective layer away from the top gate structure; Depositing to form a second protection layer, the second protection layer is located on a sidewall of the first isolation layer away from the first protection layer and covers a top of the top gate structure; forming a second isolation layer, wherein the second isolation layer is located on a sidewall of the second protection layer away from the first isolation layer, and in a direction perpendicular to the top surface of the semiconductor substrate, a height of the second isolation layer is lower than a height of the top gate structure; forming a third protective layer, wherein the third protective layer covers a top portion of the second protective layer and a top portion of the second isolation layer; The method of forming the second isolation layer includes: Depositing a second isolation film on the surface of the second protective layer, and forming a carbon coating on the surface of the second isolation film by spin coating; The carbon coating is etched to expose the top surface of the second isolation film, and the second isolation film is etched until the height of the second isolation film is lower than the height of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate, and the remaining second isolation film constitutes the second isolation layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method of forming the first protective layer and the first isolation layer includes: Depositing a first protective film on the surface of the semiconductor substrate and the top gate structure; depositing a first isolation film on the surface of the first protective film; The first protective film and the first isolation film located on the top of the top gate structure and the top of the semiconductor substrate are etched away, and the remaining first protective film located on the side wall of the top gate structure forms the first protective layer, and the remaining first isolation film located on the side wall of the first protective layer forms the first isolation layer.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the third protective layer includes: forming a third protective film, wherein the third protective film is located on top of the second isolation layer and the second protective layer; patterning the third protection film to expose the carbon coating on the sidewall of the second isolation layer; removing the carbon coating; The top of the semiconductor substrate and the top gate structure are etched based on an etching process to expose the semiconductor substrate, and the remaining third protection film constitutes the third protection layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The etching process has an etching selectivity ratio of 3:1 to 10:1 for the second isolation layer and the third protection layer.

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