Method for manufacturing display device

Abstract

The invention relates to a manufacturing method of a display device. According to one embodiment, in a method of manufacturing a display device, a process substrate is prepared in which a lower electrode, an inorganic insulating layer, and a partition wall including a lower portion located on the inorganic insulating layer, and an upper portion located on the lower portion and protruding from a side surface of the lower portion are formed, and the process substrate is formed on the lower electrode in an opening. The method includes forming a laminated film including an upper electrode by vapor deposition using a partition wall as a mask, forming a sealing layer on the laminated film using an inorganic insulating material, forming a patterned resist on the sealing layer, removing the sealing layer exposed from the resist, and removing the laminated film exposed from the resist. The step of removing the laminated film includes a step of removing the upper electrode in contact with the lower portion with an etching solution, the etching solution being a mixture of nitric acid, phosphoric acid and acetic acid, the concentration of nitric acid being 26% or more, the concentration of phosphoric acid being 0.5-10%, and the concentration of acetic acid being 0.5-15%.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023 - 221237 filed on December 27, 2023, and incorporates by reference all the disclosures described in the Japanese application. Technical field

[0003] Embodiments of the present invention relate to a method for manufacturing a display device. Background art

[0004] In recent years, display devices using organic light - emitting diodes (OLEDs) as display elements have been put into practical use. The display element includes a pixel circuit including thin - film transistors, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole - transporting layer and an electron - transporting layer in addition to a light - emitting layer.

[0005] In the process of manufacturing such a display element, techniques for suppressing a reduction in reliability are required. Summary of the invention

[0006] An object of the embodiments is to provide a method for manufacturing a display device capable of suppressing a reduction in reliability.

[0007] According to one embodiment, in a method for manufacturing a display device,

[0008] Prepare a processing substrate in which a lower electrode is formed above the substrate, an inorganic insulating layer having an opening overlapping with the lower electrode, and a partition wall including a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from the side surface of the lower portion. Above the lower electrode in the opening, a laminated film including an upper electrode is formed by evaporation using the partition wall as a mask. Above the laminated film, a sealing layer is formed of an inorganic insulating material. Above the sealing layer, a patterned resist is formed. The sealing layer exposed from the resist is removed, the laminated film exposed from the resist is removed, and the step of removing the laminated film includes a step of removing the upper electrode in contact with the lower portion with an etching solution. The etching solution is a mixture of nitric acid, phosphoric acid, and acetic acid. The concentration of nitric acid is 26% or more, the concentration of phosphoric acid is 0.5% or more and 10% or less, and the concentration of acetic acid is 0.5% or more and 15% or less.

[0009] According to one embodiment, in a method for manufacturing a display device,

[0010] Prepare a processing substrate, in which a first lower electrode and a second lower electrode are formed above the substrate, an inorganic insulating layer having a first opening overlapping with the first lower electrode and a second opening overlapping with the second lower electrode, and a partition wall including a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from a side surface of the lower portion are provided. Above the first lower electrode in the first opening and above the second lower electrode in the second opening, a stacked film including an upper electrode is formed by evaporation using the partition wall as a mask. Above the stacked film, a sealing layer is formed of an inorganic insulating material. A patterned resist is formed above the sealing layer directly above the first lower electrode. The exposed sealing layer is removed from the resist, so that the stacked film overlapping above the second lower electrode is exposed. The exposed stacked film is removed from the resist, the second lower electrode is exposed from the second opening, and a side surface of the lower portion facing the second opening is exposed. The step of removing the stacked film includes a step of removing the upper electrode in contact with the lower portion using an etching solution. The etching solution is a mixture of nitric acid, phosphoric acid, and acetic acid. The concentration of the nitric acid is 26% or more, the concentration of the phosphoric acid is 0.5% or more and 10% or less, and the concentration of the acetic acid is 0.5% or more and 15% or less.

[0011] According to the embodiment, a manufacturing method of a display device capable of suppressing a reduction in reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG. is a diagram showing a configuration example of a display device DSP.

[0013] Figure 2 FIG. is an example diagram showing the layout of sub-pixels SP1, SP2, and SP3.

[0014] Figure 3 is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line A-B in

[0015] Figure 4 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0016] Figure 5 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0017] Figure 6 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0018] Figure 7 FIG. is a diagram for explaining a manufacturing method of the display device DSP.

[0019] Figure 8 This is a diagram for explaining a manufacturing method of a display device DSP.

[0020] Figure 9 This is a diagram that simply shows a configuration example of an etching device 200 for removing an upper electrode UE1.

[0021] Figure 10 This is a diagram for explaining a manufacturing method of a display device DSP.

[0022] Figure 11 This is a diagram for explaining a manufacturing method of a display device DSP.

[0023] Figure 12 This is a diagram for explaining a manufacturing method of a display device DSP.

[0024] Figure 13 This is a diagram for explaining a manufacturing method of a display device DSP.

[0025] Figure 14 This is a cross-sectional view showing another configuration example of a mother substrate 100.

[0026] Figure 15 This is the experimental result showing the relationship between the composition ratio of an etching solution and the peeling of an organic layer. Detailed implementation mode

[0027] An implementation mode will be described with reference to the accompanying drawings.

[0028] The disclosed content is merely an example, and appropriate changes that can be easily conceived by those skilled in the art while maintaining the gist of the invention are of course included in the scope of the present invention. In addition, regarding the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part may be schematically shown, but this is merely an example and does not limit the interpretation of the present invention. In addition, in this specification and each drawing, for components that perform the same or similar functions as those described with respect to the components in the already presented drawings, there are cases where the same reference numerals are marked and repeated detailed descriptions are appropriately omitted.

[0029] It should be noted that, for the convenience of understanding, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described in the drawings as needed. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Observing various elements parallel to the third direction Z is called a top view.

[0030] The display device of this implementation mode is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, a vehicle-mounted device, a tablet terminal, a smart phone, a mobile phone terminal, etc.

[0031] Figure 1 This is a diagram showing a configuration example of a display device DSP.

[0032] The display device DSP includes a display panel PNL on an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA outside the display area DA. The substrate 10 can be glass or a flexible resin film.

[0033] In the present embodiment, the shape of the substrate 10 when viewed from above is rectangular. However, the shape of the substrate 10 when viewed from above is not limited to a rectangle and can be other shapes such as a square, a circle, or an ellipse.

[0034] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different from each other. It should be noted that the pixel PX may also include sub-pixels SP of other colors such as white together with or instead of any one of the sub-pixels SP1, SP2, and SP3.

[0035] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of thin film transistors, for example.

[0036] The gate electrode of the pixel switch 2 is connected to the scan line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0037] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0038] The display element DE is an organic light emitting diode (OLED) as a light emitting element and is sometimes referred to as an organic EL element.

[0039] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends in the second direction Y, but is not limited thereto. Such a plurality of terminals TE are electrically connected to a flexible printed circuit board and an IC chip, for example.

[0040] Figure 2 This is a diagram showing an example of the layout of sub-pixels SP1, SP2, and SP3.

[0041] In the illustrated example, sub-pixels SP2 and sub-pixel SP3 are arranged in the second direction Y. Sub-pixels SP1 and sub-pixel SP2 are arranged in the first direction X, and sub-pixels SP1 and sub-pixel SP3 are arranged in the first direction X.

[0042] When the sub-pixels SP1, SP2, and SP3 are in such a layout, columns in which sub-pixels SP2 and sub-pixel SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed in the display area DA. These columns are alternately arranged in the first direction X.

[0043] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 the example. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may also be arranged in sequence in the first direction X.

[0044] An inorganic insulating layer 5 and a partition wall 6 are arranged in the display area DA. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes referred to as a rib.

[0045] The partition wall 6 overlaps the inorganic insulating layer 5 in a top view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition wall 6 may also have openings in the sub-pixels SP1, SP2, and SP3 in the same manner as the inorganic insulating layer 5. The partition wall 6 has conductivity and is electrically connected to the terminal TE of the common potential among the plurality of terminals TE Figure 1 shown.

[0046] The sub-pixels SP1, SP2, and SP3 each include display elements DE1, DE2, and DE3 as the display element DE.

[0047] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that respectively overlap the opening AP1. The peripheral portion of the lower electrode LE1 is covered by the inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition wall 6 in a top view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap the inorganic insulating layer 5 in a top view. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength region.

[0048] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that respectively overlap with the opening AP2. The peripheral portion of the lower electrode LE2 is covered by the inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by the partition wall 6 in a top view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 respectively overlap with the inorganic insulating layer 5 in a top view. The organic layer OR2 includes, for example, a light-emitting layer that emits light in the green wavelength region.

[0049] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that respectively overlap with the opening AP3. The peripheral portion of the lower electrode LE3 is covered by the inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by the partition wall 6 in a top view. The peripheral portions of the organic layer OR3 and the upper electrode UE3 respectively overlap with the inorganic insulating layer 5 in a top view. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength region.

[0050] In the illustrated example, the outer shapes of the lower electrodes LE1, LE2, and LE3 are represented by dashed lines, and the outer shapes of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are represented by single-dot dash lines. It should be noted that the outer shapes of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect the accurate shapes.

[0051] The lower electrodes LE1, LE2, and LE3 correspond to the anodes of the display elements, for example. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of the display elements and are in contact with the partition wall 6.

[0052] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1 ). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0053] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from each other. The area of the opening AP1 is larger than the area of the opening AP2, and the area of the opening AP2 is larger than the area of the opening AP3. In other words, the area of the lower electrode LE1 exposed from the opening AP1 is larger than the area of the lower electrode LE2 exposed from the opening AP2, and the area of the lower electrode LE2 exposed from the opening AP2 is larger than the area of the lower electrode LE3 exposed from the opening AP3.

[0054] Figure 3 is a schematic cross-sectional view of the display device DSP along the A-B line in Figure 2 .

[0055] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 various circuits such as the pixel circuit 1 shown in the figure and various wirings such as the scan line GL, the signal line SL, and the power line PL. The circuit layer 11 is covered with the insulating layer 12. The insulating layer 12 is an organic insulating layer that planarizes the unevenness generated by the circuit layer 11.

[0056] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12 and are separated from each other. The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through the contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are omitted in Figure 3 the figure.

[0057] The partition wall 6 includes a lower portion 61 disposed on the inorganic insulating layer 5 and having conductivity and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a larger width than the lower portion 61. The both end portions of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape.

[0058] In the illustrated example, the lower portion 61 has a first conductive layer 63 disposed on the inorganic insulating layer 5 and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed thinner than the second conductive layer 64. The both end portions of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64.

[0059] The upper portion 62 has a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. The both end portions of the first thin film 65 and the second thin film 66 protrude from the side surfaces of the second conductive layer 64.

[0060] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61.

[0061] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61.

[0062] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and its peripheral portion is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower portion 61.

[0063] In the illustrated example, the sub-pixel SP1 has a cover layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cover layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cover layer CP3 and a sealing layer SE3. The cover layers CP1, CP2, and CP3 each function as an optical adjustment layer for improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. It should be noted that the cover layers CP1, CP2, and CP3 can be omitted.

[0064] The cover layer CP1 is disposed above the upper electrode UE1.

[0065] The cover layer CP2 is disposed above the upper electrode UE2.

[0066] The cover layer CP3 is disposed above the upper electrode UE3.

[0067] The sealing layer SE1 is disposed above the cover layer CP1, is in contact with the partition wall 6, and continuously covers the respective components of the sub-pixel SP1.

[0068] The sealing layer SE2 is disposed above the cover layer CP2, is in contact with the partition wall 6, and continuously covers the respective components of the sub-pixel SP2.

[0069] The sealing layer SE3 is disposed above the cover layer CP3, is in contact with the partition wall 6, and continuously covers the respective components of the sub-pixel SP3.

[0070] In the following description, the multi-layer body including the organic layer OR1, the upper electrode UE1, and the cover layer CP1 is referred to as the stacked film FL1, the multi-layer body including the organic layer OR2, the upper electrode UE2, and the cover layer CP2 is referred to as the stacked film FL2, and the multi-layer body including the organic layer OR3, the upper electrode UE3, and the cover layer CP3 is referred to as the stacked film FL3.

[0071] In the illustrated example, a part of the stacked film FL1 is located above the partition wall 6 around the sub-pixel SP1 and is separated from the stacked film FL1 (the part constituting the display element DE1) located at the opening AP1.

[0072] Similarly, a part of the stacked film FL2 is located above the partition wall 6 around the sub-pixel SP2 and is separated from the stacked film FL2 (the part constituting the display element DE2) located at the opening AP2.

[0073] Similarly, a part of the stacked film FL3 is located on the partition wall 6 around the sub-pixel SP3 and is separated from the stacked film FL3 (the part constituting the display element DE3) located in the opening AP3.

[0074] It should be noted that the stacked films FL1, FL2, and FL3 on the partition wall 6 are sometimes omitted. In this case, voids are formed between the sealing layers SE1, SE2, SE3 and the partition wall 6.

[0075] The end portions of the sealing layers SE1, SE2, SE3 are respectively located on the partition wall 6. In the illustrated example, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the stacked film FL2 and the sealing layer SE2 on this partition wall 6. In addition, the stacked film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the stacked film FL3 and the sealing layer SE3 on this partition wall 6.

[0076] The partition wall 6 and the sealing layers SE1, SE2, SE3 are covered by the resin layer 13. When voids are formed between the sealing layers SE1, SE2, SE3 and the partition wall 6, the resin layer 13 fills these voids. The resin layer 13 is covered by the sealing layer 14. The sealing layer 14 is covered by the resin layer 15.

[0077] The inorganic insulating layer 5, the sealing layers SE1, SE2, SE3, and the sealing layer 14 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3), for example.

[0078] The lower part 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound, for example. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper part 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound, for example.

[0079] The upper part 62 of the partition wall 6 is formed of a conductive material, for example, but may also be formed of an insulating material. The upper part 62 is formed of a material different from the lower part 61. The first thin film 65 is formed of a titanium-based material such as titanium or a titanium compound, for example. The second thin film 66 is formed of an oxide conductive material such as indium tin oxide (ITO), for example.

[0080] The lower electrodes LE1, LE2, LE3 are, for example, a multilayer body including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, LE3 are a multilayer body including a reflective layer between a pair of transparent layers.

[0081] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of materials different from each other. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength region, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength region, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength region.

[0082] In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0083] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), for example.

[0084] The cover layers CP1, CP2, and CP3 are multi-layer bodies of a plurality of thin films. The plurality of thin films are all transparent and have different refractive indexes from each other.

[0085] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed throughout the display area DA and the peripheral area SA.

[0086] Next, a method for manufacturing the display device DSP will be described. It should be noted that in each of the drawings for explaining the manufacturing method, illustrations below the insulating layer 12 are omitted.

[0087] First, as Figure 4 shown, a processing substrate SUB having lower electrodes LE1, LE2, LE3, an inorganic insulating layer 5, and a partition wall 6 is prepared. The process of preparing the processing substrate SUB includes the following processes. That is, on the substrate 10, a circuit layer 11 and an insulating layer 12 are formed throughout the display area DA and the peripheral area SA. Then, lower electrodes LE1 of the sub-pixel SP1, lower electrodes LE2 of the sub-pixel SP2, and lower electrodes LE3 of the sub-pixel SP3 are formed on the insulating layer 12. Then, an inorganic insulating layer 5 covering the peripheral portions of the lower electrodes LE1, LE2, and LE3 is formed. The inorganic insulating layer 5 is formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. Then, a partition wall 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61 is formed. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from the side surface of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a titanium-based material, and the second conductive layer 64 is formed of an aluminum-based material.

[0088] It should be noted that the process of forming openings AP1, AP2, and AP3 in the inorganic insulating layer 5 may be performed before forming the partition wall 6 or after forming the partition wall 6.

[0089] Next, a display element DE1 is formed.

[0090] First, as Figure 5 shown, a stacked film FL1 including an organic layer OR1, an upper electrode UE1, and a cover layer CP1 is formed. The process of forming the stacked film FL1 includes: a process of forming the organic layer OR1 that contacts the lower electrode LE1 in the opening AP1; a process of forming the upper electrode UE1 that covers the organic layer OR1 and contacts the lower part 61 of the partition wall 6; and a process of forming the cover layer CP1 located above the upper electrode UE1. The process of forming the organic layer OR1 includes processes of separately forming a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc. The upper electrode UE1 is formed of a mixture of magnesium and silver.

[0091] The organic layer OR1, the upper electrode UE1, and the cover layer CP1 are respectively formed by evaporation using the partition wall 6 as a mask. The stacked film FL1 is partitioned into a plurality of parts by the cantilever-shaped partition wall 6. These organic layer OR1, upper electrode UE1, and cover layer CP1 are continuously formed while maintaining a vacuum environment. Such a stacked film FL1 is also formed on the lower electrode LE2 and the lower electrode LE3.

[0092] Then, a sealing layer SE1 is formed on the stacked film FL1 by depositing an inorganic insulating material. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers the partitioned parts of the stacked film FL1 and the partition wall 6.

[0093] Next, as Figure 6 shown, a resist RS patterned into a specified shape is formed on the sealing layer SE1. The resist RS overlaps with the sub-pixel SP1 and a part of the partition wall 6 around it.

[0094] Next, etching is performed using the resist RS as a mask, and the sealing layer SE1 and the stacked film FL1 exposed from the resist RS are sequentially removed. This etching process will be described in detail with reference to an enlarged cross-sectional view including the lower electrode LE1 and the lower electrode LE2.

[0095] First, as Figure 7 shown, the sealing layer SE1 exposed from the resist RS is removed. As a result, a part of the cover layer CP1 is exposed above the partition wall 6, and in addition, the cover layer CP1 on the lower electrode LE2 is exposed. Although not shown, the cover layer CP1 on the lower electrode LE3 is also exposed. In addition, the side surface of the lower part 61 (or the second conductive layer 64) of the partition wall 6 facing the lower electrode LE2 is also exposed.

[0096] Next, as Figure 8As shown, the capping layer CP1 exposed from the resist RS is removed. As a result, a part of the upper electrode UE1 is exposed above the partition wall 6, and also, the upper electrode UE1 above the lower electrode LE2 is exposed. Although not shown, the upper electrode UE1 above the lower electrode LE3 is also exposed.

[0097] Next, the upper electrode UE1 exposed from the resist RS is removed. The process of removing the upper electrode UE1 is performed by wet etching using a prescribed etching solution.

[0098] Figure 9 FIG. is a diagram schematically showing a configuration example of an etching apparatus 200 for removing the upper electrode UE1.

[0099] The etching apparatus 200 includes a nozzle 210 for ejecting an etching solution 211 and a light source 220 for illuminating the inside of the apparatus.

[0100] The etching solution 211 is a mixture of nitric acid, phosphoric acid, and acetic acid. The concentration of nitric acid is 26% or more. The concentration of phosphoric acid is 0.5% or more and 10% or less. The concentration of acetic acid is 0.5% or more and 15% or less. The concentrations in this specification are all volume% concentrations, and sometimes the unit is expressed as vol%.

[0101] The light source 220 has a bright line spectrum at a wavelength of 550 nm or more. As the light source 220, for example, a low-pressure sodium lamp is preferably used.

[0102] If the processing substrate SUB from which the capping layer CP1 has been removed is loaded into the etching apparatus 200, the etching solution 211 is ejected from the nozzle 210 toward the processing substrate SUB. The upper electrode UE1 and the side surface of the lower portion 61 (or the second conductive layer 64) of the lower electrode LE2 exposed from the resist RS are exposed to the etching solution 211.

[0103] As a result, as Figure 10 shown, the upper electrode UE1 exposed from the resist RS is removed, and a part of the organic layer OR1 is exposed above the partition wall 6, and also, the organic layer OR1 above the lower electrode LE2 is exposed. Although not shown, the organic layer OR1 above the lower electrode LE3 is also exposed.

[0104] Next, as Figure 11 shown, the organic layer OR1 exposed from the resist RS is removed. As a result, a part of the upper portion 62 of the partition wall 6 is exposed, and also, the lower electrode LE2 is exposed.

[0105] As Figure 12 shown, in the sub-pixel SP1, the stacked film FL1 covered with the resist RS remains, in the sub-pixel SP2, the lower electrode LE2 is exposed, and in the sub-pixel SP3, the lower electrode LE3 is exposed.

[0106] Then, the resist RS is removed. Thus, the display element DE1 is formed in the sub-pixel SP1.

[0107] Next, as Figure 13 shown, the display element DE2 is formed. The steps of forming the display element DE2 are the same as those of forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2, and a cover layer CP2 are sequentially formed on the lower electrode LE2 to form a stacked film FL2. Then, a sealing layer SE2 is formed on the stacked film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cover layer CP2, the upper electrode UE2, and the organic layer OR2 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. Thus, the display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0108] Next, as Figure 14 shown, the display element DE3 is formed. The steps of forming the display element DE3 are the same as those of forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3, and a cover layer CP3 are sequentially formed on the lower electrode LE3 to form a stacked film FL3. Then, a sealing layer SE3 is formed on the stacked film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cover layer CP3, the upper electrode UE3, and the organic layer OR3 are patterned by etching using the resist as a mask. After this patterning, the resist is removed. Thus, the display element DE3 is formed in the sub-pixel SP3.

[0109] Then, a resin layer 13, a sealing layer 14, and a resin layer 15 shown in Figure 3 are sequentially formed. Thus, the display device DSP is completed.

[0110] It should be noted that in the above manufacturing process, it is assumed that the display element DE1 is formed first, then the display element DE2 is formed, and finally the display element DE3 is formed. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0111] Figure 15 is the experimental result showing the relationship between the composition ratio of the etching solution and the peeling of the organic layer.

[0112] The concentration of nitric acid in the etching solution is set to 30%. The horizontal axis of the graph corresponds to the concentration of phosphoric acid, and the vertical axis of the graph corresponds to the concentration of acetic acid. The time for exposing the processing substrate SUB to the etching solution is 15 to 300 seconds. In the graph, "〇" indicates that no peeling of the organic layer occurs when the processing substrate SUB is exposed to the etching solution, and "×" indicates that peeling of the organic layer occurs when the processing substrate SUB is exposed to the etching solution.

[0113] In the figure, in region A surrounded by solid lines, peeling of the organic layer is hardly confirmed. At this time, the concentration of nitric acid is 30% or more, the concentration of phosphoric acid is 0.5% or more and 10% or less, and the concentration of acetic acid is 0.5% or more and 15% or less. In addition, in region B surrounded by single dotted lines in the figure, peeling of the organic layer is not confirmed at all. At this time, the concentration of nitric acid is 30% or more, the concentration of phosphoric acid is 0.5% or more and 8% or less, and the concentration of acetic acid is 0.5% or more and 8% or less.

[0114] Here, the defect caused by peeling of the organic layer when removing the upper electrode will be described.

[0115] It is presumed that the organic layer is formed by vapor deposition and is bonded to the lower electrode by an electric effect. Therefore, if the ion density of the etching solution increases, the electrostatic interaction between the lower electrode and the organic layer will be hindered, the bonding force between the two will decrease, and peeling of the organic layer is likely to occur.

[0116] On the other hand, the second conductive layer 64 contained in the lower part 61 of the partition wall 6 is formed of an aluminum-based material, and when exposed to the etching solution, undesirable etching of the second conductive layer 64 needs to be prevented. Therefore, from the viewpoint of promoting oxidation of the surface of the second conductive layer 64, the etching solution needs to contain nitric acid as a strong acid with a concentration of 26% or more (desirably 30% or more).

[0117] If such an etching solution reacts with the upper electrode formed of a mixture of magnesium and silver, it ionizes into nitrate ions (NO3-) and silver ions (Ag+). Silver has a smaller ionization tendency than aluminum. Therefore, silver ions accept electrons from aluminum, precipitate as silver, and aluminum flows out as ions.

[0118] When the organic layer peels off during the etching of the upper electrode, the lower electrode is exposed, and a battery effect is generated between the lower electrode and the upper electrode through the etching solution. This battery effect further promotes the electron exchange as described above. Therefore, since the second conductive layer 64 of the partition wall 6 is exposed to the etching solution, aluminum is excessively dissolved and the side surface of the second conductive layer 64 recedes. Depending on the situation, it is also possible that the etching solution penetrates into the inside of the second conductive layer 64 and forms voids in the second conductive layer 64. Such a phenomenon occurs on the side surface of the second conductive layer 64 facing the display elements DE2 and DE3. Therefore, poor connection between the upper electrode and the second conductive layer 64 in the display elements DE2 and DE3 is caused. In addition, in the case of generating voids, the moisture remaining in the voids causes deterioration of the organic layer in the display elements DE2 and DE3. In addition, the precipitated silver grows on the partition wall 6, resulting in deterioration of the sealing performance of the display elements DE2 and DE3.

[0119] Therefore, when etching the upper electrode, it is extremely important to suppress the peeling of the organic layer. For example, in the process of forming the display element DE1, when etching the upper electrode UE1, it is required that the organic layer OR1 covers the lower electrodes LE2 and LE3. Additionally, in the process of forming the display element DE2, when etching the upper electrode UE2, it is required that the organic layer OR2 covers the lower electrode LE3.

[0120] Therefore, in the present embodiment, in addition to the above-mentioned nitric acid, a mixture of phosphoric acid having a concentration of 0.5% or more and 10% or less and acetic acid having a concentration of 0.5% or more and 15% or less is used as the etching solution. The phosphate ions (PO4 3- ) contained in the etching solution are likely to combine with the silver ions contained in the etching solution. Therefore, the silver ions in the etching solution can be reduced, the electron exchange between the silver ions and aluminum can be suppressed, and the precipitation of silver can be inhibited. The acetic acid contained in the etching solution exerts the effect of a surfactant and can suppress the under-etching of the upper electrode.

[0121] Moreover, for phosphoric acid and acetic acid, a low concentration that can exert the above functions is preferred. When the concentrations of phosphoric acid and acetic acid in the etching solution are high, the ion density contained in the etching solution increases. As described above, the electrostatic interaction between the lower electrode and the organic layer is hindered, and the peeling of the organic layer is likely to occur. Therefore, the phosphoric acid is 10% or less, preferably 8% or less. Additionally, the acetic acid is 15% or less, preferably 8% or less.

[0122] By applying such an etching solution, the peeling of the organic layer can be suppressed during the etching of the upper electrode. As a result, the excessive recession of the side surface of the second conductive layer 64, the formation of voids in the second conductive layer 64, and the precipitation of unwanted silver as described above can be suppressed. Therefore, the connection failure between the upper electrode and the second conductive layer 64 in the display elements DE2 and DE3, the deterioration of the organic layer in the display elements DE2 and DE3, and the deterioration of the sealing performance in the display elements DE2 and DE3 can be suppressed, and the reduction in reliability can be suppressed.

[0123] In addition, the light source 220 of the etching apparatus 200 has a bright line spectrum at a wavelength of 550 nm or more. It is known that silver phosphate generated from phosphate ions and silver ions in the etching solution absorbs light with a wavelength shorter than 550 nm and decomposes. Therefore, by applying the above-mentioned light source 220, the decomposition of silver phosphate can be suppressed, and the precipitation of silver can be inhibited.

[0124] The inventors of the present application have conducted various studies on the etching time for exposing the processing substrate SUB to the etching solution within the range of 15 to 300 seconds. Thus, from the viewpoint of suppressing the precipitation of silver, it is desirable that the etching time be as short as possible, preferably 120 seconds or less. In addition, from the viewpoint of suppressing under-etching of the upper electrode, it is desirable that the etching time be as long as possible, preferably 60 seconds or more.

[0125] In the above-described embodiment, for example, in the inorganic insulating layer 5, the opening AP1 corresponds to the first opening, and the opening AP2 corresponds to the second opening. The lower electrode LE1 corresponds to the first lower electrode, and the lower electrode LE2 corresponds to the second lower electrode. The organic layer OR1 corresponds to the first organic layer, and the organic layer OR2 corresponds to the second organic layer. The upper electrode UE1 corresponds to the first upper electrode, and the upper electrode UE2 corresponds to the second upper electrode.

[0126] As described above, according to the present embodiment, a manufacturing method of a display device capable of suppressing a reduction in reliability can be provided.

[0127] Based on the manufacturing method of the display device described as an embodiment of the present invention above, all manufacturing methods of display devices that those skilled in the art can implement by appropriately designing changes belong to the scope of the present invention as long as they include the gist of the present invention.

[0128] Within the scope of the idea of the present invention, those skilled in the art can conceive of various modifications, and these modifications should also be understood to belong to the scope of the present invention. For example, a solution obtained by appropriately adding, deleting, or designing changes to the components of the above-described embodiment by those skilled in the art, or a solution obtained by adding, omitting, or changing conditions of the process as long as it has the gist of the present invention is also included in the scope of the present invention.

[0129] In addition, regarding other effects brought about by the solutions described in the above-described embodiment, effects that can be clearly understood from the description of this specification or effects that can be appropriately conceived by those skilled in the art should of course be understood as effects brought about by the present invention.

Claims

1. A method for manufacturing a display device, wherein: preparing a processing substrate in which a lower electrode located above a substrate, an inorganic insulating layer having an opening overlapping with the lower electrode, and a partition wall including a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from a side surface of the lower portion are formed, forming a stacked film including an upper electrode in the opening on the lower electrode by vapor deposition using the partition wall as a mask, On the laminated film, a sealing layer is formed using an inorganic insulating material, forming a patterned resist on the sealing layer, removing the sealing layer exposed from the resist, removing the laminated film exposed from the resist, The step of removing the stacked film includes removing the upper electrode in contact with the lower portion using an etching solution, The etching solution is a mixture of nitric acid, phosphoric acid and acetic acid. The concentration of the nitric acid is above 26%, The concentration of the phosphoric acid is 0.5% to 10%. The concentration of the acetic acid is greater than or equal to 0.5% and less than or equal to 15%.

2. The method for manufacturing a display device according to claim 1, wherein: The concentration of the phosphoric acid is 8% or less.

3. The method for manufacturing a display device according to claim 2, wherein: The concentration of the acetic acid is below 8%.

4. The method for manufacturing a display device according to claim 3, wherein: The concentration of the nitric acid is above 30%.

5. The method for manufacturing a display device according to claim 1, wherein: The time for removing the upper electrode using the etching solution is 60 seconds to 120 seconds.

6. The method for manufacturing a display device according to claim 1, wherein: The process of removing the upper electrode using the etching solution is performed under a light source having a bright line spectrum at a wavelength of 550 nm or more.

7. The method for manufacturing a display device according to claim 6, wherein: A sodium lamp was used as the light source.

8. The method for manufacturing a display device according to claim 1, wherein: The first conductive layer located on the inorganic insulating layer in the lower portion is formed of a titanium-based material, and the second conductive layer located between the first conductive layer and the upper portion is formed of an aluminum-based material.

9. The method for manufacturing a display device according to claim 8, wherein: The upper electrode is formed of a mixture of magnesium and silver.

10. The method for manufacturing a display device according to claim 9, wherein: The process of forming the laminated film includes: forming an organic layer including a light-emitting layer on the lower electrode; forming an upper electrode on the organic layer; and forming a capping layer on the upper electrode, When removing the sealing layer, a part of the lower portion and the cover layer are exposed, In the step of removing the upper electrode with the etching solution, a portion of the lower portion is exposed to the etching solution.

11. A method for manufacturing a display device, wherein: A processing substrate is prepared, wherein the processing substrate is formed with a first lower electrode and a second lower electrode located above the substrate, an inorganic insulating layer having a first opening overlapping with the first lower electrode and a second opening overlapping with the second lower electrode, and a partition wall between the first opening and the second opening including a lower portion located above the inorganic insulating layer and an upper portion located above the lower portion and protruding from a side surface of the lower portion, forming a stacked film including an upper electrode on the first lower electrode in the first opening and on the second lower electrode in the second opening by vapor deposition using the partition wall as a mask, On the laminated film, a sealing layer is formed using an inorganic insulating material, forming a patterned resist on the sealing layer directly on the first lower electrode, removing the sealing layer exposed from the resist to expose the stacked film overlapping the second lower electrode, removing the stacked film exposed from the resist, exposing the second lower electrode from the second opening, and exposing the side surface of the lower portion facing the second opening, The step of removing the stacked film includes removing the upper electrode in contact with the lower portion using an etching solution, The etching solution is a mixture of nitric acid, phosphoric acid and acetic acid. The concentration of the nitric acid is above 26%, The concentration of the phosphoric acid is 0.5% to 10%. The concentration of the acetic acid is greater than or equal to 0.5% and less than or equal to 15%.

12. The method for manufacturing a display device according to claim 11, wherein: The concentration of the phosphoric acid is 8% or less.

13. The method for manufacturing a display device according to claim 12, wherein: The concentration of the acetic acid is below 8%.

14. The method for manufacturing a display device according to claim 13, wherein: The concentration of the nitric acid is above 30%.

15. The method for manufacturing a display device according to claim 11, wherein: The time for removing the upper electrode using the etching solution is 60 seconds to 120 seconds.

16. The method for manufacturing a display device according to claim 11, wherein: The process of removing the upper electrode using the etching solution is performed under a light source having a bright line spectrum at a wavelength of 550 nm or more.

17. The method for manufacturing a display device according to claim 16, wherein: A sodium lamp was used as the light source.

18. The method for manufacturing a display device according to claim 11, wherein: The first conductive layer located on the inorganic insulating layer in the lower portion is formed of a titanium-based material, and the second conductive layer located between the first conductive layer and the upper portion is formed of an aluminum-based material.

19. The method for manufacturing a display device according to claim 18, wherein: The upper electrode is formed of a mixture of magnesium and silver.

20. The method for manufacturing a display device according to claim 19, wherein: The process of forming the laminated film includes: forming an organic layer including a light-emitting layer on the lower electrode; forming an upper electrode on the organic layer; and forming a capping layer on the upper electrode, When removing the sealing layer, a part of the lower portion and the cover layer are exposed, In the step of removing the upper electrode with the etching solution, a portion of the lower portion is exposed to the etching solution.

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