Self-rectification memristor array based on tantalum oxide and preparation method thereof

Abstract

The invention discloses a self-rectification memristor array based on tantalum oxide, the whole self-rectification memristor array adopts a sandwich structure, the self-rectification memristor array comprises a transversely arranged upper electrode, a tantalum oxide thin film and a longitudinally arranged lower electrode, and the upper electrode, the tantalum oxide thin film and the lower electrode are sequentially and vertically stacked and integrated on a silicon wafer substrate; the tantalum oxide thin film shows a resistance memory switching characteristic in the aspect of electrical characteristics. According to the self-rectification memristor array, the Pt / TaOx / Ti sandwich structure is adopted, and stable electrical performance is achieved. The device can keep consistent resistance change characteristics in multiple cycle tests, and has low read-write volatility and excellent reliability.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic manufacturing, and particularly to a self-rectifying memristor array based on tantalum oxide and a preparation method thereof. Background Art

[0002] With the rapid development of artificial intelligence and big data technologies, the traditional von Neumann architecture is difficult to meet the high-efficiency processing requirements under the bottleneck of separated storage and computing. As a new type of non-volatile memory device, the memristor has become one of the key technologies in the field of neuromorphic computing with its high-density storage capacity, low power consumption and multi-state characteristics. The memristor stores information by regulating the resistance state, has the advantages of simple structure and high-speed operation, and is very suitable for constructing an efficient memory-computation integrated system. In addition, the memristor can also simulate the behavior of neural synapses, providing a new idea for the research and development of brain-like computing chips.

[0003] However, in a high-density memristor array, the cross-coupling interference problem severely restricts its application. The traditional solution is to introduce a selection device, such as a diode (1S1R structure) or a transistor (1T1R structure), into the memristor cell to suppress the interference of the leakage path. However, these methods will significantly increase the manufacturing complexity and the array area, and reduce the device integration and cost-effectiveness.

[0004] The self-rectification effect, as an inherent current regulation mechanism, provides a new way to solve the cross-coupling problem. The memristor with self-rectifying characteristics can achieve functions similar to 1S1R or 1T1R without an external selection device, thus significantly simplifying the device structure and improving the array integration and operation efficiency. In addition, the highly non-linear I-V characteristics of the self-rectifying memristor can effectively suppress the leakage current in the array and improve the accuracy of data storage. However, the following deficiencies generally exist in the prior art: (1) the self-rectification ratio is not sufficient to completely suppress the cross-coupling interference in a high-density array; (2) the stability of the device in complex environments such as high temperature and high humidity has not been fully solved; (3) during long-term operation, the self-rectifying performance may degrade, affecting the overall device reliability. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a self-rectifying memristor array based on tantalum oxide with a simple structure and reliable operation, and provides a preparation method for the self-rectifying memristor array based on tantalum oxide with a simple process.

[0006] The technical solution of the present invention to solve the above technical problems is: a self-rectifying memristor array based on tantalum oxide, which adopts a sandwich structure as a whole, includes a horizontally arranged upper electrode, a tantalum oxide thin film, and a vertically arranged lower electrode. The upper electrode, the tantalum oxide thin film, and the lower electrode are vertically stacked and integrated on a silicon wafer substrate in sequence.

[0007] For the above self-rectifying memristor array based on tantalum oxide, the upper electrode is a strip-shaped Pt electrode, and the lower electrode is a strip-shaped Ti electrode.

[0008] For the above self-rectifying memristor array based on tantalum oxide, the tantalum oxide thin film exhibits resistive memory switching characteristics in terms of electrical properties.

[0009] For the above self-rectifying memristor array based on tantalum oxide, the thickness of the Pt electrode is 60 - 70 nm.

[0010] For the above self-rectifying memristor array based on tantalum oxide, the thickness of the Ti electrode is 40 - 60 nm.

[0011] For the above self-rectifying memristor array based on tantalum oxide, the thickness of the tantalum oxide thin film is 60 - 70 nm.

[0012] For the above self-rectifying memristor array based on tantalum oxide, the work function difference between the Pt electrode and the Ti electrode is greater than 1 eV.

[0013] A preparation method of a self-rectifying memristor array based on tantalum oxide includes the following steps:

[0014] Step 1: Spin-coat a double-layer photoresist on the substrate and heat it for drying. Use a mask plate for photolithography to pattern the lower electrode, and then use electron beam evaporation to deposit the lower electrode, that is, the Ti electrode;

[0015] Step 2: Prepare a tantalum oxide thin film on the substrate with the Ti electrode grown. Use a supporting insulating layer mask plate for photolithography to pattern the tantalum oxide thin film, and then use a magnetron sputtering device to deposit the tantalum oxide thin film;

[0016] Step 3: Photolithograph the upper electrode pattern on the substrate with the tantalum oxide thin film grown, and then use electron beam evaporation to deposit the upper electrode, that is, the Pt electrode.

[0017] For the above preparation method of the self-rectifying memristor based on tantalum oxide, in Step 2, deposit the tantalum oxide thin film in an environment with a vacuum degree of 6×10 -4 Pa, a working gas pressure of 1 Pa, and 50 sccm argon.

[0018] The beneficial effects of the present invention are as follows:

[0019] 1. High stability and repeatability: The self-rectifying memristor array of the present invention adopts Pt / TaO xThe / Ti sandwich structure achieves stable electrical performance. The device can maintain consistent resistive switching characteristics in multiple cycle tests, with low read / write fluctuations and excellent reliability. In addition, the device supports 32 stable resistance states, each with a uniform and repeatable resistance value distribution, which is helpful for high-precision storage and analog synaptic weight regulation.

[0020] 2. Self-rectifying characteristic improves the storage cell density: The self-rectifying memristor array of the present invention has a significant self-rectifying effect, showing asymmetric conductance characteristics under positive and negative voltages. This characteristic effectively suppresses the leakage current and reduces the sneak current problem in the crossbar array structure, thereby improving the density and read accuracy of the storage cells. Compared with traditional memristors, the present invention can improve the storage performance without additional peripheral circuits and is suitable for high-density storage devices.

[0021] 3. Suitable for neuromorphic computing: The self-rectifying memristor array of the present invention not only has excellent storage characteristics, but also can simulate the dynamic regulation of synaptic weights to achieve bio-like plasticity regulation. The device shows stable synaptic plasticity under continuous voltage stimulation, which is helpful for the implementation of hardware neural networks. In addition, its high stability and low power consumption characteristics make it suitable for large-scale neural network acceleration computing, improving the energy efficiency ratio and promoting the development of artificial intelligence hardware. Brief Description of the Drawings

[0022] Figure 1 It is a schematic structural diagram of the self-rectifying memristor array.

[0023] Figure 2 It is a microscope image of the self-rectifying memristor array.

[0024] Figure 3 It is a current-voltage curve graph of the self-rectifying memristor array.

[0025] Figure 4 It is a graph showing the variation of the switching ratio and rectification ratio of the self-rectifying memristor array with voltage.

[0026] Figure 5 It is a flow chart of the preparation method of the present invention. Detailed Embodiments

[0027] The following further describes the present invention with reference to the drawings and embodiments.

[0028] As Figure 1 、 Figure 2 shown, a self-rectifying memristor array based on tantalum oxide, with an overall sandwich structure, includes a horizontally arranged upper electrode 1, a tantalum oxide thin film 2, and a vertically arranged lower electrode 3. The upper electrode 1, the tantalum oxide thin film 2, and the lower electrode 3 are vertically stacked and integrated on a silicon wafer substrate in sequence.

[0029] The upper electrode 1 is a strip-shaped Pt electrode with a thickness of 60 - 70 nm; the lower electrode 3 is a strip-shaped Ti electrode with a thickness of 40 - 60 nm, and the difference in work function between the Pt electrode and the Ti electrode is greater than 1 eV.

[0030] Figure 2 Shown is the microscopic image of a self-rectifying memristor array with a size of 32×32, and the width of each electrode is 4 μm.

[0031] The tantalum oxide thin film 2 exhibits resistive memory switching characteristics in terms of electrical properties, and the thickness of the tantalum oxide thin film 2 is 60 - 70 nm.

[0032] As Figure 3 shown, Figure 3 It represents the current-voltage (I-V) curve of a single device in the array under direct current. This figure includes 100 cycles of the same device. The SET process is 0V—4V—0V, which switches the resistance state of the device from the high resistance state (HRS) to the low resistance state (LRS). The RESET process is 0V— -4V—0V, which switches the resistance state of the device from the low resistance state (LRS) to the high resistance state (HRS). As Figure 3 shown, when the voltage is 2.5V in absolute value, the current ratio (rectification ratio) corresponding to the negative low resistance state and the positive low resistance state is greater than 5×103. The device exhibits an ultra-high rectification ratio exceeding 5×103, effectively suppressing the leakage current in the crossbar array, thereby improving the reading accuracy and storage cell density. In addition, the device has good resistance state retention ability and repeatability, and can still maintain stable resistive switching characteristics in multiple cycle tests.

[0033] As Figure 4 shown, Figure 4 Quantitatively statistically analyzed the change trends and stabilities of the switching ratio and rectification ratio of the device in 100 direct current cycle scans. It can be seen from the thumbnail in the middle part that the fluctuations of the switching ratio and rectification ratio of the device at different voltages in 100 cycles are very small and the uniformity is very high. The switching ratio at 2V all exceeds 128, and the rectification ratio at the voltage of 3V all exceeds 1000. The whole Figure 4The quantitative analysis of the switching ratio and rectification ratio is shown, where σ is the standard deviation of the switching ratio and rectification ratio at different voltages during 100 cycles. The extremely low σ value highlights the high consistency and stability of the device performance, making it suitable for reliable operation in high-density memristor arrays. Even after 100 DC scanning cycles, the performance fluctuation of the self-rectifying memristor array is still extremely small. Since the device has small variations in both the switching ratio and rectification ratio during cycling, it may lead to a relatively small change in the resistance state during large-scale storage and reading. Therefore, this characteristic also endows the device with a more uniform resistance state distribution, making it more suitable for analog synaptic weight regulation and having broad application prospects in the field of neuromorphic computing.

[0034] A preparation method of a tantalum oxide-based self-rectifying memristor array, comprising the following steps:

[0035] Step 1: Spin-coat a bilayer photoresist on a substrate and heat it for drying. Use a mask plate for photolithography to pattern the bottom electrode, and then use electron beam evaporation to deposit the bottom electrode, i.e., a Ti electrode.

[0036] Step 2: Prepare a tantalum oxide thin film on the substrate with the Ti electrode grown. Use a matching insulating layer mask plate for photolithography to pattern the tantalum oxide thin film, and then use a magnetron sputtering device to deposit the tantalum oxide thin film in an environment with a vacuum degree of 6×10 -4 Pa, a working gas pressure of 1 Pa, and 50 sccm of argon.

[0037] Step 3: Photolithograph the top electrode pattern on the substrate with the tantalum oxide thin film grown, and then use electron beam evaporation to deposit the top electrode, i.e., a Pt electrode.

Claims

1. A tantalum oxide-based self-rectifying memristor array, characterized in that: The whole adopts a sandwich structure, including a horizontally arranged upper electrode, a tantalum oxide thin film, and a vertically arranged lower electrode. The upper electrode, the tantalum oxide thin film, and the lower electrode are vertically stacked and integrated on a silicon wafer substrate in sequence.

2. The self-rectifying memristor array based on tantalum oxide according to claim 1, characterized in that: The upper electrode is a strip-shaped Pt electrode, and the lower electrode is a strip-shaped Ti electrode.

3. The self-rectifying memristor array based on tantalum oxide according to claim 1, wherein: The tantalum oxide thin film exhibits resistive memory switching characteristics in terms of electrical properties.

4. The self-rectifying memristor array based on tantalum oxide according to claim 2, wherein: The thickness of the Pt electrode is 60 - 70 nm.

5. The self-rectifying memristor array based on tantalum oxide according to claim 2, characterized in that: The thickness of the Ti electrode is 40 - 60 nm.

6. The self-rectifying memristor array based on tantalum oxide according to claim 2, wherein: The thickness of the tantalum oxide thin film is 60 - 70 nm.

7. The self-rectifying memristor array based on tantalum oxide according to claim 2, characterized in that: The work function difference between the Pt electrode and the Ti electrode is greater than 1 eV.

8. A preparation method of a tantalum oxide-based self-rectifying memristor array, applied to the tantalum oxide-based self-rectifying memristor array described in any one of claims 1-7, characterized in that, It includes the following steps: Step 1: Spin-coat a double-layer photoresist on the substrate and heat it for drying. Use a mask plate to lithograph the pattern of the lower electrode, and then use electron beam evaporation to deposit the lower electrode, that is, the Ti electrode. Step 2: Prepare a tantalum oxide thin film on the substrate with the Ti electrode grown. Use a supporting insulating layer mask plate to lithograph the pattern of the tantalum oxide thin film, and then use a magnetron sputtering device to deposit the tantalum oxide thin film. Step 3: Lithograph the pattern of the upper electrode on the substrate with the tantalum oxide thin film grown, and then use electron beam evaporation to deposit the upper electrode, that is, the Pt electrode.

9. The preparation method of the tantalum oxide-based self-rectifying memristor according to claim 8, characterized in that, In the second step, tantalum oxide thin film is deposited in an environment with a vacuum degree of 6×10 -4 Pa, a working gas pressure of 1 Pa, and 50 sccm argon.

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