System and method for reducing grain internal stress and improving grain surface adhesion

Abstract

The present disclosure provides a die, an integrated circuit (IC) device including two or more stacked dies, and a process of forming a die. The die includes a circuit, a passivation layer disposed over the circuit and including a top side and a bottom side, and a polyimide layer disposed on the top side of the passivation layer, the top side of the passivation layer including portions of different respective heights extending vertically from the circuit, a top side of the polyimide layer opposite to a top side of the passivation layer includes portions of different respective heights extending vertically away from the circuit such that a surface area of the top side of the polyimide layer increases compared to a planar top side.

Description

Technical Field

[0001] The present disclosure relates to a die for an integrated circuit (IC) device having more than two stacked dies, and more particularly, to an improved die for reducing stress in an IC device having more than two stacked dies and improving surface adhesion. Summary of the Invention

[0002] According to the present disclosure, there is provided a die for a three-dimensional (3D) IC device, which is configured to adjust wafer bending and die-level warping, and / or to improve die surface adhesion between stacked dies. The die includes a circuit, a passivation layer disposed above the circuit and including a top side and a bottom side, and a polyimide layer disposed on the top side of the passivation layer, wherein the top side of the passivation layer includes portions of different respective heights extending vertically from the circuit.

[0003] In some embodiments, the top side of the passivation layer may include a plurality of protrusions extending from a base of the top side.

[0004] In some embodiments, each of the plurality of protrusions may include a respective side portion, each side portion being tapered such that the protrusion narrows as it extends away from the base.

[0005] In some embodiments, the side portions of one of the plurality of protrusions may each taper at an angle.

[0006] In some embodiments, the protrusions may include protrusions of different heights extending away from the base of the top side.

[0007] In some embodiments, each of the plurality of protrusions may be one of a trapezoidal prism, a pyramid, or a triangular prism.

[0008] In some embodiments, the arrangement and shape of the plurality of protrusions may be based on the lattice orientation of Si in the die and the circuit size.

[0009] In some embodiments, the top side of the polyimide layer opposite the top side of the passivation layer may include portions of different respective heights extending vertically away from the circuit, such that the surface area of the top side of the polyimide layer is increased compared to a planar top side.

[0010] In some embodiments, an IC device is provided. The IC device includes a substrate and a first die disposed on the substrate. The first die includes: a first circuit; a first passivation layer that includes a top side and a bottom side and is disposed above the first circuit; and a first polyimide layer disposed on the top side of the first passivation layer. The top side of the polyimide layer opposite to the top side of the passivation layer includes portions that extend away from the first passivation layer and have different respective heights. The IC further includes a die attach film (DAF) disposed on the top side of the first polyimide layer and a second die. The second die includes: a second circuit; a second passivation layer that includes a top side and a bottom side and is disposed above the first circuit, and a second polyimide layer that is disposed on the top side of the first passivation layer. The second die is vertically stacked on top of the first die and attached to the first die through the DAF, and the DAF bonds the top side of the first polyimide layer to the bottom side of the second circuit opposite to the second passivation layer.

[0011] In some embodiments, the IC device is a three-dimensional floating-gate NAND memory.

[0012] In some embodiments, a method for setting a passivation layer is provided. The method includes: disposing a passivation layer on a circuit layer, the passivation layer including a top side and a bottom side; and adjusting the thickness of a portion of the passivation layer such that the top side is non-planar.

[0013] In some embodiments, adjusting the thickness of the portion may include etching away the thickness of the portion from the top side of the passivation layer.

[0014] In some embodiments, adjusting the thickness of the portion may include applying a lithography process to the top side of the passivation layer to adjust the thickness of the portion.

[0015] In some embodiments, the lithography process may include using a mask having portions that allow different respective percentages of chromium leakage to reach the top side of the passivation layer to adjust the passivation thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following description includes a discussion of the drawings, which have illustrations given by way of example of implementations of embodiments of the present disclosure. The drawings should be understood by way of example and not by way of limitation. As used herein, a reference to one or more “embodiments” should be understood to describe specific features, structures, and / or characteristics included in at least one implementation. Thus, phrases such as “in one embodiment” or “in an alternative embodiment” that appear herein describe various embodiments and implementations, and do not necessarily all refer to the same embodiment, however, they are not necessarily mutually exclusive either.

[0017] Figure 1Shows a simplified cross - sectional view of a 3D IC device;

[0018] Figure 2 Shows an exemplary cross - sectional view of an IC device according to some embodiments of the present disclosure;

[0019] Figures 3A - 3C Shows a series of exemplary steps in a process for manufacturing a passivation layer (e.g.,) according to some embodiments of the present disclosure Figure 2 of;

[0020] Figure 4A and 4B Shows a series of exemplary steps in a process for manufacturing a polyimide layer (e.g.,) according to some embodiments of the present disclosure Figure 2 of;

[0021] Figure 5 Shows an exemplary cross - sectional view of a die according to some embodiments of the present disclosure;

[0022] Figure 6 Shows an exemplary cross - sectional view of another die according to some embodiments of the present disclosure;

[0023] Figures 7A - 7D Shows an exemplary top - view of the geometry of the top - side of a protective layer according to some embodiments of the present disclosure; and

[0024] Figure 8 Shows a flowchart of an exemplary process for manufacturing a die according to some embodiments of the present disclosure. Detailed Description

[0025] To increase the chip density in an IC device (e.g., a flash memory), multiple dies can be vertically stacked on a substrate (e.g., a 3D IC device). Figure 1 A simplified cross - sectional view of a 3D IC device 100 is shown. As shown, the IC device 100 includes a plurality of stacked dies 103a, 103b, 103n (collectively dies 103) vertically stacked (e.g., in the y - direction) on a substrate 101. Each die 103 includes a circuit layer 102 containing one or more ICs, a passivation layer 104 disposed above the circuit layer 102, and a polyimide layer 106 disposed above the circuit layer. As shown, die 103a is bonded to the substrate 101 through an adhesive layer 108a (such as DAF), die 103b is bonded to the polyimide layer 106 of die 103a through another adhesive layer 108b, and die 103n is bonded to the polyimide layer 106 of IC die 103b through another adhesive layer 108c. In this method, by vertically stacking multiple dies 103, the chip density of the IC device 100 can be increased without substantially increasing the footprint of the IC device 100.

[0026] In some methods, to further increase the chip density of the IC device 100, the wafer thickness (e.g., the thickness of the circuit layer 102) can be reduced and the number of vertically stacked dies 103 can be increased. However, as the wafer thickness is reduced and the number of vertically stacked dies 103 is increased (e.g., with each new generation of silicon (Si)), the likelihood of wafer-level bending and die-level warping increases. As a result, microcracks may occur in the passivation layer, the adhesion between stacked dies may be reduced (e.g., delamination), and cracks may occur in the wafer.

[0027] According to the present disclosure, there is provided a die for a 3D IC device, which is used to adjust wafer bending and die-level warping, and / or to improve the die surface adhesion between stacked dies.

[0028] Reference Figures 2 - 8 The subject matter of the present disclosure can be better understood.

[0029] Figure 2 An exemplary cross-sectional view of an IC device 200 according to some embodiments of the present disclosure is shown. In some embodiments, the IC device 200 can be a solid-state memory including one or more non-volatile memory die packages. For example, the IC device 200 can be a 3D NAND-based flash memory (e.g., using floating gate technology). However, this is only an example, and the IC device 200 can be any IC memory device (e.g., volatile memory) or non-memory device using an IC.

[0030] As shown, the IC device 200 can include a plurality of dies 203a, 203b, 203n (collectively referred to as dies 203) vertically stacked on a substrate 201 (e.g., a mounting substrate). Although only three dies 203 are shown, it should be understood that any suitable number of dies 203 can be vertically stacked on the substrate 201 (e.g., in the y-direction in the shown x-y plane). In one example, 16 dies 203 are vertically stacked on the substrate 201. However, this is only an example. The plurality of stacked dies 203 can include more or less than 16 stacked dies 203 (e.g., 2, 4, 8, 32, 64, 128, etc.), and the number need not be even. In some embodiments, as shown, the plurality of dies 203 can be stacked with a lateral offset (e.g., in the x-direction in the shown x-y plane) to expose the wire bond pad regions (220a, 220b, 220n) on each die 203 for interconnecting the dies 203 by wire bonding (e.g., shingled stacking or stepped configuration). However, it should be understood that the dies 203 can be arranged in other vertical stacking configurations, in which case other suitable wire bonding configurations can be used. For example, the dies 203 can also be edge-aligned (e.g., in which case wire-on-film bonding can be used).

[0031] As shown, each die 203 may include a circuit layer 202 that includes one or more ICs (collectively referred to as circuits), a passivation layer 204 disposed above the circuit layer 202, and a polyimide layer 206 disposed above the passivation layer 204. It should be understood that the die 203 may include other suitable layers, contact pads, and components (not shown). For example, a metal layer (e.g., an aluminum layer) may be disposed between the circuit layer 202 and the passivation layer 204. However, since these components are known to those skilled in the art, these components and other well-known components are not shown in order to simplify the description and discussion and not to obscure the present disclosure.

[0032] The substrate 201 may be a mounting substrate or a carrier substrate. As shown, the substrate 201 includes a top side 211, and a plurality of dies 203 may be stacked on the top side 211. The substrate 201 may include silicon, glass, epoxy resin, any other suitable material, or any combination thereof. In some embodiments, the substrate 201 may include one or more conductive pads configured to be connected to the circuit layer 202 (e.g., via solder bumps).

[0033] The circuit layer 202 may include one or more ICs formed on a silicon (Si) wafer. In some embodiments, the thickness of the Si wafer may be less than or equal to 55 micrometers (μm). However, this is merely an example, and the thickness of the Si wafer may be any suitable thickness (e.g., greater than 55 μm). In some embodiments, the Si wafer may include 100-degree or 110-degree lattice Si (e.g., an arrangement of the lattice structure within silicon). As shown, the circuit layer 202 includes a top side 212a and a bottom side 212b. Although a Si wafer is described, it should be understood that one or more ICs may be formed on other suitable wafer materials (e.g., gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC)). Additionally, the circuits formed on the wafer may include components that match the wafer material or components formed of different materials (e.g., GaAs components on a Si wafer).

[0034] The passivation layer 204 is disposed above the circuit layer 202 (e.g., in the y direction) and may protect the circuit layer 202 from damage (e.g., electrical and / or mechanical) and contamination (e.g., a first protective layer). In some embodiments, as described in more detail below, the passivation layer 204 may be a hard-coated protective layer manufactured using an improved wafer (hard coat) passivation process. Although the passivation layer 204 is shown as a single layer, it should be understood that the passivation layer 204 may include multiple layers (e.g., according to an improved passivation process). In some embodiments, the passivation layer 204 includes a combination of at least one silicon dioxide (SiO2) layer and / or a nitrogen oxide (ONON) layer.

[0035] As shown in the figure, the passivation layer 204 includes a top side 214a and a bottom side 214b. In some embodiments, the bottom side 214b may be a planar surface disposed above and facing the top side 212a of the circuit layer 202, while the top side 214a may be a non-planar surface including portions (e.g., multiple protrusions) of different corresponding heights extending vertically away from the circuit layer 202 (in the y direction). As explained in further detail below, the geometry of the top side 214a of the passivation layer 204 can be configured to adjust the wafer bow (of the circuit layer 202) and the warpage of the die 203 (e.g., die-level warpage) in the IC device 200.

[0036] The polyimide layer 206 is disposed on the top side 214a of the passivation layer 204. The polyimide layer 206 may be an insulating layer (e.g., a second protective layer) that further protects the die 203. In some embodiments, as described in more detail below, the polyimide layer 206 may be fabricated using an improved polyimide (soft coat) protective coating process. For example, the polyimide layer 206 may be fabricated using an improved polyimide mask layout design to achieve a defined exposure pattern to increase the surface area and reduce wafer bow / die warpage, as explained in more detail below. As shown in the figure, the polyimide layer 206 includes a top side 216a and a bottom side 216b. The bottom side 216b of the polyimide layer 206 may conform to the geometry of the top side 214a of the passivation layer 204 (e.g., due to being disposed on the top side 214a of the passivation layer 204), while the top side 216a of the polyimide layer 206 may be a non-planar surface including portions (e.g., multiple protrusions) of different corresponding heights extending vertically away from the passivation layer 204 (in the y direction). As explained in further detail below, the increased geometry of the top side 216a of the polyimide layer 206 can improve the die surface adhesion between stacked dies by increasing the surface area of the top side 216a of the polyimide layer 206 for the bonding layer 208b to bond to (e.g., compared to the planar top side shown Figure 1 in).

[0037] As shown, the first die 203a may be bonded to the substrate 201 via the adhesive layer 208a, which bonds the bottom side 212b of the circuit layer 202 of the first die 203a to the top side 211 of the substrate 201. The second die 203b may be bonded to the top side 216a of the polyimide layer 206 of the first die 203a via the adhesive layer 208b, which bonds the top side 216a of the polyimide layer 206 of the first die 203a (via the bottom surface 218b of the adhesive layer 208b) to the bottom side 212b of the circuit layer 202 of the second die 203b (via the top surface 218a of the adhesive layer 208b). Similarly, the third die 203n can be bonded to the top side 216a of the polyimide layer 206 of the second die 203a by the adhesive layer 208c, which bonds the top side 216a of the polyimide layer 206 of the second die 203a to the bottom side 212b of the circuit layer 202 of the third die 203n. In some embodiments, each of the adhesive layers 208a, 208b, 208c (collectively referred to as adhesive layers 208) may include a die attach film (DAF). In some embodiments, the DAF may include a thermosetting or thermoplastic resin.

[0038] Figures 3A - 3C According to some embodiments of the present disclosure, a method for manufacturing, for example, Figure 2 A series of exemplary steps in a process for forming a passivation layer 204 of the wafer. In some embodiments, the process is an improved wafer passivation process.

[0039] Figure 3A A passivation layer 204 is shown disposed on the circuit layer 202. In some embodiments, as shown, the passivation layer 204 (as provided) may have a substantially planar top surface. In addition, although the passivation layer 204 is shown as a single layer, it is to be understood that the passivation layer 204 may be composed of a plurality of layers disposed on top of each other, as described above. For example, the passivation layer 204 may include a combination of at least one SiO2 layer and / or an ONON layer. However, these are merely examples, and the passivation layer 204 may include any suitable layer.

[0040] Figure 3B Shown is applied to Figure 3A The photolithography process may include selectively leaking light (from light 302) around the chrome of the mask (or portion of the mask) 304 to allow different percentages of light ("leaking chrome") to reach the top side 214a of the passivation layer 204, thereby adjusting the thickness of the passivation layer 204 (e.g., during a subsequent etching step). The mask 304 may be configured with a pattern corresponding to the desired geometry of the top side 214a of the passivation layer 204. As described in reference Figures 7A - 7D Explained in more detail.

[0041] Figure 3C shows the final geometry of the top side 214a of the passivation layer 204 after an etching process following a lithography process at Figure 3B . As shown, the top side 214a of the passivation layer 204 includes a plurality of protrusions 310 that extend away from a base 312 (e.g., a lower height). As shown, corresponding sides 314 of each protrusion 310 are tapered such that the protrusions narrow as they extend away from the base 312. In some embodiments, the taper angle of the sides 314 can vary between 30 degrees and 45 degrees depending on the desired geometry for adjusting wafer bending and die-level warping. In some embodiments, the taper angle of the sides 314 can vary at other suitable degrees.

[0042] In some embodiments, wafer bending and die-level warping can be determined experimentally (e.g., by measuring wafer bending and die-level warping of the dies of an IC device (e.g., Figure 1 the IC device shown)). In some embodiments, wafer bending and die-level warping can be determined based on the design and configuration of the IC device. Based on the determined wafer bending and die-level warping, the shape and thickness of the passivation layer 204 can be adjusted to compensate for the determined wafer bending and die-level warping. For example, the shape and thickness of the passivation layer 204 can be adjusted to introduce geometries (shape, pattern, features, feature spacing, etc.) that provide the desired strength and stability for the desired application and compensate for the determined wafer bending and die-level warping. It should be understood that in the field of mechanical engineering, various geometries can provide desired results. Thus, the shape and thickness of the passivation layer 204 can be adjusted according to mechanical engineering principles to compensate for the determined wafer bending and die-level warping. For example, Figure 5 shows a passivation layer 204 having a geometry that provides the desired strength and stability for another IC device.

[0043] Although each of the plurality of protrusions 310 is shown as a trapezoidal prism, it should be understood that the protrusions 310 can be formed in other geometries, such as pyramidal, triangular prism, spherical, or any other suitable geometry based on known mechanical engineering principles. Additionally, although the plurality of protrusions 310 are shown as regularly spaced (e.g., along the x direction), it should be understood that the protrusions 310 can be irregularly spaced to provide the desired strength and stability for the desired application. In some embodiments, the arrangement and shape of the protrusions 310 are based on the lattice orientation of the Si in the circuit layer 202 (e.g., relative to the arrangement of the IC) and the size of the circuit layer 202. For example, the arrangement of the ICs of the dies relative to the lattice orientation of the Si of the wafer may contribute to wafer bending and die-level warping of the stacked dies. Thus, the arrangement and shape of the protrusions 310 can compensate for this wafer bending and die-level warping.

[0044] Figure 4A and4B illustrates a series of exemplary steps in a process for manufacturing a polyimide layer 206, such as Figure 2 In some embodiments, the process is an improved polyimide protection coating process.

[0045] Figure 4A illustrates the polyimide layer 206 disposed on the top side 214a of the passivation layer 204 (e.g., Figure 3B ). In some embodiments, as shown, the top side 216a of the polyimide layer 206 (as disposed) may be substantially planar. However, this is merely an example, and due to being disposed on the top side 214a of the passivation layer 204, the top side 216a of the polyimide layer 206 may retain some of the geometry of the top side 214a of the passivation layer 204.

[0046] Figure 4B illustrates the final geometry of the top side 216a of the polyimide layer 206 after an adjustment process. In some embodiments, the adjustment process may be the lithography (and etching) process described above with reference to Figure 3B . In some embodiments, the adjustment process may be a pad etching process. As shown, the top side 216a of the polyimide layer 206 includes a plurality of protrusions 410 extending away from a base 412 (e.g., a lower height). As shown, the respective side portions 414 of each protrusion 410 are tapered such that the protrusion narrows as it extends away from the base 412. In some embodiments, the taper angle of the side portions 414 may vary between 30 degrees and 45 degrees. However, this is merely an example, and as Figure 5 shown, the respective side portions 414 of each protrusion 410 may not be tapered. In some embodiments, the taper angle of the side portions 414 may vary at other suitable degrees. In some embodiments, the thickness of the polyimide layer 206 may be adjusted between 1.7 μm and 3.5 μm. However, this is merely an example, and the thickness of the polyimide layer 206 may be any suitable thickness.

[0047] In some embodiments, because the top side 216a of the polyimide layer 206 is a non-planar surface, the surface area of the top side 216a of the polyimide layer 206 is increased (e.g., compared to a planar surface). Accordingly, the adhesion to the adhesive layer 208 can be improved, thereby enhancing Figure 2 the adhesion between the die surfaces of the stacked dies 203.

[0048] Figure 5 illustrates an exemplary cross-section of a die 500 according to some embodiments of the present disclosure, and the die 500 may correspond to Figure 2For the grains 203, except that the geometries of the top surface 505 of the passivation layer 504 and the top surface 507 of the polyimide layer 506 can be configured differently to provide desired strength and stability for another application. For example, as shown in the figure, the top surface 505 of the passivation layer 504 can gradually descend towards the center of the grain 500, while the top surface 507 of the polyimide layer 506 can include a plurality of protrusions 508 extending away from the passivation layer 504 and formed by removing the pyramidal portion 510 of the top surface.

[0049] Figure 6 An exemplary cross-sectional view of a grain 600 according to some embodiments of the present disclosure is shown. In some embodiments, when it is not necessary to adjust the passivation layer 604 to adjust the wafer bending of the (circuit layer 202) and the warping of the grain 203 (e.g., grain-level warping) (e.g., for a circuit layer 202 with a large wafer thickness), it may still be necessary to improve the adhesion between stacked grains. For example, as shown in the figure, the passivation layer 604 can include a planar top side 605, while the top side 607 of the polyimide layer 606 can include a plurality of rectangular protrusions (e.g., formed by a pad etching process) to increase the surface area of the top side 607 of the polyimide layer 606. However, this is only an example, and the top side 607 of the polyimide layer 606 can be adjusted in any suitable manner.

[0050] Figures 7A - 7D An exemplary top view of the geometry of the top side of a protective layer according to some embodiments of the present disclosure is shown. The top sides (700a, 700b, 700c, 700d) can correspond to any top side of the above-mentioned passivation layer (204 or 504) or polyimide layer (206, 506 or 606). In some embodiments, Figures 7A - 7D the patterns shown can correspond to the patterns of the photomasks (e.g., the photomask 304 in FIG. 3) used in the above-mentioned lithography process steps for creating the geometries of the respective top sides. It should be understood that the patterns shown can represent the shapes of the bases of the features, but the side profiles of the features can be adjusted at the angles as described above (e.g., by a 45-degree adjustment process, or any other suitable angle). Although four patterns are shown, these are only examples, and the geometry of the top side of the protective layer can have any suitable pattern according to the desired strength and stability of the desired application.

[0051] Figure 7A An exemplary top view of the top side 700a of a protective layer is shown. The top side 700a can include a plurality of square portions 701a where the thickness of the protective layer is reduced. As shown, the plurality of square portions 701a can be arranged in a checkerboard pattern.

[0052] Figure 7BAn exemplary top view of the top side 700b of the protective layer is shown. The top side 700b may include a plurality of circular portions 701b where the thickness of the protective layer is reduced. As shown, the plurality of circular portions 701b may be arranged in a checkerboard pattern.

[0053] Figure 7C An exemplary top view of the top side 700c of the protective layer is shown. The top side 700c may include a plurality of rectangular portions 701c where the thickness of the protective layer is reduced. As shown, the plurality of rectangular portions 701c may be regularly spaced from each other, but may have different sizes.

[0054] Figure 7D An exemplary top view of the top side 700d of the protective layer is shown. The top side 700d may include a plurality of rectangular portions 701d where the thickness of the protective layer is reduced. As shown, the density of the rectangular portions 701d may increase in the x - direction. Additionally, the size of the rectangular portions 701d may vary based on the desired strength and stability of the desired application.

[0055] Figure 8 A flowchart of an exemplary process 800 for fabricating a die in accordance with some embodiments of the present disclosure is shown.

[0056] In step 802, a circuit is provided, which may be the circuit layer 202 as described above in Figure 2 .

[0057] In step 804, a passivation layer (e.g., a first protective layer) is disposed over the circuit. The passivation layer may be the passivation layer 204 (or 504) as described above in Figure 2 and 5 .

[0058] In step 806, the thickness of portions of the top side of the passivation layer is adjusted to form portions of different respective heights extending vertically away from the circuit. For example, a lithography (and etching) process may be applied to the top side 214a of the passivation layer 204 as described above in Figure 3B and 3C . The passivation layer may also be the passivation layer 504 as described in Figure 5 . As described above, the final geometry of the top side of the passivation layer may compensate for the determined wafer bow and die - level warpage of the die 203.

[0059] In step 808, a polyimide layer may be disposed on the top side of the passivation layer. The polyimide layer may be the polyimide layer 206 as described above in Figure 4A .

[0060] In step 810, the thickness of portions of the top side of the adjustable polyimide layer is adjusted to form portions of different respective heights that extend vertically away from the passivation layer. For example, a lithography and / or etching process may be applied to the top side 216a of the polyimide layer 206, as described above in Figure 4B above. The polyimide layer may also be polyimide layer 506 or 606, as described above in Figure 5 and 6 above. The final geometry of the top side of the polyimide layer may increase the surface area of the top side (e.g., compared to a planar surface), thereby improving the die surface adhesion between stacked dies, as described above.

[0061] The foregoing are merely illustrative of the principles of the present disclosure, and those skilled in the art can make various modifications without departing from the scope of the present disclosure. The above embodiments are presented for illustrative rather than limiting purposes. The present disclosure may also take many forms other than those explicitly described herein. Therefore, it is emphasized that the present disclosure is not limited to the explicitly disclosed methods, systems, and devices, but is intended to cover variations and modifications within the spirit of the following claims.

Claims

1. A die, comprising: A circuit; A passivation layer, including a top side and a bottom side, the passivation layer disposed above the circuit, wherein the top side of the passivation layer includes portions of different corresponding heights extending vertically away from the circuit; And A polyimide layer, disposed on the top side of the passivation layer.

2. The crystal grains according to claim 1, wherein, The top side of the passivation layer includes a plurality of protrusions extending away from a base of the top side.

3. The die according to claim 2, wherein each of the plurality of protrusions includes a respective side portion, and the respective side portion of each of the plurality of protrusions is tapered such that the protrusion narrows as it extends away from the base.

4. The crystal grain according to claim 3, wherein, The side portions of the protrusions among the plurality of protrusions are tapered at an angle.

5. The grain according to claim 2, wherein, The protrusions include protrusions of different heights extending away from the base of the top side.

6. The crystal grain as claimed in claim 2, wherein, Each of the plurality of protrusions is one of a trapezoidal prism, a pyramid, or a triangular prism.

7. The grain according to claim 2, wherein, The arrangement and shape of the plurality of protrusions are based on the lattice orientation of silicon in the die and the size of the circuit.

8. The grain according to claim 1, wherein, The top side of the polyimide layer opposite to the top side of the passivation layer includes portions of different corresponding heights extending vertically away from the circuit, such that the surface area of the top side of the polyimide layer is increased compared to a planar top side.

9. An integrated circuit (IC) device, comprising: A substrate; A first die disposed on the substrate, the first die including: A first circuit; A first passivation layer, including a top side and a bottom side, the first passivation layer disposed above the first circuit; and A first polyimide layer, disposed on the top side of the first passivation layer, wherein the top side of the polyimide layer opposite to the top side of the passivation layer includes portions of different corresponding heights extending away from the first passivation layer; A die attach film (DAF), disposed on the top side of the first polyimide layer; and A second die, including: A second circuit; A second passivation layer, including a top side and a bottom side, the second passivation layer disposed above the first circuit; and A second polyimide layer, disposed on the top side of the first passivation layer, Wherein the second die is vertically stacked on top of the first die and attached to the first die through the DAF, and the DAF bonds the top side of the first polyimide layer to the bottom side of the second circuit opposite to the second passivation layer.

10. The IC device according to claim 9, wherein, The top side of the first polyimide layer includes a plurality of protrusions extending away from a base of the top side.

11. The IC device according to claim 10, wherein, Each of the plurality of protrusions includes a respective side portion, and wherein the respective side portion of each of the plurality of protrusions is tapered such that the protrusion narrows as it extends away from the base.

12. The IC device according to claim 11, wherein, The side portions of the protrusions among the plurality of protrusions are tapered at an angle.

13. The IC device according to claim 10, wherein, Each of the plurality of protrusions is one of a trapezoidal prism, a pyramid, or a triangular prism.

14. The IC device according to claim 9, wherein, The portions of different corresponding heights of the first polyimide layer increase the surface area of the top side of the first polyimide layer compared to a planar top side.

15. The IC device according to claim 9, wherein: The top side of the first passivation layer includes portions of different respective heights extending vertically away from the first circuit; and The top side of the second passivation layer includes portions of different respective heights extending vertically away from the second circuit.

16. The IC device according to claim 9, wherein, The IC device is a three-dimensional floating gate NAND memory.

17. A method for setting a passivation layer, the method comprising: Setting the passivation layer on a circuit layer, the passivation layer including a top side and a bottom side; And Adjusting the thickness of portions of the passivation layer such that the top side is non-planar.

18. The method of claim 17, wherein adjusting the thickness of the portions includes etching away the thickness of the portions from the top side of the passivation layer.

19. The method of claim 17, wherein adjusting the thickness of the portions includes applying a lithography process to the top side of the passivation layer to adjust the thickness of the portions.

20. The method of claim 19, wherein the lithography process includes using a mask having portions that allow different respective percentages of chrome leakage to reach the top side of the passivation layer to adjust the passivation thickness.

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