IEC protection of high frequency terminals

Abstract

An ESD trigger circuit for protecting a pass transistor coupled with an integrated circuit terminal is provided. The integrated circuit terminal is coupled with the voltage node through the diode. In response to an electrostatic shock at the integrated circuit terminal, the diode conducts charge to the voltage node to apply a pulse to a voltage of the voltage node. The ESD trigger circuit responds to the pulse of the voltage by coupling a voltage node to the gate of the pass transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of U.S. Patent Application No. 18 / 070,414, filed on November 28, 2022, the disclosure of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes. Technical Field

[0003] This application relates to electrostatic discharge (ESD) circuits for protecting terminals according to International Electrotechnical Commission (IEC) standards, and more particularly to ESD circuits that provide IEC protection for high - frequency terminals. Background Art

[0004] The fabrication of integrated circuits and their assembly into electronic devices are typically carried out under controlled ESD conditions. Due to ESD prevention measures taken during fabrication and assembly, potential ESD stresses from contact with technicians are relatively suppressed. To simulate such stresses, the human - body model (HBM) has been developed. Due to the ESD prevention measures taken during fabrication and assembly, the stress from the HBM is not as severe as the stress developed by the International Electrotechnical Commission (IEC) for modeling the ESD stresses that an electronic device may experience from an end - user. Therefore, integrated - circuit terminals must withstand voltage levels and current levels significantly greater than the HBM levels to meet IEC standards.

[0005] To meet IEC standards and thus accommodate such high voltage levels and current levels, integrated - circuit terminals are typically coupled to a robust ESD clamping circuit (which may also be referred to as an ESD triggering circuit) that can conduct the increased charge quantity from the integrated - circuit terminal to a voltage node such as ground or a power - supply voltage rail. A clamping circuit that can safely accommodate IEC charge levels will typically load a large amount of capacitance onto the integrated circuit. This increased capacitive loading by the IEC clamping circuit may result in an unacceptable bit - error rate for high - speed (and thus high - frequency) data signaling. Summary of the Invention

[0006] According to one aspect of the present disclosure, there is provided an electrostatic discharge (ESD) circuit, comprising: an integrated - circuit terminal; a pass transistor having a drain coupled to the integrated - circuit terminal; a voltage node; a first ESD diode coupled between the integrated - circuit terminal and the voltage node; and an ESD triggering circuit coupled between the gate of the pass transistor and the voltage node, the ESD triggering circuit being configured to couple the gate of the pass transistor to the voltage node in response to an electrostatic shock to the integrated - circuit terminal and to isolate the gate of the pass transistor from the voltage node in the absence of an electrostatic shock to the integrated - circuit terminal.

[0007] According to another aspect of the present disclosure, there is provided an electrostatic discharge method, including the following operations: receiving charge from an electrostatic shock at a terminal of an integrated circuit; conducting the charge from the terminal to a voltage node through a diode to apply a pulse to the voltage of the voltage node; and coupling the voltage node to a gate of a transfer transistor in response to detecting a pulse in the voltage of the voltage node, the transfer transistor having a drain coupled to the terminal.

[0008] According to still another aspect of the present disclosure, there is provided an electrostatic discharge (ESD) circuit, including: an integrated circuit terminal; a node for a high-speed data signal; a transfer transistor coupled between the node for the high-speed data signal and the integrated circuit terminal; and an ESD trigger circuit configured to couple a power node for a power supply voltage to the gate of the transfer transistor in response to a positive electrostatic shock to the integrated circuit terminal.

[0009] According to still another aspect of the present disclosure, there is provided an electrostatic discharge (ESD) circuit, including: an integrated circuit terminal; a node for a high-speed data signal; a transfer transistor coupled between the node for the high-speed data signal and the integrated circuit terminal; and an ESD trigger circuit configured to couple a negative voltage node for a negative voltage to the gate of the transfer transistor in response to a negative electrostatic shock to the integrated circuit terminal.

[0010] These and other advantageous features can be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a circuit diagram of an integrated circuit including an ESD trigger circuit according to an aspect of the present disclosure, the ESD trigger circuit being configured to apply a pulse to the voltages of a gate and a bulk of a transfer transistor coupled to an integrated circuit terminal.

[0012] Figure 2 is a circuit diagram of an integrated circuit having an ESD circuit for protecting an NMOS transfer transistor according to an aspect of the present disclosure.

[0013] Figure 3 is a circuit diagram of an exemplary ESD circuit for protecting an NMOS transfer transistor according to an aspect of the present disclosure.

[0014] Figure 4 is a circuit diagram of an integrated circuit having an ESD circuit for protecting a PMOS transfer transistor according to an aspect of the present disclosure.

[0015] Figure 5 is a circuit diagram of an exemplary ESD circuit for protecting a PMOS transfer transistor according to an aspect of the present disclosure.

[0016] Figure 6 is a flowchart of an operation method of an ESD circuit according to an aspect of the present disclosure.

[0017] Figure 7 Illustrates some example electronic systems including an ESD circuit according to an aspect of the present disclosure.

[0018] Embodiments of the present disclosure and their advantages are best understood by reference to the detailed description below. It should be understood that like reference numerals are used to identify like elements illustrated in one or more of the figures. Detailed Description

[0019] When the terminals of an integrated circuit are used not only to transmit (or receive) high-speed data during a high-speed data operation mode but also to transmit (or receive) an audio signal during an audio operation mode, the increased capacitive loading from the IEC clamping circuit is particularly problematic. Figure 1 A dual-mode integrated circuit 100 is shown, which has both a high-speed data mode and an audio operation mode. The integrated circuit 100 includes a differential terminal pair formed by a universal serial bus (USB) data positive (DP) terminal and a data negative (DN) terminal. The ESD diode D1 has an anode coupled to the DP terminal and a cathode coupled to a node for the power supply voltage Vdd. Similarly, the ESD diode D2 has an anode coupled to a negative voltage node or rail for the negative voltage Vneg and a cathode coupled to the DP terminal. The DN terminal is protected by a pair of similar ESD diodes D3 and D4. The anode of diode D3 is coupled to the DN terminal, while its cathode is coupled to the power supply node. The anode of diode D4 is coupled to the negative voltage rail, while its cathode is coupled to the DN terminal.

[0020] Diodes D1, D2, D3, and D4 protect terminals DP and DN from charges at the HBM level, but do not provide IEC ESD protection. To provide IEC ESD protection, integrated circuit 100 may include an ESD clamping circuit coupled to terminals DP and DN. An ESD clamping circuit that can accommodate electrostatically induced charges of IEC amounts, as defined herein, is denoted as an IEC clamping circuit. However, such an IEC clamping circuit will load terminals DP and DN with a capacitance of several tens of picofarads, as will be further discussed herein. During high-speed data operation mode, integrated circuit 100 may generate a DP signal (DPin) that is coupled to an external device (not shown) through switch S1 and the DP terminal, and the external device is coupled to the DP terminal through USB plug 105. Similarly, integrated circuit 100 may generate a DN signal (DNin) that is coupled to the external device through switch S3 and the DN terminal via USB plug 105. Due to the bidirectionality of the DP and DN terminals, the external device may alternatively drive the DP and DN terminals such that the DPin and DNin signals are received signals rather than signals generated by integrated circuit 100.

[0021] During audio operation mode, integrated circuit 100 may generate a headphone right (HPHR) signal and a headphone left (HPHL) signal. Alternatively, these audio signals may be generated by another integrated circuit and routed to integrated circuit 100. The HPHR signal is coupled to the DP terminal through switch S2. Similarly, the HPHL signal is coupled to the DN terminal through switch S4. Switches S1 and S3 are open during audio operation mode. Similarly, switches S2 and S4 are open during high-speed data operation mode.

[0022] To transmit both strong binary 1 and strong binary 0, switches S1 and S3 may be constructed using transmission gates that include both n-type metal-oxide-semiconductor (NMOS) transmission transistors and p-type metal-oxide-semiconductor (PMOS) transmission transistors. Alternatively, switches S1 and S3 may be constructed using only a single transmission transistor of either polarity. The (one or more) transmission transistors used to construct switches S1 and S3 are off during audio operation mode and on during high-speed data mode. Switches S2 and S4 may also be constructed using transmission transistors. Although the transmission transistors forming switches S2 and S4 are off during high-speed data operation mode, these transmission transistors and the associated audio drive circuits (not illustrated) load the DP terminal and the DN terminal with capacitance. Thus, if the DP terminal and the DN terminal are coupled to the IED clamping circuit, this capacitive loading may become unsustainable.

[0023] To avoid capacitive loading from the IED clamping circuit, integrated circuit 100 includes an ESD trigger circuit 110 that responds to charging caused by an electrostatic shock to an integrated circuit terminal (such as a DP or DN terminal) by applying a pulse to the voltages of the gates and bases of transfer transistors that form switches coupled to the integrated circuit terminals. The ESD trigger circuit 110 may also be represented as an RC clamping circuit or an edge-triggered RC clamping circuit. Since the ESD trigger circuit 110 is not coupled to the DP and DN terminals, these terminals are not loaded with the capacitance of the IEC clamping circuit, but the transfer transistor(s) coupled to the integrated circuit terminals are protected from charges caused by electrostatic shocks at the IEC level.

[0024] To provide a better understanding of the function of the ESD trigger circuit 110, an example NMOS transfer transistor M1 in integrated circuit 200 is shown in Figure 2 . The transfer transistor M1 may be used to form switches S1 or S3, as discussed for integrated circuit 100. A plurality of audio transfer transistors 210 form switches S2 and S4, also as discussed for integrated circuit 100. The drain of the transfer transistor M1 and the drains of the audio transfer transistors 210 (not illustrated) are both coupled to the integrated circuit terminal DX. The integrated circuit terminal DX is a general representation of either of the terminals DP and DN of integrated circuit 100. In this regard, the following discussion will assume that the high-speed data operation mode is the USB operation mode. However, it will be understood that the IEC ESD protection of the ESD trigger circuit disclosed herein may be applied to other types of high-speed data protocols.

[0025] In the audio operation mode, the audio signal conducted through the audio transmission transistor 210 can be positive or negative in voltage. To ensure that the transmission transistor M1 remains off during the audio mode in the presence of such a negative signal, the controller 205 makes the gate voltage of the transistor M2 effective, which is coupled between the negative voltage node for the negative voltage Vneg and the gate of the transmission transistor M1. In this way, the gate of the transmission transistor M1 is charged to the negative voltage Vneg during the audio operation mode to ensure that the transmission transistor M1 is non-conductive. During the high-speed data operation mode, the controller 205 turns off the transistor M2 and turns on another transistor (not illustrated) coupled between the gate of the transmission transistor M1 and the power supply node for the power supply voltage Vdd. Thus, the transmission transistor M1 is conductive during the high-speed data operation mode, enabling the high-speed data signal to be conducted through the transmission transistor M1 to the integrated circuit terminal DX. The transistor M3 is coupled between the base of the transmission transistor M1 and the negative voltage node. A controller such as the controller 205 uses the Vbulk control signal to control the gate voltage of the transistor M3 such that the transistor M3 is conductive during the audio mode to bias the base voltage Vbias of the transmission transistor to the negative voltage Vneg.

[0026] Although the charging caused by the electrostatic shock of the DX terminal can be positive or negative, it can be shown that the positive electrostatic charge poses a danger to the NMOS transmission transistor (such as the transmission transistor M1). In contrast, the negative electrostatic charge poses a danger to the PMOS transmission transistor ( Figure 2 not shown in the figure but further discussed herein). The ESD trigger circuit 110 is universal for the polarity of the transmission transistor, but in the exemplary embodiment, there is a separate trigger circuit for protecting the NMOS transmission transistor compared to the trigger circuit for protecting the PMOS transmission transistor. For the transmission transistor M1, the NMOS transmission transistor protection ESD trigger circuit 215 is coupled between the power supply node for the power supply voltage Vdd and the gate of the transistor M1. During normal operation (without the electrostatic shock of the DX terminal), the ESD trigger circuit 215 isolates the power supply node from the gate of the transmission transistor M1. However, in response to the positive electrostatic charging of the DX terminal, the ESD trigger circuit 215 couples the power supply node to the gate of the transistor M1.

[0027] To provide additional ESD protection against positive electrostatic charge, the DX terminal is coupled to the power supply node through the Dpositive diode, which is a generic representation of diode D1 or diode D3 of integrated circuit 100. Similarly, to provide ESD protection against negative electrostatic charge, the DX terminal is coupled to the negative voltage node Vneg through the Vnegative diode, which is a generic representation of diode D2 or diode D4 of integrated circuit 100. In the presence of positive electrostatic charging of the DX terminal, the Dpositive diode becomes forward biased, allowing the positive charge to conduct to the power supply node. The ESD trigger circuit 215 responds to the resulting positive pulse in the supply voltage Vdd by coupling the power supply node to the gate of transistor M1. This coupling through the ESD trigger circuit 215 causes the gate voltage of the transfer transistor M1 to also pulse positively. Since transistor M2 is conducting, the pulse in the gate voltage of the transfer transistor M1 conducts through transistor M2 to raise the negative voltage of the negative voltage Vneg. In the case where transistor M3 is also conducting during the audio operation mode, applying a positive pulse to the negative voltage Vneg causes the base voltage Vbulk of the transfer transistor M1 to also pulse high. In this way, the gate-to-drain voltage and the gate-to-base voltage of the transfer transistor M1 are maintained at a safe level, even though the DX terminal is suddenly exposed to IEC-level positive electrostatic charge.

[0028] The IEC level of the positive static charge on terminal DX can raise the voltage of terminal DX to approximately 10 V (albeit briefly). It will be understood that this voltage value is exemplary and other values can be used. Similarly, the negative voltage Vneg of -2 V is also exemplary and can be varied in alternative embodiments. If the negative voltage Vneg is -2 V and terminal DX is charged to 10 V, in the absence of the ESD trigger circuit 215, the gate-to-drain voltage of the transfer transistor M1 will be approximately -12 V. Such a relatively large gate-to-drain voltage may damage the transfer transistor M1. However, through the protection action of the ESD trigger circuit 215, the gate voltage will also be pulsed high briefly, such as to approximately up to 7.5 V. Thus, the gate-to-drain voltage of the transfer transistor M1 is approximately only -2.5 V, which is easily tolerated. Similarly, the base voltage Vbulk of the transfer transistor M1 can be pulsed to approximately 5 V through the conduction of the ESD trigger circuit 215. The base-to-drain voltage of the transfer transistor in response to a positive electrostatic shock is thus limited to approximately 5 V, which is also tolerated by the transfer transistor M1. Note that the ESD trigger circuit 215 does not load the DX terminal, but instead indirectly detects the pulse of the DX terminal voltage by detecting the generated pulse of the supply voltage Vdd. In this way, the ESD trigger circuit 215 advantageously does not load the DX terminal with additional capacitance. In contrast, a conventional IEC clamping circuit would load the terminal DX with a large amount of capacitance (e.g., dozens of picofarads). Thus, the ESD trigger circuit 215 is very advantageous for providing IEC ESD protection without any significant capacitive loading of the DX terminal. In this way, the DX terminal has an appropriately low level of capacitive loading for high-speed data signaling.

[0029] An example circuit embodiment 300 of the ESD trigger circuit 215 is shown in Figure 3is shown. However, it will be understood that many alternative embodiments can construct an edge-triggered circuit that functions during normal conditions to isolate the power node from the transfer transistor gate and responds to a sudden increase in the power voltage by coupling the transfer transistor gate to the power node. The ESD trigger circuit 300 includes a low-pass filter, such as a low-pass RC filter formed by a series combination of resistor R1 and capacitor C1. Resistor R1 has a terminal coupled to the power node for the power voltage Vdd. In contrast, capacitor C1 has a terminal coupled to the ground node Vss. Due to the low-pass filtering, the voltage Vfilter at node 305 between resistor R1 and capacitor C1 will be equal to the default (non-electrostatic shock) value of the power voltage Vdd. Node 305 is coupled to the gate of PMOS transistor P1, and PMOS transistor P1 has a source coupled to the power node. During normal operation, transistor P1 is thus off. In response to a sudden increase in the power voltage Vdd, voltage Vfilter decreases to turn on transistor P1. The drain of transistor P1 is coupled to the ground node through resistor R2 in series with capacitor C2. Thus, the voltage at node 310 between resistor R2 and capacitor C2 will rise in response to an increase in the power voltage Vdd. Node 310 is coupled to the gate of NMOS transistor M4, and NMOS transistor M4 has a source coupled to ground. Transistor M4 will thus turn on in response to a pulse in the power voltage Vdd. The drain of transistor M4 is coupled to the power node through resistor R3. The turn-on of transistor M4 causes its drain voltage to drop. The drain of transistor M4 is coupled to PMOS transistor P2, and PMOS transistor P2 has a source coupled to the power node. The discharge of the drain voltage of transistor M4 in turn turns on transistor P2. The drain of transistor P2 is coupled to the transfer transistor gate, such as the gate of transfer transistor M1 ( Figure 3 not shown in). Transistor P3 is biased by the bias voltage Vbias to be in saturation. Thus, the transfer transistor gate will be pulsed high by the ESD trigger circuit 300 in response to an electrostatic shock at terminal DX. In this way, the base and gate of the transfer transistor protected by the ESD trigger circuit 300 will be pulsed high in voltage as discussed for transfer transistor M1.

[0030] As previously mentioned, the transfer transistor can also be a PMOS transistor. An example PMOS transfer transistor P4 in the integrated circuit 400 is in Figure 4is shown. The transfer transistor P4 can be used to form the switches S1 or S3 as discussed for the integrated circuit 100. The audio transfer transistors 210 form the switches S2 and S4 as also discussed for the integrated circuit 100. If these audio transfer transistors 210 are PMOS transistors, they can be protected from ESD similar to that discussed for the transfer transistor P4. The drain of the transfer transistor P4 and the drains (not illustrated) of the audio transfer transistors 210 are both coupled to the integrated circuit terminal DX, which is a general representation of either of the terminals DP and DN of the integrated circuit 100. As described above, it will be understood that the IEC ESD protection performed by the ESD trigger circuit disclosed herein can be applied to other types of high-speed data protocols in addition to USB.

[0031] To ensure that the transfer transistor P4 remains off during the audio mode, the controller 405 grounds the gate voltage Vcontrol of the PMOS transistor P5, which is coupled between the power supply node and the gate of the transfer transistor P4. In this way, during the audio operation mode, the gate of the transfer transistor P4 is charged to the power supply voltage Vdd to ensure that the transfer transistor P4 does not conduct. During the high-speed data operation mode, the controller 405 turns off the transistor P5 and turns on another transistor (not illustrated) coupled between the gate of the transfer transistor P4 and the ground node. Thus, the transfer transistor P4 is on during the high-speed data operation mode, allowing the high-speed data signal to conduct through the transfer transistor M4 to the integrated circuit terminal DX. The PMOS transistor P6 is coupled between the base of the transfer transistor P4 and the power supply node. A controller such as the controller 405 uses the Vbulk control signal to control the gate voltage of the transistor P6 such that the transistor P6 is on during the audio mode to bias the base voltage Vbias of the transfer transistor P4 to the power supply voltage Vdd.

[0032] Although the charging caused by an electrostatic shock on the DX terminal can be positive or negative, it can be shown that it is the negative electrostatic charge that poses a danger to the PMOS transfer transistors such as the transfer transistor P4. As previously mentioned, the ESD trigger circuit 110 is generic with respect to the polarity of the transfer transistors, but in the exemplary embodiment, there is a separate trigger circuit for protecting NMOS transfer transistors compared to the ESD trigger circuit for protecting PMOS transfer transistors. For the transfer transistor M4, the PMOS transfer transistor protection ESD trigger circuit 415 is coupled between the negative voltage node and the gate of the transfer transistor P4. During normal operation (without an electrostatic shock on the DX terminal), the ESD trigger circuit 415 isolates the negative voltage node from the gate of the transfer transistor P4. However, in response to a negative electrostatic charge on the DX terminal, the ESD trigger circuit 415 couples the negative voltage node to the gate of the transfer transistor P4.

[0033] To provide additional ESD protection against negative electrostatic charge, the DX terminal is coupled to the negative voltage node through the Dnegative diode, which is a generic representation of diode D2 or diode D4 of integrated circuit 100. Similarly, to provide ESD protection against positive electrostatic charge, the DX terminal is coupled to the power supply node through the Dpositive diode, which is a generic representation of diode D1 or diode D3 of integrated circuit 100. In the presence of negative electrostatic charging of the DX terminal, the Dnegative diode becomes forward biased, causing the negative charge to conduct to the negative voltage node Vneg. The nominal value of the negative voltage can be -2 V, but in the presence of negative electrostatic charging of the DX terminal, the negative voltage can be pulled substantially more negative, such as to approximately -10 V. It should be understood that such voltage values are merely exemplary and can be higher or lower, depending on the exact amount of negative electrostatic charge delivered to the DX terminal and the voltage of the negative voltage node. The trigger circuit 415 responds to the resulting negative pulse of the negative voltage node Vneg by coupling the negative voltage node to the gate of the transfer transistor P4. This coupling through the ESD trigger circuit 415 causes the gate voltage of the transfer transistor P4 to also pulse negatively. Since transistor P5 is on, the negative pulse of the gate voltage of the transfer transistor P4 conducts through transistor P5 to negatively pulse the power supply voltage Vdd. Since transistor P6 is on, the negative pulse of the DX terminal causes the base voltage Vbulk of the transfer transistor P4 to also pulse negatively. In this way, the gate-to-drain voltage and the gate-to-base voltage of the transfer transistor P4 are maintained at a safe level, even though the DX terminal is suddenly exposed to an IEC level of negative electrostatic charge. As previously mentioned, the IEC level of negative electrostatic charge on terminal DX reduces the voltage of terminal DX to approximately -10 V (although briefly). If the power supply voltage Vdd is 1 V, then in the absence of the ESD trigger circuit 415, the gate-to-drain voltage of the transfer transistor P4 would be 11 V. This relatively large gate-to-drain voltage could damage the transfer transistor P4. However, through the protective action of the ESD trigger circuit 415, the gate voltage will also pulse negatively briefly, such as to approximately -8 V. Therefore, the gate-to-drain voltage of the transfer transistor P4 is only approximately 2 V, which is easily tolerated. Similarly, the conduction of the ESD trigger circuit 415 can negatively pulse the base voltage Vbulk of the transfer transistor P4 to approximately -6 V. The base-to-drain voltage of the transfer transistor P4 in response to the negative electrostatic shock is thus limited to approximately 4 V, which is also tolerated by the transfer transistor P4. Note that the ESD trigger circuit 415 does not load the DX terminal, but instead indirectly detects the pulse of the DX terminal voltage by detecting the resulting pulse of the negative voltage Vneg. In this way, the trigger circuit 415 advantageously does not load the DX terminal with additional capacitance.In contrast, a traditional IEC clamping circuit would load a large amount of capacitance (e.g., dozens of picofarads) onto terminal DX. Thus, it is highly advantageous for the ESD trigger circuit 415 to contribute to providing IEC-level ESD protection without any significant capacitive loading of the DX terminal. In this way, the DX terminal has an appropriately low level of capacitive loading for high-speed data signaling.

[0034] An example circuit implementation 500 of the ESD trigger circuit 415 is shown in Figure 5 . However, it will be understood that many alternative implementations can construct an edge-triggered RC clamping circuit that functions during normal conditions to isolate the power node from the transmission transistor gate and responds to a sudden increase in the power supply voltage by coupling the transmission transistor gate to the power node. The ESD trigger circuit 500 includes a low-pass filter, such as a low-pass RC filter formed by the series combination of resistor R4 and capacitor C4. Resistor R4 has a terminal coupled to the negative voltage node for the negative voltage Vneg. In contrast, capacitor C4 has a terminal coupled to the ground node Vss. Due to the low-pass filtering, the voltage Vfilter at node 505 between resistor R4 and capacitor C4 will be equal to the default (non-electrostatic shock) value of the negative supply voltage. Node 505 is coupled to the gate of NMOS transistor M5, which has a source coupled to the negative voltage node. During normal operation, transistor M5 is thus off. In response to a sudden decrease in the negative voltage Vneg, the gate-to-source voltage of transistor M5 rises, which turns on transistor M5 to discharge its drain voltage. The drain of transistor M5 is coupled to a high-pass filter formed by the series combination of capacitor C5 and resistor R5. The terminal of resistor R5 is coupled to the gate of a PMOS transmission transistor (not illustrated) protected by the ESD trigger circuit 500. The node 510 between resistor R5 and capacitor C5 is coupled to the gate of PMOS transistor P7, which has a source coupled to the gate of the PMOS transmission transistor and a drain coupled to the ground node. Due to the high-pass filtering through capacitor C5 and resistor R5, a sudden decrease in the drain voltage of transistor M5 causes a sudden decrease in the voltage at node 510, which turns on transistor P7. The gate voltage of the PMOS transmission transistor is thus pulsed negatively by the ESD trigger circuit 500.

[0035] Now will be regarding Figure 6The flow chart shown in FIG. discusses the method of operating an ESD circuit. The method includes an action 600 of receiving charge from an electrostatic shock at a terminal of an integrated circuit. The charging of the terminal DP or DN in the integrated circuit 100 or the charging of the terminal DX in the integrated circuit 200 or 400 is an example of the action 600. The method further includes an action 605 of conducting the charge from the terminal through a diode to a voltage node to apply a pulse to the voltage of the voltage node. Conducting through the Dpositive diode in the integrated circuit 200 to apply a positive pulse to the supply voltage Vdd or conducting through the Dnegative diode in the integrated circuit 400 to apply a negative pulse to the negative voltage Vneg is an example of the action 605. The method further includes an action 610 of coupling the voltage node to the gate of a transfer transistor having a drain coupled to the terminal in response to detecting a pulse in the voltage of the voltage node. The coupling through the ESD trigger circuit 300 or through the ESD trigger circuit 500 is an example of the action 610.

[0036] The ESD circuit as disclosed herein can be incorporated into any suitable mobile device or electronic system. For example, as Figure 7 shown, the cellular phone 700, the laptop computer 705, and the tablet PC 710 can all include the ESD circuit according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with the ESD circuit constructed according to the present disclosure.

[0037] The present disclosure will now be outlined in the following series of clauses:

[0038] Clause 1. An electrostatic discharge (ESD) circuit, comprising:

[0039] An integrated circuit terminal;

[0040] A transfer transistor having a drain coupled to the integrated circuit terminal;

[0041] A voltage node;

[0042] A first ESD diode coupled between the integrated circuit terminal and the voltage node; and

[0043] An ESD trigger circuit coupled between the gate of the transfer transistor and the voltage node, the ESD trigger circuit being configured to couple the gate of the transfer transistor to the voltage node in response to an electrostatic shock at the integrated circuit terminal and to isolate the gate of the transfer transistor from the voltage node in the absence of the electrostatic shock at the integrated circuit terminal.

[0044] Clause 2. The electrostatic discharge circuit according to Clause 1, wherein the transfer transistor is an n-type metal oxide semiconductor (NMOS) transfer transistor.

[0045] Clause 3. The electrostatic discharge circuit according to any one of Clauses 1-2, wherein the voltage node is a power supply node for a power supply voltage.

[0046] Clause 4. The electrostatic discharge circuit according to any one of Clauses 1-3, wherein the integrated circuit terminal is a data terminal for a universal serial bus (USB) interface.

[0047] Clause 5. The electrostatic discharge circuit according to Clause 3, further comprising:

[0048] A negative voltage node for a negative voltage; and

[0049] A second ESD diode coupled between the integrated circuit terminal and the negative voltage node.

[0050] Clause 6. The electrostatic discharge circuit according to Clause 5, further comprising:

[0051] A first transistor coupled between the negative voltage node and the gate of the transfer transistor; and

[0052] A controller configured to turn on the first transistor during an audio operation mode to charge the gate of the transfer transistor to a negative supply voltage.

[0053] Clause 7. The electrostatic discharge circuit according to Clause 6, further comprising:

[0054] A second transistor coupled between the negative voltage node and the base of the transfer transistor, wherein the controller is further configured to turn on the second transistor during the audio operation mode.

[0055] Clause 8. The electrostatic discharge circuit according to Clause 3, wherein the ESD trigger circuit includes a first PMOS transistor having a source coupled to the power supply node and a drain coupled to the gate of the transfer transistor.

[0056] Clause 9. The electrostatic discharge circuit according to any one of Clauses 1-9, wherein the ESD trigger circuit further includes a low-pass filter.

[0057] Clause 10. The electrostatic discharge circuit according to Clause 1, wherein the transfer transistor is a PMOS transistor.

[0058] Clause 11. The electrostatic discharge circuit according to Clause 10, wherein the voltage node is a negative voltage node for a negative voltage.

[0059] Clause 12. The electrostatic discharge circuit according to Clause 10 further includes:

[0060] A second ESD diode coupled between the integrated circuit terminal and a power supply node for a power supply voltage.

[0061] Clause 13. The electrostatic discharge circuit according to Clause 12 further includes:

[0062] A first PMOS transistor coupled between the gate of the transfer transistor and the power supply node; and

[0063] A controller configured to turn on the first PMOS transistor during an audio operation mode.

[0064] Clause 14. The electrostatic discharge circuit according to Clause 13 further includes:

[0065] A second PMOS transistor coupled between the base of the transfer transistor and the power supply node, wherein the controller is further configured to turn on the second PMOS transistor during the audio operation mode.

[0066] Clause 15. A method of electrostatic discharge includes:

[0067] Receiving, at a terminal of an integrated circuit, charge from an electrostatic shock;

[0068] Conducting the charge from the terminal to a voltage node through a diode to apply a pulse to a voltage of the voltage node; and

[0069] In response to detecting a pulse in the voltage of the voltage node, coupling the voltage node to a gate of a transfer transistor having a drain coupled to the terminal.

[0070] Clause 16. The method according to Clause 15, wherein receiving the charge at the terminal includes receiving positive charge, and wherein conducting the charge from the terminal to the voltage node through the diode includes conducting the positive charge from the terminal to a power supply voltage node for a power supply voltage.

[0071] Clause 17. The method according to Clause 15, wherein receiving the charge at the terminal includes receiving negative charge, and wherein conducting the charge from the terminal to the voltage node through the diode includes conducting the negative charge from the terminal to a negative voltage node for a negative voltage.

[0072] Clause 18. An electrostatic discharge (ESD) circuit includes:

[0073] An integrated circuit terminal;

[0074] A node for a high-speed data signal;

[0075] A transmission transistor coupled between the node for the high-speed data signal and the integrated circuit terminal; and

[0076] An ESD trigger circuit configured to couple a power supply node for a power supply voltage to the gate of the transmission transistor in response to a positive electrostatic shock to the integrated circuit terminal.

[0077] Clause 19. The electrostatic discharge circuit according to Clause 18 further includes:

[0078] A diode having an anode coupled to the integrated circuit terminal and a cathode coupled to the power supply node.

[0079] Clause 20. The electrostatic discharge circuit according to Clause 18, wherein the integrated circuit terminal is an integrated circuit terminal for an integrated circuit included in a cellular phone.

[0080] Clause 21. The electrostatic discharge circuit according to Clause 18, wherein the transmission transistor is an NMOS transmission transistor.

[0081] Clause 22. An electrostatic discharge (ESD) circuit includes:

[0082] An integrated circuit terminal;

[0083] A node for a high-speed data signal;

[0084] A transmission transistor coupled between the node for the high-speed data signal and the integrated circuit terminal; and

[0085] An ESD trigger circuit configured to couple a negative voltage node for a negative voltage to the gate of the transmission transistor in response to a negative electrostatic shock to the integrated circuit terminal.

[0086] Clause 23. The electrostatic discharge circuit according to Clause 22 further includes:

[0087] A diode having an anode coupled to the negative voltage node and a cathode coupled to the integrated circuit terminal.

[0088] Clause 24. The electrostatic discharge circuit according to Clause 22, wherein the transmission transistor is a PMOS transmission transistor.

[0089] It should be understood that, without departing from the scope of the present disclosure, many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments illustrated and described herein (since they are only by way of some examples), but should be fully commensurate with the scope of the appended claims hereinafter and their functional equivalents.

Claims

1. An electrostatic discharge (ESD) circuit, comprising: An integrated circuit terminal; A transfer transistor having a drain coupled to the integrated circuit terminal; A voltage node; A first ESD diode coupled between the integrated circuit terminal and the voltage node; And An ESD trigger circuit coupled between the gate of the transfer transistor and the voltage node, the ESD trigger circuit being configured to couple the gate of the transfer transistor to the voltage node in response to an electrostatic shock at the integrated circuit terminal and to isolate the gate of the transfer transistor from the voltage node in the absence of the electrostatic shock at the integrated circuit terminal.

2. The electrostatic discharge circuit according to claim 1, wherein the transfer transistor is an n-type metal oxide semiconductor (NMOS) transfer transistor.

3. The electrostatic discharge circuit according to claim 2, wherein the voltage node is a power node for a power supply voltage.

4. The electrostatic discharge circuit according to claim 2, wherein the integrated circuit terminal is a data terminal for a universal serial bus (USB) interface.

5. The electrostatic discharge circuit according to claim 3, further comprising: A negative voltage node for a negative voltage; And A second ESD diode coupled between the integrated circuit terminal and the negative voltage node.

6. The electrostatic discharge circuit according to claim 5, further comprising: A first transistor coupled between the negative voltage node and the gate of the transfer transistor; And A controller configured to turn on the first transistor during an audio operation mode to charge the gate of the transfer transistor to a negative supply voltage.

7. The electrostatic discharge circuit according to claim 6, further comprising: A second transistor coupled between the negative voltage node and the base of the transfer transistor, wherein the controller is further configured to turn on the second transistor during the audio operation mode.

8. The electrostatic discharge circuit according to claim 3, wherein the ESD trigger circuit includes a first PMOS transistor having a source coupled to the power node and a drain coupled to the gate of the transfer transistor.

9. The electrostatic discharge circuit according to claim 3, wherein the ESD trigger circuit further includes a low-pass filter.

10. The electrostatic discharge circuit according to claim 1, wherein the transfer transistor is a PMOS transistor.

11. The electrostatic discharge circuit according to claim 10, wherein the voltage node is a negative voltage node for a negative voltage.

12. The electrostatic discharge circuit according to claim 10, further comprising: A second ESD diode coupled between the integrated circuit terminal and a power node for a power supply voltage.

13. The electrostatic discharge circuit according to claim 12, further comprising: A first PMOS transistor, the first PMOS transistor being coupled between the gate of the transfer transistor and the power supply node; And A controller configured to turn on the first PMOS transistor during an audio operation mode.

14. The electrostatic discharge circuit according to claim 13, further comprising: A second PMOS transistor, the second PMOS transistor being coupled between the base of the transfer transistor and the power supply node, wherein the controller is further configured to turn on the second PMOS transistor during the audio operation mode.

15. A method of electrostatic discharge, comprising: Receiving charge from an electrostatic shock at a terminal of an integrated circuit; Conducting the charge from the terminal to a voltage node through a diode to apply a pulse to the voltage of the voltage node; And In response to detecting a pulse in the voltage of the voltage node, coupling the voltage node to the gate of a transfer transistor having a drain coupled to the terminal.

16. The method according to claim 15, wherein receiving the charge at the terminal comprises receiving a positive charge, and wherein conducting the charge from the terminal to the voltage node through the diode comprises conducting the positive charge from the terminal to a power supply voltage node for a power supply voltage.

17. The method according to claim 15, wherein receiving the charge at the terminal comprises receiving a negative charge, and wherein conducting the charge from the terminal to the voltage node through the diode comprises conducting the negative charge from the terminal to a negative voltage node for a negative voltage.

18. An electrostatic discharge (ESD) circuit, comprising: An integrated circuit terminal; A node for a high-speed data signal; A transfer transistor, the transfer transistor being coupled between the node for the high-speed data signal and the integrated circuit terminal; And An ESD trigger circuit configured to couple a power supply node for a power supply voltage to the gate of the transfer transistor in response to a positive electrostatic shock to the integrated circuit terminal.

19. The electrostatic discharge circuit according to claim 18, further comprising: A diode having an anode coupled to the integrated circuit terminal and a cathode coupled to the power supply node.

20. The electrostatic discharge circuit according to claim 18, wherein the integrated circuit terminal is an integrated circuit terminal for an integrated circuit included in a cellular phone.

21. The electrostatic discharge circuit according to claim 18, wherein the transfer transistor is an NMOS transfer transistor.

22. An electrostatic discharge (ESD) circuit, comprising: An integrated circuit terminal; A node for a high-speed data signal; A transfer transistor, the transfer transistor being coupled between the node for the high-speed data signal and the integrated circuit terminal; And An ESD trigger circuit configured to couple a negative voltage node for a negative voltage to the gate of the transfer transistor in response to a negative electrostatic shock to the integrated circuit terminal.

23. The electrostatic discharge circuit according to claim 22 further comprises: A diode having an anode coupled to the negative voltage node and a cathode coupled to the integrated circuit terminal.

24. The electrostatic discharge circuit according to claim 22, wherein the transfer transistor is a PMOS transfer transistor.

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