Level-based fault detection for row driver of optical sensor

Abstract

The invention relates to level-based fault detection for a row driver of an optical sensor. An exemplary fault detection system may include an input node, a transmission circuit, and a comparison circuit. The input node is electrically connectable to a row driver that generates a row driver voltage on the input node, the row driver voltage having one of a plurality of analog voltage levels. The transmission circuit may be configured to transmit the row driver voltage to a monitoring node shared by a plurality of fault detection systems including the fault detection system when the row driver is selected from a plurality of row drivers. The comparison circuit may be shared by the plurality of fault detection systems and may be configured to generate a digital output by: regulating a voltage from the monitoring node; performing a comparison between the regulated voltage and a reference voltage; and latching the digital output based on the comparison. Corresponding systems, integrated circuits, and methods are also disclosed.

Description

Technical Field

[0001] This specification relates to ways of detecting faults in row driver circuits such as may be implemented within an optical sensor device. Background Art

[0002] Integrated circuits (ICs) can include millions of transistors, capacitors, resistors, and / or other components fabricated on a semiconductor substrate. As the foundation of modern electronics, these complex microelectronic systems can perform complex computations and manipulate information to help drive progress across different fields. One type of IC is an optical sensor IC, which can be configured to convert light energy into electrical signals for sensing and analyzing a visual environment in order to evaluate and / or facilitate interactions with objects in that environment. For example, an optical sensor IC can implement an image sensor, an infrared (IR) sensor, a reflection sensor, a fiber optic sensor, a photoelectric sensor, and / or other suitable types of optical sensor circuits. By capturing the spatial variation of light intensity, an optical sensor IC can convert the complexities of the physical environment into a digital representation. In this way, optical sensor ICs can support applications ranging from smartphone photography to extended reality to autonomous vehicles. The functionality and reliability of ICs, especially optical sensor ICs, often depend on how faults within the IC can be detected immediately and reliably during the manufacturing process and when new faults occur during the in-field operation of the IC. Summary of the Invention

[0003] As described herein, an optical sensor IC can include a plurality of row driver circuits (referred to herein as row drivers) and circuitry for performing level-based fault detection for that row driver. The latter circuitry can be dedicated to a single row driver, shared between two or more row drivers (up to and including shared between all of the row drivers), or a combination of both. The circuitry for performing fault detection for a given row driver is referred to herein as a fault detection system, and it should be understood that multiple such fault detection systems can be integrated into an optical sensor IC to perform level-based fault detection for multiple row drivers. Each such fault detection system can include certain circuitry or circuitry systems dedicated to a particular row driver, as well as other circuitry or circuitry systems shared by two or more row drivers, as described and illustrated in detail herein.

[0004] In an exemplary embodiment, a fault detection system for a row driver of an optical sensor may include an input node, a transmission circuit, and a comparison circuit. The input node may be electrically connected to the row driver, and the row driver may generate a row driver voltage at the input node, the row driver voltage having one of a plurality of analog voltage levels. The transmission circuit may be configured to transmit the row driver voltage to a monitoring node shared by a plurality of fault detection systems including the fault detection system when the row driver is selected from the plurality of row drivers. The comparison circuit may be shared by the plurality of fault detection systems and may be configured to generate a digital output based on the row driver voltage and a reference voltage. For example, the comparison circuit may generate the digital output by: adjusting the voltage from the monitoring node; performing a comparison between the adjusted voltage and the reference voltage; latching the digital output based on the comparison; and / or other such operations described herein.

[0005] A fault detection system for a row driver (such as the exemplary embodiment described above) may include various additional elements, features, characteristics, etc.

[0006] As an example, the row driver may be configured to activate a plurality of transistors one at a time such that the row driver voltage is driven under the following conditions: 1) a first voltage level among the plurality of analog voltage levels when a first PMOS transistor among the plurality of transistors is activated; 2) a second voltage level among the plurality of analog voltage levels when a second PMOS transistor among the plurality of transistors is activated; 3) a third voltage level among the plurality of analog voltage levels when a first NMOS transistor among the plurality of transistors is activated; and 4) a fourth voltage level among the plurality of analog voltage levels when a second NMOS transistor among the plurality of transistors is activated. In this way, the row driver may operate as an analog multiplexer for the plurality of analog voltage levels (including the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level, and any other analog voltage levels that may serve a particular embodiment). In this example, the digital output may include a first output bit determined at a first time when the reference voltage has a first reference level. In this case, the first output bit may indicate whether a defect is detected in the first NMOS transistor or the second NMOS transistor. In this example, the digital output may further include a second output bit determined at a second time when the reference voltage has a second reference level. The second output bit may indicate whether a defect is detected in the first PMOS transistor or the second PMOS transistor. In some embodiments, in this example, the comparison circuit may include a storage circuit configured to store and output the first output bit and the second output bit of the digital output.

[0007] As another example, the transfer circuit may include a first routing transistor and a second routing transistor. These routing transistors may be jointly configured to route the line driver voltage to the monitoring node in the following manner: 1) via a first path through the first routing transistor when the analog voltage level of the line driver voltage is greater than a threshold voltage level; or 2) via a second path through the second routing transistor when the analog voltage level of the line driver voltage is less than the threshold voltage level. In this example, the transfer circuit may further include: a first shielding transistor configured to protect the first routing transistor from voltage levels outside a first operating range of the first routing transistor; and a second shielding transistor configured to protect the second routing transistor from voltage levels outside a second operating range of the second routing transistor.

[0008] As another example, the transfer circuit may include: 1) a first monitor selection transistor that, when activated, connects the monitoring node to a first path and routes the line driver voltage via the first path when the analog voltage level of the line driver voltage is greater than a threshold voltage level; 2) a second monitor selection transistor that, when activated, connects the monitoring node to a second path and routes the line driver voltage via the second path when the analog voltage level of the line driver voltage is less than the threshold voltage level; and 3) a control node that receives a control signal configured to control the activation of the first monitor selection transistor and the second monitor selection transistor. In this example, the control signal may be configured to control the activation of the first monitor selection transistor and the second monitor selection transistor according to a pre-charge phase and an evaluation phase of a period when the line driver is selected from the plurality of line drivers. Similarly, in this example, the control signal may be configured to control the activation of the first monitor selection transistor and the second monitor selection transistor according to a protection period when a different line driver other than the line driver is selected from the plurality of line drivers.

[0009] As another example, the comparison circuit may include: 1) a first capacitor electrically connected to the monitoring node; 2) a second capacitor electrically connected between the first capacitor and ground; 3) an adjusted monitoring node between the first capacitor and the second capacitor; 4) a comparator device connected to the adjusted monitoring node and a reference node for the reference voltage; 5) a first reference control transistor that, when activated, connects a first scaled reference node to the monitoring node; and 6) a second reference control transistor that, when activated, connects a second scaled reference node to the adjusted monitoring node. In this example, the comparison circuit may further include a storage circuit connected to the output of the comparator device and configured to: latch the digital output based on an enable signal; and store and output the digital output.

[0010] In another exemplary embodiment, an optical sensor integrated circuit (IC) may include: a plurality of row drivers including row drivers configured to generate row driver voltages; and a plurality of fault detection systems for the plurality of row drivers. In this embodiment, the plurality of fault detection systems may include a fault detection system for (dedicated to) the row driver; and other fault detection systems dedicated to other row drivers of the plurality of row drivers. The fault detection system may include: 1) an input node electrically connected to the row driver to receive the row driver voltage; 2) a monitoring node shared by the plurality of fault detection systems; 3) a transmission circuit configured to receive the row driver voltage from the input node and transmit the row driver voltage to the monitoring node when the row driver is selected from the plurality of row drivers; and 4) a comparison circuit shared by the plurality of fault detection systems, the comparison circuit being configured to receive the row driver voltage via the monitoring node and generate a digital output based on the row driver voltage and a reference voltage. The digital output may be generated by: adjusting the voltage from the monitoring node; performing a comparison between the adjusted voltage and the reference voltage; latching the digital output based on the comparison; and / or other such operations described herein.

[0011] An optical sensor IC embodiment (such as the above exemplary embodiment) may include a variety of additional elements, features, characteristics, etc.

[0012] As an example, the row driver can be configured to activate multiple transistors one by one, such that the row driver voltage is driven under the following conditions: 1) a first voltage level when a first PMOS transistor among the multiple transistors is activated; 2) a second voltage level when a second PMOS transistor among the multiple transistors is activated; 3) a third voltage level when a first NMOS transistor among the multiple transistors is activated; and 4) a fourth voltage level when a second NMOS transistor among the multiple transistors is activated. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor can all be different transistors among the multiple transistors. In this example, the digital output can include a first output bit determined at a first time when the reference voltage has a first reference level. The first output bit can indicate whether a defect is detected in the first NMOS transistor or the second NMOS transistor. In this example, the digital output can further include a second output bit determined at a second time when the reference voltage has a second reference level. The second output bit can indicate whether a defect is detected in the first PMOS transistor or the second PMOS transistor.

[0013] As another example, the transfer circuit can include a first routing transistor and a second routing transistor, and the first routing transistor and the second routing transistor are jointly configured to route the row driver voltage to the monitoring node. The first transistor and the second transistor can perform the routing in the following manner: 1) via a first path through the first routing transistor when the analog voltage level of the row driver voltage is greater than the threshold level; or 2) via a second path through the second routing transistor when the analog voltage level of the row driver voltage is less than the threshold level.

[0014] As another example, the transfer circuit can include: 1) a first monitor selection transistor, which, when activated, connects the monitoring node to a first path and routes the row driver voltage via the first path when the analog voltage level of the row driver voltage is greater than the threshold level; 2) a second monitor selection transistor, which, when activated, connects the monitoring node to a second path and routes the row driver voltage via the second path when the analog voltage level of the row driver voltage is less than the threshold level; and 3) a control node, on which a control signal is received, and the control signal is configured to control the activation of the first monitor selection transistor and the second monitor selection transistor.

[0015] In another exemplary embodiment, a method for level-based fault detection of a row driver for an optical sensor may include: 1) receiving a row driver voltage at an input node of a fault detection system electrically connected to the row driver among a plurality of row drivers; 2) transmitting the row driver voltage through a transmission circuit within the fault detection system and based on selecting the row driver from the plurality of row drivers to a monitoring node shared by a plurality of fault detection systems including the fault detection system; and 3) generating a digital output by a comparison circuit shared by the plurality of fault detection systems by: adjusting the voltage from the monitoring node; performing a comparison between the adjusted voltage and a reference voltage; and latching the digital output based on the comparison.

[0016] A method for level-based fault detection (such as the exemplary method embodiment described above) may include a variety of additional elements, features, characteristics, etc.

[0017] As an example, as an example, the row driver may be configured to activate a plurality of transistors of the row driver one at a time such that the row driver voltage is driven under the following conditions: 1) a first voltage level when a first PMOS transistor among the plurality of transistors is activated; 2) a second voltage level when a second PMOS transistor among the plurality of transistors is activated; 3) a third voltage level when a first NMOS transistor among the plurality of transistors is activated; and 4) a fourth voltage level when a second NMOS transistor among the plurality of transistors is activated. The first PMOS transistor and the second PMOS transistor and the first NMOS transistor and the second NMOS transistor may all be different transistors among the plurality of transistors. In this example, generating the digital output may include determining a first output bit of the digital output at a first time when the reference voltage has a first reference level. The first output bit may indicate whether a defect is detected in the first NMOS transistor or the second NMOS transistor. In this example, generating the digital output may further include determining a second output bit of the digital output at a second time when the reference voltage has a second reference level. The second output bit may indicate whether a defect is detected in the first PMOS transistor or the second PMOS transistor.

[0018] As another example, in the method, transmitting the row driver voltage to the monitoring node may include routing the row driver voltage in the following manner: 1) via a first path through a first routing transistor within the transmission circuit when an analog voltage level of the row driver voltage is greater than a threshold voltage level; or 2) via a second path through a second routing transistor within the transmission circuit when the analog voltage level of the row driver voltage is less than the threshold voltage level. Additionally, in this example, the method may further include: 1) connecting the monitoring node to the first path through the first monitor selection transistor when the first monitor selection transistor is activated; 2) connecting the monitoring node to the second path through a second monitor selection transistor when the first monitor selection transistor is activated; and 3) controlling the activation of the first monitor selection transistor and the second monitor selection transistor by a control signal received at a control node.

[0019] These and other specific implementation details are set forth in the accompanying drawings and the following description. Other features will also be apparent from the following description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A block diagram of an exemplary image sensor integrated circuit configured to perform level-based fault detection for a plurality of row drivers in accordance with the principles described herein is shown.

[0021] Figure 2 An exemplary method for level-based fault detection of a row driver for an optical sensor in accordance with the principles described herein is shown.

[0022] Figure 3A An exemplary circuit system of an example row driver in accordance with the principles described herein is shown.

[0023] Figure 3B Exemplary aspects of certain operations of a row driver without any defects in accordance with the principles described herein are shown.

[0024] Figure 3C Exemplary aspects of certain operations of a row driver having a defect in an NMOS transistor in accordance with the principles described herein are shown.

[0025] Figure 3D Exemplary aspects of other operations of a row driver without any defects in accordance with the principles described herein are shown.

[0026] Figure 3E Exemplary aspects of other operations of a row driver having a defect in a PMOS transistor in accordance with the principles described herein are shown.

[0027] Figure 3FAn exemplary table showing the fault detection capabilities of an indication non-level-based fault detection method in accordance with the principles described herein.

[0028] Figure 4A An exemplary circuitry of an example level-based fault detection system in accordance with the principles described herein.

[0029] Figure 4B An exemplary timing diagram of an example level-based fault detection system in accordance with the principles described herein.

[0030] Figure 4C An exemplary table showing the fault detection capabilities of an indication level-based fault detection method in accordance with the principles described herein. DETAILED DESCRIPTION

[0031] Systems, circuits, and methods for level-based fault detection of a row driver for an optical sensor are described herein. For any integrated circuit (IC) that includes an optical sensor IC, the electronic components within the IC are prone to faults both during manufacture at the manufacturing stage and later in the life cycle of the IC. For example, transistors or other electronic components may be manufactured with various faults or defects, or may develop various faults or defects after a certain time, including open-circuit defects (whereby the component loses the ability to conduct current properly), short-circuit defects (whereby the component loses the ability to properly block or resist current), gate defects (whereby the component loses the ability to control properly), and so on.

[0032] Depending on the application or use case of a particular IC, a certain level of integrity may be desired or required to ensure a certain level of reliability associated with the working IC. For example, for an IC used in a cheap electronic device, the desired or required level of integrity for the IC may not be particularly stringent. On the other hand, for an IC used in a more complex and / or high-risk application, such as in the decision-making chain of an autonomous vehicle, the desired or required level of integrity for the IC may be much higher in terms of meeting safety goals and ensuring the proper operation of other devices. In any of these or other situations, various manufacturing tests and operational tests can be applied to the various circuits as well as functional blocks and components within the IC to ensure that the desired or required level of integrity is met and maintained. As described and illustrated in detail herein, level-based fault detection for a row driver of an optical sensor is a type of integrity test that can be built into the IC and applied throughout the life cycle of the IC to provide a high level of test coverage for the components of the row driver within the optical sensor and to ensure that these row drivers meet and maintain any level of integrity that may be desired or required for a given IC application.

[0033] Some optical sensors can be constructed in a grid having row circuitry and column circuitry, where the row circuitry and column circuitry are configured to detect light passing through a pixel array on the sensor. The row circuitry in such optical sensors can be responsible for a variety of tasks, such as proper decoding of row addresses, checking the proper voltage level of a low dropout (LDO) regulator, verifying the integrity of pixel control signals passing through the pixel array, and so on. The proper operation of such circuitry can be continuously monitored throughout the life cycle of the optical sensor IC, but doing so requires additional fault detection circuitry that can consume a significant amount of the limited substrate footprint, can use a significant amount of the IC's power budget, can increase manufacturing complexity, and so on. Additionally, as will be shown and described in more detail below, traditional fault detection circuitry may be only very suitable for detecting certain types of faults, while other faults may be masked or otherwise evade detection.

[0034] To address these challenges, the level-based fault detection described herein is configured to provide significantly greater test coverage than traditional methods, while being more highly efficient in terms of area usage, power usage, manufacturing complexity, and so on. For example, the benefits provided by the level-based fault detection systems and methods described herein can include, but are not limited to: 1) helping to achieve 100% defect detection of the row driver circuitry in order to meet high integrity level requirements and ensure the safe and proper operation of the optical sensor throughout its life cycle; 2) implementing certain functions using circuitry dedicated to a single row driver while implementing other functions using shared circuitry that is multiplexed to serve many row drivers; 3) optimizing area usage by using relatively small transistors integrated in the sensor adjacent to the row driver; 4) sharing comparators, scaling, level shifting, and other functions between multiple rows or all rows compared to using dedicated circuitry for each row to minimize the area and power usage of these functions; 5) minimizing routing and manufacturing complexity by implementing defect testing on the chip near the row circuitry to avoid additional routing and / or excessive pins for passing signals between dies in a stacked die configuration; and / or 6) allowing for efficient and convenient scaling of the defect coverage by sharing critical components between rows and placing them near the row circuitry they serve.

[0035] Various specific implementations will now be described in more detail with reference to the accompanying drawings. It should be understood that the specific specific implementations described below are provided as non-limiting examples and can be applied to various situations. Additionally, it should be understood that other specific implementations not explicitly described herein may also fall within the scope of the claims set forth below. The optical sensor IC and related methods for level-based fault detection for the row drivers of an optical sensor IC can produce any one or all of the above-described technical benefits, as well as various additional technical benefits that will be described and / or made apparent below.

[0036] Figure 1 A block diagram of an exemplary optical sensor integrated circuit (IC) 100 configured to perform level-based fault detection for a plurality of row drivers in accordance with the principles described herein is shown. As will be described and presented below, an optical sensor IC such as optical sensor IC 100 can be implemented in a variety of ways and has a variety of optional features that can be used in any combination, as may serve a particular specific implementation. Thus, Figure 1 The block diagram of optical sensor IC 100 in [the figure] is presented as a schematic representation of certain features common to many or all of the optical sensor IC specific implementations described herein, and various additional specific implementations with different specific features and combinations of features will be described and shown using the same or related reference numerals as introduced in Figure 1 [the figure].

[0037] As Figure 1 shown, optical sensor IC 100 includes a plurality of row drivers 102, which includes row driver 102-1 (at the front of the stack) and various other row drivers 102 (drawn behind row driver 102-1 and not individually labeled in Figure 1 [the figure]). Similarly, a plurality of fault detection systems 104 for the plurality of row drivers 102 are shown, each outlined in dashed lines. The plurality of fault detection systems 104 are shown to include a fault detection system 104-1 corresponding to row driver 102-1 (at the front of the stack), and other fault detection systems 104 (drawn behind fault detection system 104-1 and not individually labeled in Figure 1 [the figure]). As Figure 1Further shown, a plurality of transmission circuits 106 dedicated to a single row driver 102 are each electrically coupled to a comparison circuit 108 shared by all the transmission circuits 106 and their corresponding row drivers 102. More specifically, as shown, each fault detection system 104 includes a dedicated transmission circuit 106 while sharing access to a single comparison circuit 108 shared by all rows. For example, fault detection system 104-1 is shown to include transmission circuit 106-1 (at the front of the stack), and it should be understood that this transmission circuit is dedicated to being used by row driver 102-1 and belongs only to fault detection system 104-1. However, fault detection system 104-1 is also shown to include comparison circuit 108. It should be understood that this indicates shared use with other fault detection systems 104 that also include (share) this same comparison circuit.

[0038] Optical sensor IC 100 is shown in Figure 1 to include the shared use of a corresponding plurality of row drivers 102 and fault detection systems 104 and their dedicated transmission circuits 106 and comparison circuits 108. However, for clarity, convenience of description, and illustration, the following description will focus particularly on row driver 102-1 and fault detection system 104-1.

[0039] As shown, row driver 102-1 receives a level selection input 110 and generates a row driver voltage at node 112. The output terminal (node 112) of row driver 102-1 is shown as the input terminal dedicated to row driver 102-1 of fault detection system 104-1. Thus, node 112 is also referred to herein as input node 112. As shown, input node 112 can electrically connect row driver 102-1 to the transmission circuit 106-1 of fault detection system 104-1 to allow the transmission circuit to receive the row driver voltage. As will be described and shown in more detail below, the row driver voltage generated by row driver 102-1 at input node 112 can have one of a plurality of analog voltage levels based on the digital value of level selection input 110.

[0040] When row driver 102-1 is selected from among the plurality of row drivers 102 (such as for pixel readout or other operations where each row is selected in sequence for execution in turn), transmission circuit 106-1 can be configured to transmit the row driver voltage to a monitoring node 114 shared by transmission circuit 106-1 and the other plurality of transmission circuits 106, as shown. Thus, monitoring node 114 can be referred to herein as a shared monitoring node. Monitoring node 114 is shown to electrically connect the plurality of transmission circuits 106 to a comparison circuit 108, which is also shared by all the plurality of fault detection systems 104 and can be referred to herein as a shared comparison circuit.

[0041] Comparator circuit 108 may be configured to generate a digital output 116. For example, as will be described in more detail below, comparator circuit 108 may generate digital output 116 by performing operations that include, for example: 1) conditioning a voltage from shared monitoring node 114; 2) performing a comparison between the conditioned voltage and a reference voltage; 3) latching digital output 116 based on the comparison; and / or other operations described herein or that may serve a particular implementation.

[0042] Figure 2 An exemplary method 200 for level-based fault detection of a row driver for an optical sensor in accordance with the principles described herein is shown. Although Figure 2 exemplary operations 202-206 and sub-operations 208-212 in accordance with one implementation are shown, other implementations of method 200 may omit, add to, re-order, and / or modify Figure 2 any of the operations 202-206 and / or sub-operations 208-212 shown. In some examples, Figure 2 the operations shown or described with respect to Figure 2 may be performed simultaneously (e.g., in parallel) with each other rather than sequentially as shown and / or described. Each of operations 202-206 and sub-operations 208-212 will now be described in more detail as they may be performed by an implementation of optical sensor IC 100, or more specifically, by an implementation of one of the fault detection systems in fault detection system 104, such as fault detection system 104-1.

[0043] At operation 202, fault detection system 104-1 may receive a row driver voltage at an input node of the fault detection system that is electrically connected to a row driver among a plurality of row drivers. For example, the input node may be Figure 1The input node 112 shown. The row driver voltage can have one of a plurality of analog voltage levels. More specifically, as will be described and shown in more detail below, the row driver can be configured to operate as an analog multiplexer for the plurality of analog voltage levels by activating one of a plurality of transistors within the row driver at a time. For example, the row driver voltage can be driven under any of the following conditions: 1) the first voltage level among the plurality of analog voltage levels when the first PMOS transistor among the plurality of transistors is activated; 2) the second voltage level among the plurality of analog voltage levels when the second PMOS transistor among the plurality of transistors is activated; 3) the third voltage level among the plurality of analog voltage levels when the first NMOS transistor among the plurality of transistors is activated; 4) the fourth voltage level among the plurality of analog voltage levels when the second NMOS transistor among the plurality of transistors is activated; or 5) another suitable analog voltage level associated with another one of the plurality of transistors.

[0044] At operation 204, the fault detection system 104-1 can use a transmission circuit such as the transmission circuit 106-1 to transmit the row driver voltage from the input node to a monitoring node such as the monitoring node 114 shared by a plurality of fault detection systems 104 including the fault detection system 104-1. The transmission of the row driver voltage by the transmission circuit can be performed based on selecting a row driver from among the plurality of row drivers. For example, since the monitoring node 114 can be shared by many fault detection systems (one for each row in the pixel rows on the optical sensor IC), the controller can keep track of when it is the turn of the fault detection system 104-1 to drive the monitoring node and when it is the turn of the fault detection system 104 instead of the fault detection system 104-1. When it is the turn, the fault detection system 104-1 can be selected as the circuit that is assigned to use and control the shared monitoring node and the shared comparison circuit. At this time, the transmission circuit can instruct the row driver voltage to be driven onto the shared monitoring node in a manner that takes into account the operating ranges of the various components to avoid imposing inappropriate stress on these components, as will be described in more detail below. At other times, when it is not the turn of the fault detection system 104-1 and the fault detection system is not selected, the transmission circuit can be configured to isolate the row driver voltage from the node when it is the turn of other fault detection systems 104 to use the shared monitoring node.

[0045] At operation 206, the fault detection system 104-1 can use a comparison circuit such as the comparison circuit 108 to generate a digital output. As Figure 1As shown in the example of comparator circuit 108, the comparator circuit used at operation 206 can be shared by multiple fault detection systems 104. For example, similar to what was described above for the shared monitoring nodes, the use of the comparator circuit can be arbitrated by a selection mechanism that manages the fault detection systems taking turns using the comparator circuit, or in other words, selects and grants each fault detection system access to and use of the corresponding time periods of these shared resources. When fault detection system 104-1 is selected in this manner, a digital output can be generated by the comparator circuit in any suitable manner. For example, operation 206 is shown as including three sub-operations 208, 210, and 212 that can be performed as part of operation 206.

[0046] For sub-operation 208, the comparator circuit can adjust the voltage from the monitoring node. For example, the adjustment can include shifting the voltage level to a level suitable for the operating range of a comparator device that will be used to analyze the voltage level at sub-operation 210. Additionally, the adjustment at sub-operation 208 can include scaling the voltage to prepare it for comparison with a specific reference level. As will be described and shown in more detail below, this voltage adjustment can involve a capacitor network that uses one or more reference voltages to pre-charge to produce an adjusted voltage, and the adjusted voltage is appropriately level-shifted and scaled to represent the voltage level of the row driver voltage for sub-operation 210.

[0047] At sub-operation 210, the comparator circuit can perform a comparison between the adjusted voltage generated at sub-operation 208 and a reference voltage. For example, the reference voltage can be selected such that when compared with the adjusted voltage, any faults or defects present in the row driver will be detected based on the unexpected voltage level of the adjusted voltage. As will be described and shown in more detail below, for example, one reference voltage can be selected to detect whether any faults or defects are present in the NMOS transistors of the row driver, while a different reference voltage can be selected to detect whether any faults or defects are present in any of the PMOS transistors of the row driver. This comparison can be performed by a comparator component that receives the adjusted voltage and an appropriate reference voltage (depending on which transistors are currently being tested) as inputs, and then outputs a voltage that indicates whether the comparison was as expected (such that no defect was detected) or not as expected (such that a defect was detected).

[0048] For sub-operation 212, the comparison circuit may latch a digital output based on the comparison. For example, since the same comparison circuit may perform at least two tests for each row (a test for the PMOS transistor and a test for the NMOS transistor, as described above and as described in more detail below), the test results may be recorded and stored by latching the respective voltages output by the comparator component for each test. Thus, the digital output may include two bits representing the test results for a given row, which may subsequently be fed into other circuits, storage facilities, etc. Ultimately, the digital output latched at sub-operation 212 may be used to allow the information obtained by the pixels on the row served by row driver 102-1 to be relied upon to the extent that the row driver has been verified to operate reliably and without defects.

[0049] Figure 3A An illustrative circuit system of an example row driver in accordance with the principles described herein is shown. More specifically, as shown, a specific implementation of row driver 102-1 is shown in Figure 3A to receive a level select input 110 and output a row driver voltage at node 112. As described above, it should be understood that node 112 will serve as the output node of row driver 102-1, although it is elsewhere referred to as input node 112 because this output is an input to the fault detection system (fault detection system 104-1 in this example).

[0050] Row driver 102-1 may be configured to act as an analog multiplexer that converts various digital values into analog voltages with different corresponding voltage levels. For example, if a pixel row is configured to perform actions such as capturing light information, reading out the captured information, clearing the pixels to prepare for a subsequent image, transmitting or partially transmitting data, etc., the row driver for that pixel row may be configured to provide a signal with a row driver voltage having a specific analog voltage value to indicate which of these functions will be performed at a given time. In one specific implementation, for example, the row driver may be configured to generate a row driver voltage having up to eight different analog values, which eight different analog values correspond to eight different functions of the pixels driven on that row. Thus, the function of a row driver such as row driver 102-1 may be to receive a digital input signal that may have a certain number of possible digital values and generate an analog signal having a voltage level corresponding to the current digital value on the input line.

[0051] To this end, an example of the row driver 102-1 shows that the level selection input 110 can be a 3-bit digital input capable of representing up to eight different digital values. An example 3-bit value of the signal is shown by the example waveform in the dashed circle drawn below the level selection input 110, and the decoder 302 receiving the level selection input 110 is shown with a table showing the voltage ranges to be output for various possible digital input values. Specifically, as shown on the decoder 302 of this example, a row driver voltage with a value between 2V and 4V can be output at the node 112 for the digital value 0b000 ("0") or the digital value 0b001 ("1") on the level selection input 110; a row driver voltage with a value between -1V and 1V can be output at the node 112 for the digital value 0b010 ("2") or the digital value 0b011 ("3") on the level selection input 110; a row driver voltage with a value between -1V and 2V can be output at the node 112 for the digital value 0b100 ("4") or the digital value 0b101 ("5") on the level selection input 110; and a row driver voltage with a value of 0V (ground) can be output at the node 112 for the digital value 0b110 ("6") or the digital value 0b111 ("7") on the level selection input 110.

[0052] In some specific implementations, the row driver 102-1 can be configured to provide the same analog voltage level for the row driver voltage for two or more different digital values. For example, the row driver 102-1 can be configured such that the level selection input values of 0b000 ("0") or 0b001 ("1") produce the same row driver voltage output of 3V. In other specific implementations, the row driver 102-1 can be configured to provide different analog voltage levels for the row driver voltage for different digital values. For example, the row driver 102-1 can be configured such that the level selection input value 0b000 ("0") produces a row driver voltage of 3V, while the level selection input value 0b001 ("1") produces a row driver voltage output of 4V.

[0053] An example waveform attached to node 112 may correspond to the example values shown in the waveform attached to the level select input 110. Thus, these waveforms together show that the analog voltage values of the row driver voltage driven onto node 112 can reflect a relatively wide voltage range, such as from -1V to 4V in this example. This voltage range may be wider than the operating range of any particular device used to drive or process voltages (e.g., any single PMOS or NMOS transistor). However, by combining complementary PMOS and NMOS transistors powered at different voltage levels, a wide range of voltage values required for node 112 can be achieved. Thus, in this example, row driver 102-1 is configured to operate as an analog multiplexer for multiple analog voltage levels (such as those shown in the waveform of node 112 and / or as indicated in the table of decoder 302) by activating one of the multiple transistors included in row driver 102-1 at a time. In this particular implementation, Figure 3A it is shown that the multiple transistors include two PMOS transistors 304-0 and 304-1 (collectively referred to as PMOS transistors 304) and six NMOS transistors 306-2, 306-3, 306-4, 306-5, 306-6, and 306-7 (collectively referred to as NMOS transistors 306), for a total of eight transistors corresponding to eight possible digital values of the level select input 110.

[0054] By activating only one of these eight transistors at a time based on the level select input 110, decoder 302 can effectively select or multiplex the voltages supplied to each of these transistors that will be driven onto node 112. As a specific example based on Figure 3A the values shown, the row driver voltage at node 112 can be driven under the following conditions: a first voltage level (such as 4V) when PMOS transistor 304-0 is activated; a second voltage level (such as 3V) when PMOS transistor 304-1 is activated; a third voltage level (such as 1V) when NMOS transistor 306-2 is activated; a fourth voltage level (such as -1V) when NMOS transistor 306-3 is activated; a fifth voltage level (such as 2V) when NMOS transistor 306-4 or 306-5 is activated; and a sixth voltage level (such as 0V) when either of NMOS transistors 306-6 or 306-7 is activated. It should be understood that these voltage levels are provided only as examples, and any suitable voltage levels can be associated with each digital input value, as may serve a particular implementation.

[0055] Additional components other than decoder 302 and the plurality of transistors 304 and 306 may also be included in the row driver implementation, such as may serve a particular implementation. For example, certain circuit elements may serve various functions to facilitate, support, or enable the primary functions of the row driver circuits already described. For example, as Figure 3A shown, row driver 102-1 may include a level shifter 308 configured to level shift the voltage output by decoder 302 to an appropriate voltage level to activate the PMOS transistor when applied to the gate of PMOS transistor 304. For this exemplary implementation, it will be assumed that no similar level shifting is required to activate NMOS transistor 306, although this may not necessarily be the case in other implementations. Additionally, shielding transistors 310-1 and 310-2 are shown to be included between node 112 and the multiple different sets of PMOS transistors 304 and NMOS transistors 306. Like the other shielding transistors described herein, shielding transistors 310-1 and 310-2 may be used to ensure that no component of row driver 102-1 is stressed by voltages outside of its operating range.

[0056] When appropriately configured in the manner already described, only one of transistors 304 or 306 is activated at a time (based on the input value of level select input 110), and thereby the row driver voltage having the desired analog voltage level is driven onto node 112. However, if one or more of transistors 304 or 306 is faulty or defective, the analog voltage level of the row driver voltage on node 112 may be incorrect due to problems that occur during the manufacturing process or problems that occur in the field after manufacturing. For illustration, Figures 3B to 3E desired and defective results for two example cases are shown, one example case where one of the NMOS transistors in NMOS transistor 306 is a defective transistor and another example case where one of the PMOS transistors in PMOS transistor 304 is a defective transistor. More specifically, Figure 3B shows the sequence of exemplary operations performed by row driver 102-1 when there are no defects, while Figure 3C shows the same operations performed by row driver 102-1 when there is a defect (such as one of the NMOS transistors in NMOS transistor 306 being shorted). Then, Figure 3D shows a new sequence of exemplary operations performed by row driver 102-1 when there are no defects, and Figure 3E shows the same operations performed by row driver 102-1 when there is a defect (such as one of the PMOS transistors in PMOS transistor 304 being shorted).

[0057] In Figures 3B to 3EIn each of them, multiple transistors 304 and 306 are shown as including respective defect indicators 320 to indicate whether the transistors in a particular example are operating properly or are associated with a fault or defect. Specifically, for a given example, a checkmark next to a transistor should be understood to indicate that no defect has impaired that particular transistor, while an "X" mark next to a transistor for that example should be understood to indicate that a short-circuit defect has impaired that transistor. To distinguish different defect indicators in different figures, letters in the figures are used in combination with the reference numerals of the defect indicators 320. That is, the defect indicator 320-B shows the specific state of the transistors in the example of Figure 3B ; the defect indicator 320-C shows the specific state of the transistors in the example of Figure 3C ; the defect indicator 320-D shows the specific state of the transistors in the example of Figure 3D ; and the defect indicator 320-E shows the specific state of the transistors in the example of Figure 3E .

[0058] The sequence of level selection input values on the level selection input 110, together with the row driver voltages driven onto the node 112 to indicate these values, is indicated in the waveforms below the row driver 102-1 in each of Figures 3B to 3E . In Figure 3B and Figure 3C 's example, the sequence goes from 0b010 ("2") to 0b011 ("3") to 0b001 ("1") to 0b000 ("0") and back to 0b010 ("2"). As indicated by the parentheses on the waveforms for each of these numerical values, the decoder 302 activates a particular transistor 304 or 306 for each of these numerical values. For example, the numerical value 0b010 ("2") activates the NMOS transistor 306-2, and the numerical value 0b000 ("0") activates the PMOS transistor 304-0, and so on. Based on the regulated voltage or ground voltage supplied to these various transistors (not explicitly shown), an analog voltage level 322 corresponding to that transistor is applied to the row driver voltage at the node 112, as shown in the waveform below the sequence of level selection input 110 values ("row driver voltage at node 112").

[0059] In Figure 3BIn [diagram], the defect indicator 320-B shows that the PMOS transistor 304 and all NMOS transistors 306 have no defects and are fully functional. Thus, the waveform shows that the analog voltage level 322-2B corresponds to the selection of 0b010 ("2") on the input; the analog voltage level 322-3B corresponds to the selection of 0b011 ("3") on the input; the analog voltage level 322-1B corresponds to the selection of 0b001 ("1") on the input; the analog voltage level 322-0B corresponds to the selection of 0b000 ("0") on the input; and the same analog voltage level 322-2B again corresponds to the selection of 0b010 ("2") on the input at the end of the shown sequence. This should be understood to represent the required and defect-free operation of the row driver 102-1 for this input sequence.

[0060] In contrast, Figure 3C the same input sequence is used to show the results when one of the NMOS transistors 306 has a defect. Specifically, in Figure 3C [diagram], the defect indicator 320-C shows that, while the PMOS transistor 304 and all NMOS transistors 306-3 to 306-7 have no defects and are fully functional, the NMOS transistor 306-2 includes a defect. More specifically, the defect in the NMOS transistor 306-2 should be understood as a short circuit defect that impairs the transistor's ability to resist current flow when the transistor is inactive. It should be understood that the short circuit in the NMOS transistor 306-2 can be a relatively weak short circuit (such as 100 ohms) or a relatively strong short circuit (such as 2 ohms). In either case, the defect may impair the normal function of the row driver 102-1 circuit, as shown by the difference between the actual analog voltage level 322 (shown by the solid line) and the required analog voltage level 322 (shown by the dashed line for reference) presented at node 112.

[0061] In this example, as shown in the figure, the analog voltage level 322-2C corresponds to the selection of 0b010 ("2") on the input; the analog voltage level 322-3C corresponds to the selection of 0b011 ("3") on the input; the analog voltage level 322-1C corresponds to the selection of 0b001 ("1") on the input; the analog voltage level 322-0C corresponds to the selection of 0b000 ("0") on the input; and the same analog voltage level 322-2C again corresponds to the selection of 0b010 ("2") on the input at the end of the shown sequence. When 0b010 ("2") is selected, the short circuit defect on the NMOS transistor 306-2 does not cause a problem, and the solid line and the dashed line are shown to be the same. However, when any other value is selected, the short circuit defect effectively creates a resistive divider circuit that impairs the row driver voltage level, as Figure 3Cas indicated by the difference between the solid and dashed waveforms therein. This should be understood as representing an undesirable operation of the row driver 102-1 for this input sequence caused by a defect in the NMOS transistor 306-2.

[0062] Figure 3D and Figure 3E provide a similar example, but for the case where a defect occurs in one of the PMOS transistors in the PMOS transistor 304 rather than one of the NMOS transistors. In Figure 3D and Figure 3E 's example, the sequence goes from 0b000 ("0") to 0b001 ("1") to 0b011 ("3") to 0b010 ("2") back to 0b000 ("0"). Similarly, the specific transistors 304 or 306 activated by the decoder 302 for each of these digital values are shown in parentheses on the waveform in conjunction with the corresponding digital values. For example, the digital value 0b000 ("0") causes the PMOS transistor 304-0 to be activated, the digital value 0b001 ("1") causes the PMOS transistor 304-1 to be activated, and so on. Similarly, based on the regulated voltage or ground voltage supplied to these various transistors (not explicitly shown), the analog voltage level 322 corresponding to the transistor is applied to the row driver voltage at node 112, as shown in the waveform below the sequence of level select input 110 values ("row driver voltage at node 112").

[0063] In Figure 3D , the defect indicator 320-D shows that the PMOS transistor 304 and all NMOS transistors 306 have no defects and are fully functional. Thus, the waveform shows that the analog voltage level 322-0D corresponds to the selection of 0b000 ("0") on the input; the analog voltage level 322-1D corresponds to the selection of 0b001 ("1") on the input; the analog voltage level 322-3D corresponds to the selection of 0b011 ("3") on the input; the analog voltage level 322-2D corresponds to the selection of 0b010 ("2") on the input; and the same analog voltage level 322-0D again corresponds to the selection of 0b000 ("0") on the input at the end of the shown sequence. This should be understood as representing the desired and defect-free operation of the row driver 102-1 for this input sequence.

[0064] In contrast, Figure 3E the same input sequence is used to show the results when there is a defect in one of the NMOS transistors in the PMOS transistor 304. Specifically, in Figure 3EIn this case, the defect indicator 320-E shows that, although the PMOS transistor 304-1 and all NMOS transistors 306 have no defects and are fully functional, the PMOS transistor 304-0 includes a defect. More specifically, the defect in the PMOS transistor 304-0 should be understood as a short-circuit defect that impairs the transistor's ability to resist current flow when the transistor is not activated. It should be understood that the short circuit in the PMOS transistor 304-0 can be a relatively weak short circuit (such as 100 ohms) or a relatively strong short circuit (such as 2 ohms). In either case, the defect may impair the normal function of the row driver 102-1 circuit, as indicated by the difference between the actual analog voltage level 322 (also shown by the solid line) and the desired analog voltage level 322 (also shown by the dashed line for reference) presented at node 112.

[0065] In this example, as shown, the analog voltage level 322-0E corresponds to the selection of 0b000 ("0") on the input; the analog voltage level 322-1E corresponds to the selection of 0b001 ("1") on the input; the analog voltage level 322-3E corresponds to the selection of 0b011 ("3") on the input; the analog voltage level 322-2E corresponds to the selection of 0b010 ("2") on the input; and the same analog voltage level 322-0E again corresponds to the selection of 0b000 ("0") on the input at the end of the shown sequence. In this example, when 0b000 ("0") is selected, the short-circuit defect on the PMOS transistor 304-0 does not cause a problem, and the solid line and the dashed line are shown as the same. However, when any other value is selected, the short-circuit defect effectively creates a resistor divider circuit that impairs the row driver voltage level, as Figure 3E shown by the difference between the solid line waveform and the dashed line waveform in. This should be understood to represent the undesirable operation of the row driver 102-1 for this input sequence caused by the defect in the PMOS transistor 304-0.

[0066] To detect faults or defects in the row driver, such as Figure 3C and Figure 3EFor those defects shown in row driver 102-1, one type of fault detection mechanism that has been used is a sample-and-hold mechanism that precharges a node to a known voltage and monitors the voltage swing on that node. For this traditional non-level-based fault detection, a change or trigger from a reference voltage has been used to indicate normal operation of the row driver, and the absence of such a change has been interpreted as indicating the presence of a fault. This traditional method can be relatively effective for detecting certain types of faults and defects, such as an open-circuit defect in which one of the row driver transistors in the row driver does not conduct current when activated. Unfortunately, other types of defects, such as short-circuit defects and gate defects, may tend to evade this type of fault detection. For example, the relative strength of a given short circuit (from a strong short-circuit defect of only a few ohms to a weak short-circuit defect of hundreds of ohms) can determine the extent to which the analog voltage level of the row driver voltage at node 112 is impaired. In many cases, the effective resistor divider created by a short-circuit defect in an unselected transistor can have an adverse effect on the analog voltage level, as shown by the difference between the solid line and the dashed line in Figure 3C and Figure 3E . However, if the row driver voltage is still large enough to activate the transistor in the sample-and-hold fault detection mechanism, this short-circuit defect may be masked and not detected in the same way as an open-circuit defect. In other words, simply checking for the expected voltage swing switching (in a non-level-based method) rather than verifying the actual voltage level (in a level-based method) may not be sufficient to detect certain faults and defects that may be present in a given row driver circuit.

[0067] To illustrate the deficiencies of this traditional non-level-based fault detection mechanism, Figure 3FIllustrative Table 330 showing the fault detection capabilities of a non-level-based fault detection method such as the above is presented. In Table 330, the leftmost column ("Transistor / Defect") indicates the reference numerals of the row driver transistors that may have a particular type of defect in a certain example. Each of PMOS transistor 304, NMOS transistor 306, and shield transistor 310 is represented in this column (a total of ten transistors). In the other three columns of this table, different types of defects are indicated: 1) will be "undetected" by the non-level-based fault detection mechanism; 2) will be "detected" by the non-level-based fault detection mechanism; or 3) will provide a "safe fault" (in the case of shield transistor 310). As shown in the first defect column ("Gate Open"), when there is a gate defect on either PMOS transistor 304 or NMOS transistor 306, this gate defect will not be detected by the non-level-based fault detection mechanism described above. Similarly, as shown in the rightmost column ("S-D Short"), when there is a short circuit defect from source to drain on either PMOS transistor 304 or NMOS transistor 306, this short circuit defect will also not be detected by this type of fault detection mechanism. As shown in the middle defect column ("S-D Open"), the only defects that can be detected by the non-level-based fault detection mechanism described above are those open circuit defects from source to drain of PMOS transistor 304 and NMOS transistor 306. Additionally, shield transistors 310 are shown to successfully perform their function of providing a safe fault to other transistors in the event of a defect.

[0068] Summary Table 332 below Table 330 summarizes the performance of this type of fault detection method. For a total of 30 faults shown in Table 330, only 10 of them are positively detected (when there is an open circuit defect from source to drain), and 4 safe faults are provided. The other 16 defects are shown to fall into the undetected fault category, resulting in a total detection coverage of 46.7% in this example. Although such a fault detection method may be valuable (since it may help detect certain faults and defects at least some of the time), a more reliable and consistent fault detection method may be needed, especially for higher-risk optical sensor applications, and especially when such a method can be implemented with minimal or no trade-off in terms of area usage, power usage, etc. Therefore, an example of a level-based fault detection system characterized by these and other advantageous features will now be shown and described.

[0069] Figure 4AIllustrates an exemplary circuit system of an exemplary embodiment of a fault detection system 104-1 in accordance with the principles described herein. The fault detection system 104-1 represents a level-based fault detection system that is configured to improve the drawbacks of the above-described non-level-based fault detection mechanism, which detects faults based on the switching (or lack of switching) of voltage rather than on its voltage level. As shown, this embodiment of the fault detection system 104-1 includes a transmission circuit 106-1 that is dedicated to a particular row (such as the row served by row driver 102-1) and receives the row driver voltage at input node 112, which is the output of row driver 102-1 (as described above). As described above, the transmission circuit 106-1, along with various other transmission circuits associated with other rows, is connected to a shared comparison circuit 108 at monitoring node 114. As described above, the comparison circuit 108 generates a digital output 116 for use by other systems, circuits, and processes that are outside the scope of this specification. The embodiments of each of these elements will now be described in more detail in conjunction with additional components, nodes, signals, voltages, etc. that assist these circuits in performing the described functions.

[0070] Within transmission circuit 106-1, routing transistors 402-1 and 402-2 (collectively referred to as routing transistors 402) are each connected to input node 112 to provide two possible paths for the current on input node 112. As shown, routing transistor 402-1 may be implemented by a PMOS transistor that is controlled by the voltage on routing control node 404-1 connected to the gate of the transistor. Then, in this example, routing transistor 402-2 is shown as being implemented by an NMOS transistor that is controlled by the voltage on routing control node 404-2 connected to its gate. As described above, in one specific implementation, the analog voltage level of the row driver voltage on node 112 may vary within a relatively wide range (such as a range from -1V to 4V). Since this may be wider than the operating range of a single PMOS or NMOS transistor within this image sensor IC, both transistors 402 may be included in transmission circuit 106-1 to help regulate and route the row driver voltage regardless of its voltage level. For example, when the row is selected for a read operation and one of the PMOS transistors 304 in row driver 102-1 is activated (such that the row driver voltage at node 112 has a relatively high voltage level), the voltage on routing control node 404-1 may be driven to activate routing transistor 402-1, while the voltage on routing control node 404-2 may be driven such that routing transistor 402-2 is not activated. Conversely, when the row is selected for a read operation and one of the NMOS transistors 306 in row driver 102-1 is activated (such that the row driver voltage at node 112 has a relatively low voltage level), the voltage on routing control node 404-1 may be driven to deactivate routing transistor 402-1, while the voltage on routing control node 404-2 activates routing transistor 402-2.

[0071] In some specific implementations, the voltages on the routing control nodes 404-1 and 404-2 can be controlled by the same mechanism that drives the gates of the PMOS transistor 304 and the NMOS transistor 306. For example, the voltage can be controlled by the decoder 302 and / or other related circuitry. In this case, when any one of the PMOS transistors 304 is selected, the same signal that drives the gate of one of the PMOS transistors in the PMOS transistor 304 can also be used to activate the routing transistor 402-1 at the routing control node 404-1. Similarly, when any one of the NMOS transistors 306 is selected, the same signal that drives the gate of one of the NMOS transistors in the NMOS transistor 306 can also be used to activate the routing transistor 402-2 at the routing control node 404-2. In other specific implementations, independent dedicated signaling can be used to drive the routing control nodes 404-1 and 404-2 to control the routing transistors 402-1 and 402-2 independently of the row driver.

[0072] In this way, when the row is selected, the transmission circuit 106-1 can be configured to route the row driver voltage to the monitoring node 114 through components configured to support (or handle, without undue stress) regardless of the voltage level under the following conditions, that is, from a relatively high voltage level (such as 4V) when the PMOS transistor 304 in the row driver 102-1 is activated to a relatively low voltage level (such as -1V) when the NMOS transistor 306 is activated. More specifically, as shown in the figure, the transmission circuit 106-1 includes the routing transistors 402-1 and 402-2 to jointly route the row driver voltage to the monitoring node 114 in the following ways: 1) when the analog voltage level of the row driver voltage is greater than the threshold level, via the first path through the routing transistor 402-1; or 2) when the analog voltage level of the row driver voltage is less than the threshold level, via the second path through the routing transistor 402-2. For example, the threshold level can be set between the voltage levels associated with the PMOS transistor 304 and the NMOS transistor 306 or set to another appropriate level based on the operating range of the routing transistor 402. The routing node 406-1 is shown as being part of the first path of the routing transistor 402-1 in Figure 4A while the routing node 406-2 is shown as being part of the second path of the routing transistor 402-2.

[0073] In this example, corresponding shield transistors are also shown in transmission circuit 106-1 placed on a first path through routing transistor 402-1 and routing node 406-1 and on a second path through routing transistor 402-2 and routing node 406-2. More specifically, as shown, first shield transistor 408-1 may be configured to protect routing transistor 402-1 from voltage levels outside a first operating range of routing transistor 402-1, while second shield transistor 408-2 may be configured to protect routing transistor 402-2 from voltage levels outside a second operating range of routing transistor 402-2. For example, shield transistor 408-1 is shown implemented as a PMOS transistor to protect routing transistor 402-1 from voltages outside the PMOS operating range, and shield transistor 408-2 is shown implemented as an NMOS transistor to protect routing transistor 402-2 from voltages outside the NMOS operating range. Like routing transistors 402, the two shield transistors 408 may help ensure that only one of the first or second paths is used and control the current in a manner that complies with the capabilities and operating ranges of the components handling the current.

[0074] After being properly routed through one of routing transistors 402-1 or 402-2 to one of routing nodes 406-1 or 406-2, corresponding monitor select transistors 410-1 and 410-2 (collectively monitor select transistors 410) are also shown included within transmission circuit 106-1 to regulate which routing node 406-1 or 406-2 is electrically connected to shared monitor node 114 and when (and under what circumstances) such connection occurs. In a manner similar to routing transistors 402 described above, transmission circuit 106-1 is shown including: 1) a first monitor select transistor 410-1 that, when activated, connects monitor node 114 to the first path (i.e., the path through routing transistor 402-1 and routing node 406-1) and routes the row driver voltage via the first path when the analog voltage level of the row driver voltage is greater than a threshold level; and 2) a second monitor select transistor 410-2 that, when activated, connects monitor node 114 to the second path (i.e., the path through routing transistor 402-2 and routing node 406-2) and routes the row driver voltage via the second path when the analog voltage level of the row driver voltage is less than the threshold level. As shown and for the same reasons as for routing transistors 402-1 and 402-2 described above, monitor select transistor 410-1 may be implemented as a PMOS transistor, and monitor select transistor 410-2 may be implemented as an NMOS transistor.

[0075] Control node 412 is also shown in transmission circuit 106-1, on which control signals can be received and used to control the activation of two monitor selection transistors 410. Although separate control signals having appropriate voltage ranges are described as being used at routing control nodes 404-1 and 404-2 to control different PMOS and NMOS routing transistors 402, this particular implementation shows a common control node 412 for controlling two monitor selection transistors 410. Accordingly, level shifter 414 is shown to convert the signal on control node 412 into an appropriate voltage level for monitor selection transistor 410-1 before being provided to the gate of monitor selection transistor 410-1 (for this example, it is assumed that the voltage level of the control signal on control node 412 is suitable for driving the gate of monitor selection transistor 410-2 without such level shifting). In other particular implementations, switching of monitor selection transistors 410 can be performed for multiple rows or globally. Thus, in some particular implementations, fewer groups of level shifters each serving multiple rows or a single global level shifter serving all rows can be employed instead of having dedicated level shifters for each row (e.g., as shown by level shifter 414).

[0076] Similarly, although this particular implementation of transmission circuit 106-1 includes dedicated monitor selection transistors 410 associated with only one row, it should be understood that in other particular implementations, monitor selection transistors can be combined across multiple rows, which is convenient for the layout of the IC. For example, routing nodes can be independently routed and combined in a common area such that in a particular implementation a single pair of monitor selection transistors can be used to serve all rows (instead of each row having its own dedicated monitor selection transistor as shown in the example of transmission circuit 106-1).

[0077] Whether dedicated or shared between rows, monitor selection transistors such as monitor selection transistors 410 can perform several functions for fault detection system 104-1. The first function that monitor selection transistors 410 are to perform is to act as protection transistors to protect routing transistors 402 during a protection period when different rows are selected to drive voltage onto shared monitor node 114 (i.e., when the row associated with transmission circuit 106-1 is not selected). More specifically, the control signal on control node 412 can be configured to control the activation of monitor selection transistors 410-1 and 410-2 according to the protection period when a different row driver is selected from among multiple row drivers other than the row driver of that row.

[0078] Another function that the monitor selection transistor 410 is to perform is to act as a sample-and-hold switch during the period when the row is selected (i.e., when the row is in a read mode and / or otherwise selected as the row to drive a voltage onto the shared monitor node 114). As will be described in more detail below, the monitor selection transistor 410 can be controlled to act as a switch to transfer the row driver voltage to the monitor node 114 in a manner that allows proper scaling, level shifting, and / or otherwise adjusting the voltage for comparison with a reference voltage in the level-based fault detection technique performed by the comparison circuit 108. Specifically, the control signal on the control node 412 can be configured to control the activation of the monitor selection transistor 410-1 and the monitor selection transistor 410-2 according to the pre-charge phase and the evaluation phase of the period when the row driver is selected from among multiple row drivers, as will now be described with respect to Figure 4A the comparison circuit 108 in Figure 4B and the timing diagram in

[0079] As Figure 4A shown (and as described and shown above with respect to Figure 1 ), the shared monitor node 114 can serve as the output node of each of the plurality of transmission circuits 106 (including the transmission circuit 106-1) and as the input node of the comparison circuit 108. To perform the functions of regulating the voltage from the monitor node 114, performing a comparison between the regulated voltage and a reference voltage, and latching a digital output based on the comparison, as described above, Figure 4A various elements that can be included in the comparison circuit 108 are shown. Specifically, as shown, the comparison circuit 108 can include: a first capacitor 418-1 having a capacitance C1, which is electrically connected to the monitor node 114; a second capacitor 418-2 having a capacitance C2, which is electrically connected between the capacitor 418-1 and ground; a regulated monitor node 420 between the capacitor 418-1 and the capacitor 418-2; a comparator device 422, which is configured to perform a comparison by being connected to the regulated monitor node 420 and a reference node 424 for the reference voltage; a first reference control transistor 426-1, which connects a first scaled reference node 430-1 to the monitor node 114 when activated by a voltage at the reference control node 428-1; and a second reference control transistor 426-2, which connects a second scaled reference node 430-2 to the regulated monitor node 420 when activated by a voltage at the reference control node 428-2, as shown.

[0080] These components of the comparator circuit 108 can be used to condition the voltage on the monitoring node 114 to prepare a voltage for level-based comparison represented by the digital output 116. To this end, capacitors 418-1 and 418-2 (collectively referred to as capacitor 418) are shown as forming a scaling circuit that is used to convert the voltage at the monitoring node 114 into a conditioned voltage at the conditioned monitoring node 420. The comparator device 422 is then configured to compare the voltage on the conditioned monitoring node 420 with a reference voltage on the reference node 424, which can be selected based on the test being performed. For example, when testing the PMOS transistor 304 of the row driver 102-1, the reference voltage on the reference node 424 can be one level (e.g., set by an LDO regulator), and when testing the NMOS transistor 306 of the row driver 102-1, the reference voltage on the reference node 424 can be a different level (e.g., set by a different LDO regulator). These tests will now be described in more detail.

[0081] During the period of selecting a particular row, the comparator circuit 108 can be configured to perform two level-based fault detection tests for the row driver of that particular row. The first level-based fault detection test is performed to determine whether there is a fault or defect in any of the PMOS transistors 304 of the row driver, and the second level-based fault detection test is performed to determine whether there is a fault or defect in any of the NMOS transistors 306 of the row driver. For both of these tests, the scaling circuit formed by the capacitor 418 helps to shift the voltage level at the monitoring node 114 to conform to the operating parameters of the comparator device 422, as well as scale the voltage level to prepare for comparison with an appropriate reference voltage (which is different for each test, as described above). As will now be described, the voltage conditioning performed by this scaling circuit can be performed differently for these two tests. However, as described above and as shown in more detail below regarding Figure 4B As shown in more detail, the voltage conditioning in each case can be performed in the same two phases: a precharge phase and an evaluation phase.

[0082] During the pre - charge phase of the test of NMOS transistor 306, the scaled reference voltage on scaled reference node 430 - 1 is sampled onto monitor node 114. Then, during the evaluation phase of the test, the row driver voltage on routing node 406 - 1 or routing node 406 - 2 is sampled onto monitor node 114. This is achieved by referring to the voltage at reference control node 428 - 2, which disconnects the scaled reference voltage on the second scaled reference node 430 - 2 from the regulated monitor node 420, such that the difference between the row driver voltage to be driven on the regulated monitor node 420 and the first scaled reference voltage (at node 430 - 1) is obtained. Specifically, if the scaled reference voltage at scaled reference node 430 - 1 is called Vref1, the scaled reference voltage at scaled reference node 430 - 2 is called Vref2, the row driver voltage routed through transmission circuit 106 - 1 is called Vhi1, and the corresponding capacitances of capacitors 418 are C1 and C2 (as labeled), then the voltage Vcomp_Vhi for this test at the regulated monitor node 420 can be calculated according to Equation 1:

[0083]

[0084] Conversely, during the pre - charge phase of the test of PMOS transistor 304, the row driver voltage on routing node 406 - 1 or routing node 406 - 2 can be sampled onto monitor node 114 by activating monitor selection transistor 410 using the control voltage on control node 412. Then, during the evaluation phase of the test, the scaled reference voltage on scaled reference node 430 - 1 is sampled onto monitor node 114. This is achieved by the control voltage at control node 412, which disconnects the row driver voltage from the regulated monitor node 420, such that the difference between the scaled reference voltage on scaled reference node 430 - 1 and the row driver voltage is driven on the regulated monitor node 420. Specifically, referring again to the labeled voltages presented above, and calling the row driver voltage routed through transmission circuit 106 - 1 for this test Vlo1, the voltage Vcomp_Vlo for this test at the regulated monitor node 420 can be calculated according to Equation 2:

[0085]

[0086] Using the regulated voltage on the regulated monitor node 420 for a given test (and once the voltage has had time to stabilize, etc.), comparator device 422 can be used to compare this voltage with an appropriate reference voltage driven onto reference node 424 depending on the test being performed. For example, as Figure 4AAs shown, the comparison circuit 108 may include a storage circuit connected to the comparator output 432 of the comparator device 422. In this example, the storage circuit is implemented as a latch 434 configured to latch the digital output 116 based on an enable signal 436. In this way, the storage circuit (latch 434) may store and output the digital output 116.

[0087] As described above, different tests may be performed at different times to check both the NMOS and PMOS transistors of each row driver. Thus, in some examples, the digital output 116 may represent a 2-bit digital output indicating the results of these two tests. For example, the digital output 116 may include a first output bit determined at a first time when the reference voltage at the reference node 424 has a first reference level (for testing the NMOS transistor 306), and a second output bit determined at a second time when the reference voltage at the reference node 424 has a second reference level (for testing the PMOS transistor 304). The first output bit may indicate whether a defect is detected in any of the NMOS transistors 306, while the second output bit may indicate whether a defect is detected in any of the PMOS transistors 304. Thus, the comparison circuit 108 may include a storage circuit (latch 434) capable of storing and outputting these two output bits for the digital output 116.

[0088] For Figure 4A For the configuration shown, if all of the NMOS transistors 306 are free of defects and faults, the comparator output 432 of the comparator device 422 may be high (logic “1”) during a first test represented by Equation 1 (where the row driver voltage is represented by Vhi1). Conversely, if at least one of the NMOS transistors 306 has a defect, the comparator output 432 may be low (logic “0”) for this first test. For a second test represented by Equation 2 (where the row driver voltage is represented by Vlo1), if all of the PMOS transistors 304 are free of defects and faults, the comparator output 432 of the comparator device 422 may be high, and for this test, if at least one of the PMOS transistors 304 has a defect, the comparator output 432 may be low. The enable signal 436 may be configured to latch the storage circuit (latch 434) to store these values for different tests at an appropriate time after switching is complete, the voltage has stabilized, etc.

[0089] To illustrate the timing of this process for two example tests performed on the row served by the row driver 102-1, Figure 4BIllustrates an exemplary timing diagram 440 of the various signals that have been shown and described with respect to the fault detection system 104-1. In this example, it will be assumed that the signaling at the routing control nodes 404-1 and 404-2 is controlled by the same decoder signals that are used to control the PMOS transistor 304 and the NMOS transistor 306, but it should be understood (as described above) that with certain modifications, the signaling can also be performed independently (using dedicated control signals).

[0090] In Figure 4B it, the timing diagram 440 depicts the characteristics of the various nodes and voltages that have been described for two example tests 442. In the first test 442-1, by ensuring the correct voltage level when the PMOS transistor of the row driver 102-1 (specifically, PMOS transistor 304-0 in this example) is selected to drive node 112 to simulate the voltage level 322-0 (Vhi1 in Equation 1), the NMOS transistor 306 is checked according to Equation 1. In the second test 442-2, by ensuring the correct voltage level when the NMOS transistor of the row driver 102-1 (specifically, NMOS transistor 306-2 in this example) is selected to drive node 112 to simulate the voltage level 322-2 (Vlo1 in Equation 2), the PMOS transistor 304 is checked according to Equation 2. As shown, the various control signals on the respective nodes that control the transistors within the fault detection system 104-1 can be driven to different levels in order to achieve the precharge and evaluation phases as they have been described, and then latch the test results at the appropriate time (when the enable signal 436 briefly goes to '1' near the end of each test 442).

[0091] In Figure 4A and Figure 4B after the level-based fault detection performed by the fault detection system 104-1 is shown and described, it is clear how this new method improves the above-described conventional fault detection mechanism (as represented by Table 330 in Figure 3F . To further illustrate these improvements, Table 330 can be contrasted with the exemplary Table 450 in Figure 4C . Table 450 indicates the fault detection capabilities of the level-based fault detection system, such as the fault detection system 104-1 described with respect to Figure 4A and Figure 4B .

[0092] Similar to Table 330 described above, Table 450 includes a leftmost column ("Transistor / Defect") that indicates the reference numerals of the row driver transistors being tested for a particular type of defect. As described above, each of PMOS transistor 304, NMOS transistor 306, and shield transistor 310 is represented in this column (a total of ten transistors), followed by the different types of possible defects in the other three columns of the table. In contrast to Table 330, Table 450 shows that a level-based fault detection system such as fault detection system 104-1 can detect not only open-circuit defects (as represented in the "S-D Open" column), but also all gate defects (as represented in the "Gate Open" column) and all short-circuit defects (as represented in the "S-D Short" column). Shield transistors 310 are again shown to successfully perform their role of providing a safe failure to other row driver transistors in the event of a defect.

[0093] Summary table 452 below Table 450 summarizes the performance of a level-based fault detection system such as described herein. For a total of 30 faults represented in Table 452, 26 faults were detected positively, and 4 safe failures were provided successfully. There were no undetected faults in this case, so the total detection coverage was 100% in this example. Thus, this level-based fault detection method significantly improves the reliability and consistency of various optical sensor applications, including high-risk applications that require such test coverage. At the same time, this method does not require significant trade-offs in terms of area usage, power usage, etc., which makes it very suitable for use in many image sensor IC designs.

[0094] Numerous embodiments have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of this specification.

[0095] It should also be understood that when an element is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on the other element, connected to the other element, or coupled to the other element, or there can be one or more intermediate elements. In contrast, when an element is referred to as being directly on another element, directly connected to another element, or directly coupled to another element, there are no intermediate elements. Although the terms directly on..., directly connected to..., or directly coupled to... may not be used throughout the detailed description, elements shown as being directly on an element, directly connected, or directly coupled can be referred to in such a manner. The claims of this application can be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0096] The various devices and techniques described herein can be implemented using a variety of semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with a semiconductor substrate, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0097] It should also be understood that when an element such as a layer, region, or substrate is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on the other element, connected to the other element, or coupled to the other element, or there can be one or more intervening elements. In contrast, when an element is referred to as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there are no intervening elements or layers.

[0098] Although the terms directly on..., directly connected to..., or directly coupled to... may not be used throughout the detailed description, elements shown as being directly on an element, directly connected, or directly coupled can be referred to in such a manner. The claims of this application can be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0099] As used in this specification, unless specifically stated otherwise in context, the singular forms can include the plural forms. Spatial relative terms (e.g., above, on, over, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientation shown in the figures. In some embodiments, the relative terms above and below can include vertically above and vertically below, respectively. In some embodiments, the term adjacent can include laterally adjacent or horizontally adjacent.

[0100] Although certain features of the described embodiments have been illustrated as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not by way of limitation, and various changes in form and detail can be made. Except for mutually exclusive combinations, any part of the devices and / or methods described herein can be combined in any combination. The embodiments described herein can include various combinations and / or sub - combinations of the functions, components, and / or features of the different embodiments described.

[0101] In addition, the logical flows depicted in the figures do not require the particular order or sequential order shown to achieve the desired result. Additionally, other steps may be provided, or steps may be eliminated from the flow, and other components may be added to or removed from the system. Accordingly, other embodiments are within the scope of the following claims.

[0102] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element, without departing from the scope of the examples discussed herein. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0103] Although certain features of the specific implementations described have been illustrated as described herein, many modifications, alternative forms, variations, and equivalent forms may occur to those skilled in the art. Accordingly, it should be understood that the appended claims are intended to cover such modifications and variations that fall within the scope of the specific implementations. It should be understood that they are presented by way of example only and not limitation, and various changes may be made in form and detail. Except for mutually exclusive combinations, any part of the devices and / or methods described herein may be combined in any combination. The specific implementations described herein may include various combinations and / or sub - combinations of the functions, components, and / or features of the different specific implementations described. Accordingly, the scope of the present disclosure is not limited to the specific combinations claimed hereinafter, but extends to cover any combination of the features or exemplary implementations described herein, regardless of whether that particular combination is specifically recited in the appended claims at this time.

Claims

1. A fault detection system, the fault detection system comprising: an input node electrically connected to a row driver, the row driver generating a row driver voltage on the input node, the row driver voltage having one of a plurality of analog voltage levels; a transmission circuit configured to transmit the row driver voltage to a monitoring node shared by a plurality of fault detection systems including the fault detection system when the row driver is selected from a plurality of row drivers; and A comparison circuit is shared by the plurality of fault detection systems and is configured to generate a digital output based on the row driver voltage and a reference voltage.

2. The fault detection system of claim 1 , wherein the row driver is configured to activate a plurality of transistors one at a time such that the row driver voltage: a first PMOS transistor among the plurality of transistors being driven at a first voltage level among the plurality of analog voltage levels when activated; a second PMOS transistor among the plurality of transistors is driven at a second voltage level among the plurality of analog voltage levels when a second PMOS transistor among the plurality of transistors is activated; a first NMOS transistor among the plurality of transistors being driven at a third voltage level among the plurality of analog voltage levels when activated; as well as A second NMOS transistor among the plurality of transistors is driven at a fourth voltage level among the plurality of analog voltage levels when activated.

3. The fault detection system of claim 2, wherein the digital output comprises: a first output bit, the first output bit being determined at a first time when the reference voltage has a first reference level, the first output bit indicating whether a defect is detected in the first NMOS transistor or the second NMOS transistor; and A second output bit is determined at a second time when the reference voltage has a second reference level, the second output bit indicating whether a defect is detected in the first PMOS transistor or the second PMOS transistor. 4 . The fault detection system of claim 3 , wherein the comparison circuit comprises a storage circuit configured to store and output the first output bit and the second output bit of the digital output.

5. The fault detection system of claim 1 , wherein the transmission circuit comprises a first routing transistor and a second routing transistor, the first routing transistor and the second routing transistor being collectively configured to route the row driver voltage to the monitoring node by: When the analog voltage level of the row driver voltage is greater than a threshold level, via a first path through the first routing transistor, or When the analog voltage level of the row driver voltage is less than the threshold level, a second path through the second routing transistor is passed.

6. The fault detection system according to claim 5, wherein the transmission circuit further comprises: a first shielding transistor configured to protect the first routing transistor from voltage levels outside a first operating range of the first routing transistor; and A second shielding transistor is configured to protect the second routing transistor from voltage levels outside a second operating range of the second routing transistor.

7. The fault detection system according to claim 1, wherein the transmission circuit comprises: a first monitor select transistor that, when activated, connects the monitor node to a first path through which the row driver voltage is routed when an analog voltage level of the row driver voltage is greater than a threshold level; a second monitor select transistor that, when activated, connects the monitor node to a second path through which the row driver voltage is routed when the analog voltage level of the row driver voltage is less than the threshold level; and A control node is provided at which a control signal is received, the control signal being configured to control activation of the first monitor select transistor and the second monitor select transistor.

8. The fault detection system of claim 7, wherein the control signal is configured to control activation of the first monitor selection transistor and the second monitor selection transistor according to a precharge phase and an evaluation phase of a period when the row driver is selected from the plurality of row drivers.

9. The fault detection system of claim 7, wherein the control signal is configured to control activation of the first monitor selection transistor and the second monitor selection transistor according to a protection period when a different row driver other than the row driver is selected from the plurality of row drivers.

10. The fault detection system according to claim 1, wherein the comparison circuit comprises: a first capacitor electrically connected to the monitoring node; a second capacitor electrically connected between the first capacitor and ground; a regulated monitoring node, the regulated monitoring node being between the first capacitor and the second capacitor; a comparator device connected to the regulated monitoring node and a reference node for the reference voltage; a first reference control transistor that, when activated, connects a first scaled reference node to the monitoring node; and A second reference control transistor, when activated, connects a second scaled reference node to the regulated monitoring node.

11. The fault detection system of claim 10, wherein the comparison circuit further comprises a storage circuit connected to an output terminal of the comparator device and configured to: latching the digital output based on an enable signal; and The digital output is stored and outputted.

12. An optical sensor integrated circuit, the optical sensor integrated circuit comprising: a plurality of row drivers, the plurality of row drivers including a row driver configured to generate a row driver voltage; and a plurality of fault detection systems for the plurality of row drivers, the plurality of fault detection systems comprising a fault detection system for the row driver, the fault detection system comprising: an input node electrically connected to the row driver to receive the row driver voltage, a monitoring node, the monitoring node being shared by the plurality of fault detection systems, a transmission circuit configured to receive the row driver voltage from the input node and transmit the row driver voltage to the monitoring node when the row driver is selected from the plurality of row drivers; and A comparison circuit is shared by the plurality of fault detection systems, the comparison circuit being configured to receive the row driver voltage via the monitoring node and to generate a digital output based on the row driver voltage and a reference voltage.

13. The optical sensor integrated circuit of claim 12 , wherein the row driver is configured to activate a plurality of transistors one at a time such that the row driver voltage: a first PMOS transistor among the plurality of transistors is driven at a first voltage level when activated; a second PMOS transistor among the plurality of transistors is driven at a second voltage level when activated; driven at a third voltage level when a first NMOS transistor among the plurality of transistors is activated; as well as driven at a fourth voltage level when a second NMOS transistor among the plurality of transistors is activated; The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are all different transistors among the plurality of transistors.

14. The optical sensor integrated circuit of claim 13, wherein the digital output comprises: a first output bit, the first output bit being determined at a first time when the reference voltage has a first reference level, the first output bit indicating whether a defect is detected in the first NMOS transistor or the second NMOS transistor; and A second output bit is determined at a second time when the reference voltage has a second reference level, the second output bit indicating whether a defect is detected in the first PMOS transistor or the second PMOS transistor.

15. The optical sensor integrated circuit of claim 12, wherein the transmission circuit comprises a first routing transistor and a second routing transistor, the first routing transistor and the second routing transistor being collectively configured to route the row driver voltage to the monitoring node by: When the analog voltage level of the row driver voltage is greater than a threshold level, via a first path through the first routing transistor, or When the analog voltage level of the row driver voltage is less than the threshold level, a second path through the second routing transistor is passed.

16. The optical sensor integrated circuit of claim 12, wherein the transmission circuit comprises: a first monitor select transistor that, when activated, connects the monitor node to a first path through which the row driver voltage is routed when an analog voltage level of the row driver voltage is greater than a threshold level; a second monitor select transistor that, when activated, connects the monitor node to a second path through which the row driver voltage is routed when the analog voltage level of the row driver voltage is less than the threshold level; and A control node is provided at which a control signal is received, the control signal being configured to control activation of the first monitor select transistor and the second monitor select transistor.

17. A method comprising: receiving a row driver voltage at an input node of a fault detection system electrically connected to a row driver of the plurality of row drivers; transmitting, by transmission circuitry within the fault detection system and based on selecting the row driver from the plurality of row drivers, the row driver voltage to a monitoring node shared by a plurality of fault detection systems including the fault detection system; and A digital output is generated by a comparison circuit shared by the plurality of fault detection systems by regulating a voltage from the monitoring node, performing a comparison between the regulated voltage and a reference voltage, and latching the digital output based on the comparison.

18. The method of claim 17, wherein: The row driver is configured to activate a plurality of transistors of the row driver one at a time such that the row driver voltage: When a first PMOS transistor among the plurality of transistors is activated, it is driven at a first voltage level, When a second PMOS transistor among the plurality of transistors is activated, it is driven at a second voltage level, is driven at a third voltage level when a first NMOS transistor among the plurality of transistors is activated, and driven at a fourth voltage level when a second NMOS transistor among the plurality of transistors is activated; The first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are all different transistors among the plurality of transistors.

19. The method of claim 18, wherein generating the digital output comprises: determining a first output bit of the digital output at a first time when the reference voltage has a first reference level, the first output bit indicating whether a defect is detected in the first NMOS transistor or the second NMOS transistor; as well as A second output bit of the digital output is determined at a second time when the reference voltage has a second reference level, the second output bit indicating whether a defect is detected in the first PMOS transistor or the second PMOS transistor.

20. The method of claim 17, wherein transmitting the row driver voltage to the monitoring node comprises: The row driver voltage is routed in the following way: When the analog voltage level of the row driver voltage is greater than a threshold level, via a first path through a first routing transistor within the transmission circuit, or via a second path through a second routing transistor within the transmission circuit when the analog voltage level of the row driver voltage is less than the threshold level; connecting the monitoring node to the first path through the first monitor select transistor when the first monitor select transistor is activated; connecting the monitoring node to the second path through a second monitor selection transistor when the first monitor selection transistor is activated; as well as Activation of the first monitor select transistor and the second monitor select transistor is controlled by a control signal received on a control node.

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