Design method of ultra-small high-sampling-rate one-driving-eight fast reflector controller

Abstract

The invention discloses a design method of a subminiature high-sampling-rate one-driving-eight fast reflecting mirror controller, and relates to the technical field of photoelectric device measurement. The controller controls eight groups of fast reflecting mirrors; sCI serial communication is realized between the main control computer and the controller; the controller adopts a DSP + FPGA architecture mode, and an FPGA chip transmits internal data to a DSP chip through SRIO; the DSP chip is used for external communication and implementation of a fast reflector closed-loop algorithm; the FPGA chip is used for realizing AD acquisition, DA driving and a digital current loop algorithm; input signals of the fast reflectors are transmitted to the digital current loop module after being processed by a closed-loop algorithm, the FPGA chip calls the DAC module to process the output of the digital current loop, and the output power is adjusted by the power amplifier module so as to control the eight groups of fast reflectors in real time; and the FPGA chip calls the ADC module to collect feedback voltage of the fast reflectors in real time and feed the feedback voltage back to the FPGA chip, and the feedback voltage is processed by a closed-loop algorithm and a digital current loop algorithm to realize synchronous and real-time closed-loop control of the eight groups of fast reflectors.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic device measurement, and particularly to a design method for an eight-channel fast steering mirror controller with ultra-small size and high sampling rate. Background Art

[0002] Fast steering mirrors have the advantages of small moment of inertia, high positioning accuracy, and fast response speed. They have been applied in fields such as scanning image motion compensation, line of sight stabilization, and laser communication. Installing a fast steering mirror into an imaging optical path can effectively improve the imaging quality of the system.

[0003] For the application requirements of large and complex optical systems that need to use multiple fast steering mirrors to achieve beam combination, the existing fast steering mirror systems usually use one controller to drive one or two bodies. If multiple fast steering mirror systems are needed, multiple controllers need to be used simultaneously, which will increase the weight and volume of the system. However, large and complex optical systems do not have enough reserved volume and weight, so strict requirements are imposed on the volume and weight of the fast steering mirror controller.

[0004] Due to the high bandwidth usage requirements of fast steering mirrors, high sampling rate requirements are imposed on the internal controller. The existing technology controllers can achieve high sampling rate when driving one or two bodies. If the number of bodies is increased, both data acquisition and driving the motor will occupy system machine time, resulting in a decrease in the system sampling rate, and thus the bandwidth of the fast steering mirror will be significantly reduced.

[0005] Chinese Patent Application for Invention (Application No.: 201510279016.5) discloses an analog control circuit for improving the control bandwidth of a fast steering mirror. The invention improves the control bandwidth of the fast steering mirror by building an analog control circuit. This circuit can compensate the structural resonance of the fast steering mirror in real time, improve the amplitude-frequency characteristics of the fast steering mirror, and can implement simple control algorithms. This patent improves the amplitude-frequency characteristics through an analog circuit, but its function implementation lacks flexibility and is limited by hardware chips, with limited improvement in high-bandwidth applications. Especially when driving multiple fast steering mirrors, using this method greatly increases the application cost.

[0006] Therefore, aiming at the disadvantages of the existing design methods for fast steering mirror controllers, a design method for an eight-channel fast steering mirror controller with ultra-small size and high sampling rate is designed. High-speed data acquisition is carried out based on the FPGA architecture and then transmitted to the DSP chip through SRIO. This transmission mechanism does not occupy a large amount of machine time, so high sampling rate can be achieved, which can ensure the high-bandwidth characteristics of the fast steering mirror system. At the same time, by adopting a digital current loop design, the volume of the controller is greatly reduced, the number of chips used is reduced, and the application cost is reduced to solve the above problems. Summary of the Invention

[0007] The object of the present invention is to provide a design method for a one - to - eight fast steering mirror controller with ultra - small size and high sampling rate, so as to solve the problem in the prior art that multi - channel fast steering mirrors cannot achieve high - bandwidth miniaturization.

[0008] To achieve the above object, the present invention provides the following technical solutions: A design method for a one - to - eight fast steering mirror controller with ultra - small size and high sampling rate. This method is equipped with a power supply box, a controller, fast steering mirrors and a main control computer. The power supply box provides the required voltage for the controller: The controller controls eight groups of fast steering mirrors; The main control computer realizes SCI serial communication with the controller; The controller has a DSP chip and an FPGA chip; The controller adopts a DSP + FPGA architecture. The FPGA chip transmits internal data to the DSP chip through SRIO; The DSP chip is used for external communication and the implementation of the closed - loop algorithm of the fast steering mirror; The FPGA chip is used for AD acquisition, DA drive and the implementation of the digital current loop algorithm; The input signal of the fast steering mirror is processed by the closed - loop algorithm and then transmitted to the digital current loop module. The FPGA chip calls the DAC module to process the output of the digital current loop and the power amplifier module adjusts the output power to realize the real - time control of the working voltage of the power amplifier output to control eight groups of fast steering mirrors; The FPGA chip calls the ADC module to real - time collect the feedback voltage of the fast steering mirror, and feeds back the feedback voltage amount to the FPGA chip for processing through the closed - loop algorithm and the digital current loop algorithm to realize the synchronous and real - time closed - loop control of eight groups of fast steering mirrors.

[0009] Further, the main control computer is connected to the communication chip of the controller through the SCI port, and is transmitted to the DSP chip through the communication chip to realize the external communication of the controller.

[0010] Further, the FPGA chip outputs the control voltage processed by the digital current loop algorithm through two groups of four - channel DAC modules; The control voltage output by the DAC module is power - adjusted by the power amplifier module to provide the output voltage for the drive motor of the fast steering mirror, and at the same time collects the feedback voltage and transmits it to two groups of four - channel ADC modules for analog - to - digital conversion and then transmits it to the FPGA chip to realize the closed - loop control of the fast steering mirror.

[0011] Further, the FPGA chip outputs the control voltage processed by the digital current loop algorithm through a single group of eight - channel DAC modules; The control voltage output by the DAC module is adjusted in power by the power amplifier module and then provides the output voltage for the drive motor of the fast steering mirror. At the same time, the feedback voltage is collected and transmitted to the single-group eight-channel ADC module for analog-to-digital conversion and then transmitted into the FPGA chip to realize the closed-loop control of the fast steering mirror. Further, the controller is connected to the main control computer through a USB to RS422 cable.

[0012] In the above technical solution, a design method of a super-small high-sampling-rate one-to-eight fast steering mirror controller of the present invention has the following beneficial effects: 1. The method of implementing one-to-eight by adopting the DSP+FPGA architecture can achieve high-bandwidth design. When using the conventional method to control eight fast steering mirrors, generally a single DSP chip or FPGA chip is used to control one fast steering mirror. Therefore, eight DSP chips or FPGA chips are required to control eight fast steering mirrors at the same time. This method can achieve a one-to-eight architecture by using one DSP chip and one FPGA chip, and compared with the traditional use of a single DSP chip or FPGA chip, the system sampling rate will not decrease. Therefore, high-bandwidth performance can be guaranteed, and at the same time, this architecture has the advantages of small volume and low cost. 2. The traditional controller uses the same DSP chip to drive eight bodies. In order to ensure the system performance, the control of the eight bodies is achieved by sacrificing the high sampling rate. Therefore, the bandwidth of the fast steering mirror will decrease. This method performs high-speed data acquisition based on the FPGA architecture and then transmits it to the DSP chip through SRIO. This transmission mechanism does not occupy a large amount of machine time. Therefore, a high sampling rate can be achieved, and the high-bandwidth characteristics of the system can be guaranteed. 3. The architecture in this method can realize the design of a super-small controller. When implementing the design of a fast steering mirror controller by the conventional method, it is necessary to use an analog circuit method to implement the current loop design, that is, the traditional analog current loop design requires at least 3 four-operational amplifiers to provide the output, and in the one-to-eight application, at least 24 four-operational amplifiers are required to provide the output; in this method, a digital method is used to implement the digital current loop design in the FPGA chip, which greatly reduces the design space in the controller to achieve a smaller volume design and further reduces the cost. Description of the Drawings

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0014] Figure 1Block diagram of a design method for a super-small and high-sampling-rate one-to-eight fast steering mirror controller provided by an embodiment of the present invention; Figure 2 Schematic diagram of internal function division of the controller in a design method for a super-small and high-sampling-rate one-to-eight fast steering mirror controller provided by an embodiment of the present invention; Figure 3 Flow chart of the digital current loop in a design method for a super-small and high-sampling-rate one-to-eight fast steering mirror controller provided by an embodiment of the present invention; Figure 4 Schematic diagram of the hardware structure in a design method for a super-small and high-sampling-rate one-to-eight fast steering mirror controller provided by an embodiment of the present invention; Figure 5 Flow chart of a design method for a super-small and high-sampling-rate one-to-eight fast steering mirror controller provided by an embodiment of the present invention. Detailed implementation manners

[0015] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the detailed implementation manners and with reference to the accompanying drawings; it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention; in addition, in the following descriptions, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0016] Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0017] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0018] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, like reference numerals are used to represent like elements. For clarity, the various parts in the drawings are not drawn to scale.

[0019] See Figures 1 - 5 as shown; A design method for a super-small and high-sampling-rate one-to-eight fast steering mirror controller includes: The specific implementation method is as follows: 1) Power the power supply box through external power supply, provide the required voltage for the controller through the power supply box, control eight fast steering mirrors through the controller, implement SCI serial communication between the external main control computer and the controller, and connect each device through a dedicated cable. Among them, the main control computer is connected to the controller through a USB to RS422 cable; 2) Inside the controller, it is designed by combining an octa-core TMS320C6678 chip with a K7 architecture FPGA. Among them, TMS320C6678 is mainly responsible for the closed-loop algorithm of the fast steering mirror system and external communication. The FPGA chip is mainly responsible for calling the ADC module, calling the DAC module, and implementing the digital current loop algorithm. High-speed data acquisition is carried out based on the FPGA architecture. The FPGA chip transmits internal data to the DSP chip through SRIO; 3) At the hardware level (see Figure 4 ), the external main control computer is connected to the communication chip of the controller through the SCI port; it is transmitted to the DSP chip (TMS320C6678) through the communication chip to realize the external communication of the controller. The DSP chip transmits through SRIO to the FPGA chip (K7 architecture). The FPGA chip outputs the control voltage processed by the digital current loop algorithm through two four-channel DAC modules (or a single eight-channel DAC module can also be used to further reduce the volume and control cost of the controller). The control voltage output by the DAC module is power-adjusted by the power amplifier module and then provides the output voltage for the drive motor of the fast steering mirror. At the same time, the feedback voltage is collected and transmitted to two four-channel ADC modules (or a single eight-channel ADC module) for analog-to-digital conversion, and then transmitted into the FPGA chip to realize the closed-loop control of the fast steering mirror system; 4) At the software level (see Figure 5 ), the CCS (Code composer studio) engineering software is used to edit the DSP closed-loop control algorithm, and it participates in the closed-loop control of the fast steering mirror inside the FPGA chip through SRIO. The Vivado engineering software is used to realize the program code editing, design the digital current loop in the FPGA chip, and transmit the required input signal of the fast steering mirror into the digital current loop module after being processed by the closed-loop control algorithm. The FPGA chip calls the DAC module to process the output of the digital current loop, and the power amplifier module adjusts the output power so that the working voltage output by the power amplifier can control eight fast steering mirrors in real time; the FPGA chip calls the ADC module to collect the feedback voltage of the fast steering mirror in real time and feeds back the feedback voltage amount into the FPGA chip to participate in the closed-loop algorithm processing and current loop algorithm processing to realize the synchronous real-time closed-loop control of eight fast steering mirrors; 5) In specific applications, its function verification and performance testing can be carried out according to the requirements of the fast steering mirror protocol. It communicates with the external main control computer through the DSP chip, receives control instructions, reports the status of the fast steering mirror, and realizes the drive and feedback of the fast steering mirror by the FPGA chip according to the closed-loop algorithm of the DSP chip, executes different working modes of the external main control computer, and synchronously realizes the real-time control of eight fast steering mirrors.

[0020] The digital current loop algorithm process is as follows (see Figure 3): Define the input voltage h_Reference (voltage parameter), the feedback voltage h_PresentFeedback collected by the FPGA, the proportional parameter KP, and the integral parameter KI according to the actual application requirements. Subtract h_PresentFeedback from h_Reference to obtain the error quantity W_Error. Multiply W_Error by KP and KI respectively to obtain the proportional coefficient P_Term and the integral coefficient I_Term. Accumulate I_Term with the next beat integral coefficient Wintegral to obtain the integral quantity Dwaux. Sum Dwaux and P_Term to obtain the output voltage quantity Houtput, and finally implement the digital current loop algorithm.

[0021] Only some exemplary embodiments of the present invention are described above by way of illustration. Without doubt, for those of ordinary skill in the art, the described embodiments can be modified in various different ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A design method for an ultra-small high sampling rate one-to-eight fast reflector controller, which is equipped with a power supply box, a controller, a fast reflector and a main control computer, and the power supply box provides the controller with the required voltage, characterized in that: Controlling eight groups of fast reflection mirrors by the controller; The main control computer and the controller realize SCI serial port communication; The controller comprises a DSP chip and an FPGA chip; The controller adopts DSP+FPGA architecture, and the FPGA chip transmits internal data with the DSP chip via SRIO; The DSP chip is used for external communication and the implementation of the fast mirror closed-loop algorithm; The FPGA chip is used for AD acquisition, DA driving and implementation of digital current loop algorithm; The input signal of the fast reflection mirror is processed by the closed-loop algorithm and then transmitted to the digital current loop module. The DAC module is called by the FPGA chip to process the digital current loop output and the power amplifier module adjusts the output power to achieve the working voltage output by the power amplifier to control eight groups of fast reflection mirrors in real time. The ADC module is called by the FPGA chip to collect the feedback voltage of the fast reflection mirror in real time, and the feedback voltage is fed back to the FPGA chip for closed-loop algorithm processing and digital current loop algorithm processing to realize synchronous and real-time closed-loop control of eight groups of fast reflection mirrors.

2. The design method of an ultra-small high sampling rate one-to-eight fast mirror controller according to claim 1 is characterized in that: The main control computer is connected to the communication chip of the controller via the SCI port, and the information is transmitted to the DSP chip via the communication chip to realize external communication of the controller.

3. The design method of an ultra-small high sampling rate one-to-eight fast mirror controller according to claim 1, characterized in that: The FPGA chip outputs a control voltage processed by a digital current loop algorithm through two groups of four-way DAC modules; The control voltage output by the DAC module is adjusted in power by the power amplifier module to provide an output voltage for the driving motor of the fast reflector, and at the same time, the feedback voltage is collected and transmitted to two groups of four-channel ADC modules for analog-to-digital conversion and transmitted to the FPGA chip to realize closed-loop control of the fast reflector.

4. The design method of an ultra-small high sampling rate one-to-eight fast mirror controller according to claim 1, characterized in that: The FPGA chip outputs a control voltage processed by a digital current loop algorithm through a single set of eight-way DAC modules; The control voltage output by the DAC module is power-adjusted by the power amplifier module to provide output voltage for the driving motor of the fast reflector, and at the same time, the feedback voltage is collected and transmitted to a single group of eight-channel ADC modules for analog-to-digital conversion and transmitted to the FPGA chip to realize closed-loop control of the fast reflector.

5. The design method of an ultra-small high sampling rate one-to-eight fast mirror controller according to claim 1, characterized in that: The controller is connected to the main control computer via a USB to RS422 cable.

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