Broadband beam pointing switching method based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a broadband beam pointing switching method based on an FPGA, and belongs to the technical field of digital phased arrays. The method comprises the steps that the FPGA receives and caches array configuration parameters; time delay filter coefficients and phase shifter coefficients of the array elements are calculated in parallel based on a singing function and a cordic algorithm; quantizing the coefficients, and pre-storing the quantized coefficients in an RAM (Random Access Memory) according to beam pointing; judging beam switching according to an automatic timing or external instruction mode, reading a coefficient corresponding to a target direction, and issuing the coefficient to each processing unit; an FIR filter and a phase shifter are reconfigured, and broadband signal time domain beam forming is achieved through a multi-phase filtering structure; and carrying out gain normalization and truncation correction on the composite signal and then outputting the composite signal. According to the invention, a traditional DSP + FPGA architecture is abandoned, the FPGA independently completes coefficient calculation and beam forming, through pre-storage, assembly line issuing and multi-phase processing, the beam pointing switching speed and the synthesis efficiency are significantly improved, and the method is suitable for broadband beam forming systems with high real-time requirements, such as radar and communication.

Description

A Broadband Beam Pointing Switching Method Based on FPGA Technical Field

[0001] This invention belongs to the field of information warfare, specifically referring to a broadband beam pointing switching method based on FPGA. Background Technology

[0002] Broadband digital beamforming is a core technology in modern radar and 5G communication systems. It digitally performs independent real-time amplitude and phase weighting on the broadband signals received by each array element, forming a high-gain beam with flexible pointing and controllable shape in the airspace.

[0003] Existing broadband beamforming (DBF) methods are based on DBF systems that utilize the cooperation of DSPs and FPGAs. The software at the control panel sends array element parameters, beam count, beam bandwidth, and other relevant information to the DSP. The DSP / CPU then calculates the filter coefficients and phase shifter coefficients for time-domain beamforming, and finally sends these parameters to the FPGA via a bus. The FPGA then performs broadband beamforming and beam pointing tracking and switching. However, for scenarios with high timeliness and stability requirements, the method of using a DSP or CPU for parameter calculation before sending the data to the FPGA clearly cannot achieve the required beam pointing switching speed. Summary of the Invention

[0004] The purpose of this invention is to overcome the defects in the prior art and propose a broadband beam pointing switching method based on FPGA. This method abandons the traditional DSP+FPGA processing architecture and directly sends relevant parameters to the FPGA through the interface. It makes full use of the high parallel processing speed of the FPGA and achieves rapid beam pointing response by automatically calculating coefficients and configuring IP cores through the FPGA.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A broadband beam pointing switching method based on FPGA includes the following process:

[0007] Step 1: The host computer sends and caches the initial configuration parameters of the array to the FPGA, including sampling rate, signal bandwidth, beam pointing, element spacing, number of elements, and number of beams to be synthesized. Step 2: Based on the configuration parameters cached in Step 1, the FPGA uses the Singer function to calculate the required delay for each element channel and generates the corresponding delay filter coefficients accordingly. Simultaneously, based on the same configuration parameters, the Cordic algorithm is used to simplify the Singer function data, and the required phase shifter coefficients for each element are calculated. Step 3: The delay filter coefficients calculated in Step 2 are quantized into fixed-point numbers and, together with the phase shifter coefficients calculated in Step 2, are pre-stored in the FPGA's internal memory, indexed by the beam pointing. Step 4: According to a preset switching mode, it is determined whether to trigger beam pointing switching. The switching modes include an automatic switching mode based on an internal timer and a passive switching mode responding to host computer commands. Step 5: When step 4 determines that a switch is needed, the corresponding time delay filter coefficients and phase shifter coefficients are read from the internal memory described in step 3 according to the target beam direction; the time delay filter coefficients are sent in parallel to the FIR filters corresponding to each array element for reconfiguration, and the phase shifter coefficients are sent to the corresponding phase shifters; Step 6: The broadband digital signals input to each array element flow through the FIR filters that have been reconfigured in step 5 for time delay compensation, and then through the phase shifters configured with the coefficients sent in step 5 for phase weighting. Finally, the signals processed by each channel are synthesized to form the beam pointing to the current target.

[0008] Step 7: Compensate and correct the gain and truncation errors of the synthesized beam signal in Step 6, and output the final complex beam signal; Step 8: Repeat Steps 4 to 7 to achieve rapid cyclic switching between different beam directions.

[0009] Furthermore, in step 2, the time delay between adjacent array elements is calculated using the linear array time delay calculation formula. for:

[0010] ,

[0011] Where L is the element spacing. For pointing angle, For the speed of light, based on the calculated time delay To solve for the time delay filter coefficients:

[0012] ,

[0013] Where n is the number of array elements and L is the spacing between array elements. This is the intermediate frequency of the signal.

[0014] Furthermore, the phase shifter coefficients in step 2 are obtained by solving trigonometric functions, where the I-path phase shifter is:

[0015] ;

[0016] Q-channel phase shifter:

[0017] ,

[0018] In the formula: n is the number of array elements, and L is the spacing between array elements. For the intermediate frequency of the signal, The pointing angle; It is the speed of light.

[0019] Furthermore, in step 3, the quantization process involves quantizing the floating-point coefficients into 16-bit fixed-point numbers and performing truncation and rounding optimizations to balance resource consumption and computational accuracy.

[0020] Furthermore, in step 6, the broadband signal time-domain beamforming is implemented using a polyphase filter structure, specifically including:

[0021] Step 701: The high-speed data stream of each array element is decomposed into multiple low-speed parallel sub-streams.

[0022] Step 702: Each substream undergoes delay compensation through an independent FIR filter;

[0023] Step 703: The compensated sub-streams are re-merged and phase-weighted by a phase shifter;

[0024] Step 704: The weighted signals of all array elements are added together in the time domain to complete beamforming.

[0025] Furthermore, in step 7, the gain is scaled proportionally to the output signal based on the current number of channels and coefficient amplitude of beamforming to maintain a consistent dynamic range of the signal.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] 1. This invention abandons the traditional DSP+FPGA operation mode and uses FPGA to independently realize intelligent switching of broadband beam pointing, thus achieving a significant improvement in switching speed.

[0028] 2. This invention is technologically advanced, has a moderate computational load, is easy to implement in engineering, and can realize real-time processing of broadband beam signals. Attached Figure Description

[0029] Figure 1 is a flowchart of the broadband beam pointing fast switching method in an embodiment of the present invention.

[0030] Figure 2 is a diagram illustrating the effect of rapid beam pointing switching in an embodiment of the present invention. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings.

[0032] A broadband beam pointing switching method based on FPGA is disclosed, which is used to quickly switch the pointing of array beam signals. The method includes the following steps:

[0033] (1) The relevant configuration parameters of the buffer array, including sampling rate, signal bandwidth, beam pointing, array element spacing, number of array elements and number of synthesized beams, are pre-loaded into the FPGA buffer in the DBF synthesis board by the host computer; the beam signal data stream comes from the sampled signal received by the array DBF system and is a digital signal after calibration, frequency conversion and filtering.

[0034] (2a) The FPGA uses the Singer function to implement the channel delay of each array element. The beam delay effect is achieved through the Singer function, and the filter coefficients of different array elements are calculated. According to the linear array delay calculation formula, the delay function between adjacent array elements in the horizontal and vertical directions can be derived as follows: , where L is the element spacing; The pointing angle; For the speed of light, based on the calculated time delay To solve for the time delay filter coefficients, the calculation formula is: In the formula, n is the number of array elements; L is the spacing between array elements; The intermediate frequency of the signal; This represents the time delay.

[0035] (2b) The coefficients of the phase shifter can be directly obtained using trigonometric functions. The relevant calculation formula is: I-channel phase shifter: The formula for calculating the Q-channel phase shifter is: In the formula, n is the number of array elements; L is the spacing between array elements; The intermediate frequency of the signal; The pointing angle; It is the speed of light.

[0036] (2c) In FPGA, considering the low accuracy of calculating trigonometric functions using the lookup table method, a Cordic soft core is used. By performing a micro-rotation (pseudo-rotation) at a fixed angle, the initial vector is rotated to the target angle. The trigonometric function value is approximated by shifting and addition / subtraction, avoiding direct multiplication and division or complex trigonometric function calculations. At the same time, the coefficients of the shifter are calculated using the Cordic core.

[0037] (2d) The FPGA uses the Cordic algorithm to simplify the calculation process of the sinc function. Since the direct calculation of the sinc function consumes a lot of logic and multiplier resources in the FPGA, this invention also uses the Cordic algorithm for iterative approximation when calculating the coefficients of the delay filter, converting the complex multiplication and division operations into shift and addition / subtraction operations, which significantly simplifies the implementation structure of the sinc function and saves FPGA resources.

[0038] (3) Quantize the filter coefficients. Taking into account both resources and computational accuracy, the beamforming system obtained by the Cordic algorithm is truncated and rounded to quantize the correlation coefficients into 16-bit fixed-point type.

[0039] (4) Cache the filter coefficients of different beam directions; pipeline calculate the beam filter coefficients of the required scanning angle and store them in RAM for later distribution.

[0040] (5) Determine whether to perform beam pointing switching; beam switching includes two modes: one is automatic timed switching mode, which can automatically switch beam pointing throughout the process; the other is passive switching mode, which is manually switched by issuing instructions from the host computer.

[0041] (6) Read the beam angle coefficients in a loop; send the synthesized filter coefficients stored in RAM to each discrete beam synthesizing unit in parallel. To improve configuration efficiency, the system uses a pipelined approach to read the coefficients of each beam direction from RAM in a loop. The coefficients of the next target beam can be pre-read within the previous beam synthesizing cycle, hiding the storage access delay.

[0042] (7) Configure FIR filter coefficients; For each beamforming unit, the received coefficients will automatically trigger its internal FIR filter to reconfigure the coefficients. The whole process does not require external processor intervention, realizing a closed loop of automatic distribution and automatic configuration.

[0043] (8a) FPGA utilizes an FIR filter bank to implement time-domain beamforming; for an array with N elements, if M frequency points are selected, an N*(M*2) weighting matrix can be obtained. Each row of this matrix represents the impulse response of the FIR filter after one element, and this impulse response can be implemented by an FIR filter designed using an adaptive method. That is, the amplitude weight and phase weight of each element are obtained, and then a set of filters is designed so that the amplitude and phase weights of the amplitude and phase responses of each filter at these frequency points are the same or approximately the same. In other words, FIR filters are designed so that their amplitude and phase responses at the frequencies of interest are fitted with the amplitude and phase weights required for each element, respectively. The calculation formula is:

[0044] .

[0045] Where k is the number of time-domain points, and m represents the time-domain shift.

[0046] (8b) For broadband beamforming, a single beam signal is split into polyphase data to achieve low clock processing and high sampling rate. At the same time, each data item is passed through an independent FIR filter, then time-domain summed and split back into polyphase signals. Finally, each signal is multiplied by its respective shifter coefficient to complete the entire process of time-domain broadband beamforming.

[0047] (9) Correct the beam cutoff and output beam information; based on the synthesis gain (determined by the number of synthesis channels and coefficient amplitude), effectively correct the output beam sign bit and output the current downward beam complex signal.

[0048] (10) Repeat steps (1) to (9) to realize the method of fast synthesis and switching of broadband beam signals in multiple angles and directions.

[0049] Repeat steps (1) to (10) to achieve rapid switching of broadband beam pointing.

[0050] This invention abandons the traditional DSP+FPGA architecture for beamforming, and instead uses the Cordic algorithm in the FPGA to independently implement time-domain beamforming, thereby improving the visualization level of beam scanning and beam tracking. This invention is technologically advanced and represents a significant improvement over existing technologies.

[0051] It should be understood that the above description of the specific embodiments of this patent is merely an exemplary description provided to facilitate understanding of the patent solution by those skilled in the art, and does not imply that the scope of protection of this patent is limited to these specific examples. Those skilled in the art can obtain more specific embodiments without any creative effort by combining technical features, replacing some technical features, adding more technical features, etc., of the various examples listed in this patent, provided that they have a full understanding of the technical solution of this patent. All of these specific embodiments are within the scope of the claims of this patent, and therefore, these new specific embodiments should also be within the scope of protection of this patent.

Claims

1. A broadband beam pointing switching method based on FPGA, characterized in that, The process includes the following steps: Step 1, the host computer sends and caches the initial configuration parameters of the array to the FPGA, including sampling rate, signal bandwidth, beam pointing, element spacing, number of elements, and number of beams to be synthesized; Step 2, based on the configuration parameters cached in Step 1, the FPGA uses the Singer function to calculate the required delay for each element channel and generates the corresponding delay filter coefficients accordingly; simultaneously, based on the same configuration parameters, the Cordic algorithm is used to simplify the Singer function data and calculate the required phase shifter coefficients for each element; Step 3, the delay filter coefficients calculated in Step 2 are quantized into fixed-point numbers and, together with the phase shifter coefficients calculated in Step 2, are pre-stored in the FPGA's internal memory using the beam pointing as an index. Step 4: Determine whether beam pointing switching is triggered according to the preset switching mode; the switching mode includes an automatic switching mode based on an internal timer and a passive switching mode responding to instructions from the host computer. Step 5: When Step 4 determines that switching is required, read the corresponding time delay filter coefficients and phase shifter coefficients from the internal memory mentioned in Step 3 according to the target beam pointing; send the time delay filter coefficients in parallel to the corresponding FIR filters of each array element for reconfiguration, and send the phase shifter coefficients to the corresponding phase shifters. Step 6: The broadband digital signals input to each array element flow through the reconfigured FIR filters in Step 5 for time delay compensation, then pass through the phase shifters configured with the coefficients sent in Step 5 for phase weighting, and finally synthesize the signals processed by each channel to form the beam pointing to the current target. Step 7: Compensate and correct the gain and truncation errors of the synthesized beam signal in Step 6, and output the final complex beam signal. Step 8: Repeat Steps 4 to 7 to achieve rapid cyclic switching between different beam pointing directions.

2. The broadband beam pointing switching method based on FPGA according to claim 1, characterized in that, In step 2, the time delay between adjacent array elements is calculated using the linear array time delay calculation formula. for: Where L is the element spacing, For pointing angle, For the speed of light, based on the calculated time delay To solve for the time delay filter coefficients: Where n is the number of array elements and L is the spacing between array elements. This is the intermediate frequency of the signal.

3. The broadband beam pointing switching method based on FPGA according to claim 1, characterized in that, The phase shifter coefficients in step 2 are obtained by solving trigonometric functions, where I-path phase shifter: Q-channel phase shifter: In the formula: n is the number of array elements, and L is the spacing between array elements. For the intermediate frequency of the signal, The pointing angle; It is the speed of light.

4. The broadband beam pointing switching method based on FPGA according to claim 1, characterized in that, In step 3, the quantization process involves quantizing the floating-point coefficients into 16-bit fixed-point numbers and performing truncation and rounding optimizations to balance resource consumption and computational accuracy.

5. The broadband beam pointing switching method based on FPGA according to claim 1, characterized in that, In step 6, the broadband signal time-domain beamforming is implemented using a polyphase filter structure, specifically including: step 701, decomposing the high-speed data stream of each array element into multiple low-speed parallel substreams using polyphase filtering; step 702, performing time delay compensation on each substream using an independent FIR filter; step 703, re-merging the compensated substreams and performing phase weighting via a phase shifter; and step 704, adding the weighted signals of all array elements in the time domain to complete beamforming.

6. The broadband beam pointing switching method based on FPGA according to claim 1, characterized in that, In step 7, the gain is scaled proportionally to the output signal based on the number of channels and coefficient amplitude of the current beamforming to maintain a consistent dynamic range.

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