A modular data encryption and decryption system and method

Abstract

The present invention relates to a modular data encryption and decryption system and method, belonging to the field of computer cryptography. The modular encryption and decryption architecture of the present invention runs on a system-on-chip processor and an FPGA respectively. Through the decoupled design and collaborative work of the management software and the microprocessor module software on the system-on-chip, the decoupling of cryptographic processing from the underlying hardware is achieved, and the problems of repeated design and repeated replacement of cryptographic application modules are solved; the FPGA architecture adopts the method of embedding multiple algorithm modules, and the microprocessor module corresponds to the FPGA algorithm module one by one, solving the problem that one cryptographic application module can run on multiple hardware platforms and one hardware platform can run multiple cryptographic application modules. The management software communicates with the microprocessor module by adopting the internal standard socket method of the system and communicates with the FPGA by adopting the bus method, realizing the standardization and platformization of different microprocessor modules and different cryptographic modules, and completing functions such as the scheduling of cryptographic microprocessor modules and the unified management of cryptographic resources.

Description

Technical Field

[0001] The present invention belongs to the field of computer cryptography, and particularly relates to a modular data encryption and decryption system and method. Background Art

[0002] With the diversified development of cryptographic system equipment, its hardware platform often adopts a customized design idea according to different application scenarios and specific functions. Only by improving the compatibility and generality of the cryptographic system hardware platform can embedded cryptographic devices have high processing performance and fast interaction capabilities. The key technology to achieve this requirement is to adopt a modular design idea to separate computing and management and meet different application requirements.

[0003] In an embedded cryptographic system implementing standardized design, algorithms are mostly integrated in the FPGA architecture now, and management software conducts unified management of cryptographic resources and algorithm scheduling. Therefore, modular replacement cannot be achieved, and it is difficult to achieve generality for different processors, different FPGAs, and different algorithms, which restricts the development efficiency and code reusability. Summary of the Invention

[0004] (I) Technical Problems to be Solved

[0005] The technical problem to be solved by the present invention is how to provide a modular data encryption and decryption system and method to solve the problems that the existing encryption and decryption systems cannot achieve modular replacement, are difficult to achieve generality for different processors, different FPGAs, and different algorithms, and restrict the development efficiency and code reusability.

[0006] (II) Technical Solutions

[0007] To solve the above technical problems, the present invention proposes a modular data encryption and decryption system. The system architecture includes a system-level processor chip, an FPGA chip, and a non-volatile memory. The system-level processor chip includes a microprocessing module and management software. The FPGA chip includes an algorithm module and FPGA framework software; microprocessing module resources are stored on the non-volatile storage medium;

[0008] The software on the FPGA chip includes FPGA framework software and an algorithm module; the FPGA framework software is responsible for providing all external interfaces, internal interconnection buses, peripheral calls, clock reset resources, and underlying protocol parsing functions to provide services for the FPGA algorithm module; the algorithm module implements specific business data cryptographic protocol parsing and cryptographic algorithm implementation; the FPGA framework software and the algorithm module interact through the FPGA module interface protocol;

[0009] A real-time operating system runs on the processor chip. The software on the processor chip includes management software and a microprocessing module. The management software is used for module loading, overall scheduling of system processes, and management of cryptographic resources, including a resource management module, a system control module, and an FPGA communication module. The FPGA communication module is used to receive data from the microprocessing module and send it to the FPGA through a bus interface. The microprocessing module implements key derivation, resource processing, and control of algorithm modules.

[0010] The binary files of the algorithm module and the microprocessing module have a one-to-one correspondence and are stored in the FLASH.

[0011] After the management software is started, it reads the binary file of the algorithm module from the FLASH and sends the algorithm module to the FPGA framework software through the bus interface. The FPGA framework software loads and runs it. At the same time, the microprocessing module is started by calling the corresponding interfaces of the operating system. The microprocessing module runs independently in the system as a process. The management software controls the process priority of the microprocessing module according to actual application requirements. The management software conducts data interaction with the microprocessing module and the FPGA communication module. The port number of the microprocessing module is uniformly assigned by the management software and is converted into a string and passed into main(int argc,char **argv) at startup. argc points to the number of incoming parameters, and argv[1] points to the string of the incoming parameter of the microprocessing module port number.

[0012] Further, the algorithm module is stored in the form of a binary bin file.

[0013] Further, the microprocessing module is stored in the form of an elf executable program.

[0014] Further, the management software can load multiple microprocessing modules at a time and implement socket communication with different microprocessing modules through different port numbers.

[0015] Further, the FPGA algorithm module software conducts data interaction of management-type resources with the FPGA framework software. The management-type resource data includes: cryptographic algorithm parameters, keys, random numbers, and algorithm states.

[0016] Further, the microprocessing module is also used for reporting status and reporting self-check results.

[0017] Further, the FPGA framework software receives external data and sends it to the algorithm module for encryption and decryption operations.

[0018] Further, the management software conducts data interaction with the microprocessing module and the FPGA communication module through a socket of the AF-INET domain UDP protocol.

[0019] The present invention also provides an encryption and decryption method, which includes the following steps:

[0020] Step 1: The FPGA framework software is started, the management software is started and reads the binary file of the algorithm module from the FLASH and sends it to the FPGA framework software through the bus interface. The FPGA framework software receives and loads the algorithm module.

[0021] Step 2: The management software creates a socket socket, loads the microprocessing module in a process manner, and passes the port number as a loading parameter. The microprocessing module runs independently and waits to receive configuration information.

[0022] Step 3: The management software sends password resources to the microprocessing module through the socket interface. The microprocessing module receives the password resources for derivation and encapsulation processing, and sends the processed data to the management software through the socket. The management software sends it to the FPGA framework software through the FPGA communication module. After receiving it, the FPGA framework software passes it to the algorithm module, and the algorithm module performs algorithm self-checking.

[0023] Step 4: The algorithm module passes the algorithm self-checking data to the FPGA framework software. The FPGA framework software sends it to the management software through the bus interface. The management software passes the self-checking data to the microprocessing module. The microprocessing module compares the self-checking data, obtains the algorithm self-checking result and reports it to the management software.

[0024] Step 5: The management software sends an algorithm module start instruction to the microprocessing module. The microprocessing module encapsulates the instruction and sends it to the FPGA communication module. The FPGA communication module forwards it to the FPGA framework software. After receiving the start instruction, the FPGA framework software starts to work, receives external encryption and decryption data and inputs it into the FPGA algorithm module for operation.

[0025] Further, the password resources in Step 3 include: algorithm parameters and keys.

[0026] (III) Beneficial effects

[0027] The present invention proposes a modular data encryption and decryption system and method. The present invention proposes a modular data encryption and decryption system, which realizes the encryption and decryption of various types of data by using multiple algorithms. By adopting a modular design concept, the separation of calculation and management is realized, and the problems of hardware repeated design and repeated replacement in multiple applications are solved; through the cross-platform compilation and operation characteristics of the microprocessing module, it is realized that a microprocessing module can run on multiple hardware platforms, and multiple microprocessing modules can run on one hardware platform, solving the constraints and bottlenecks brought by the traditional mode; by adopting standard socket interface API communication and high-speed bus communication, a data encryption and decryption system with strong scalability and high standardization is formed. Description of the drawings

[0028] Figure 1 This is the logical architecture of the data encryption and decryption system of the present invention;

[0029] Figure 2 This is the internal data flow diagram of the system;

[0030] Figure 3 This is the operation process of the management software. Specific embodiments

[0031] To make the objectives, content and advantages of the present invention clearer, the following further describes in detail the specific embodiments of the present invention with reference to the accompanying drawings and embodiments.

[0032] The technical problem to be solved by the present invention is how to provide a modular data encryption and decryption system and method, which shields the differences between the operating system and the cryptographic machine hardware platform, realizes the separation of management and calculation, enables a cryptographic application module to run on multiple hardware platforms, and enables a hardware platform to run multiple cryptographic application modules.

[0033] The present invention relates to a modular encryption and decryption cryptographic machine architecture, belonging to the field of computer cryptography. The present invention adopts the modular encryption and decryption architecture, which runs on a system-on-chip processor and an FPGA respectively. Through the decoupled design and collaborative work of the management software and the microprocessor module software on the system-on-chip, the decoupling of cryptographic processing and the underlying hardware is realized, and the problems of repeated design and repeated replacement of cryptographic application modules are solved; the FPGA architecture adopts the method of embedding multiple algorithm modules, and the microprocessor module corresponds to the FPGA algorithm module one by one, solving the problem that a cryptographic application module can run on multiple hardware platforms and a hardware platform can run multiple cryptographic application modules. The management software communicates with the microprocessor module by adopting the internal standard socket method of the system and communicates with the FPGA by adopting the bus method, realizing the standardization and platformization of different microprocessor modules and different cryptographic modules, and completing functions such as the scheduling of cryptographic microprocessor modules and the unified management of cryptographic resources.

[0034] To solve the above technical problems, the present invention proposes a modular data encryption and decryption system, which includes a system-on-chip processor, an FPGA chip and a non-volatile memory. The system-on-chip processor includes a microprocessor module and management software; the FPGA chip includes an algorithm module and FPGA framework software; the microprocessor module resources are stored on the non-volatile storage medium.

[0035] The cryptographic application module is installed on the cryptographic machine hardware platform in the form of module software to realize the encryption and decryption function of a certain service. The module software is generally divided into an algorithm module and a microprocessor module, and the two are in a one-to-one correspondence relationship. Through the modular implementation method, it is realized that a cryptographic application module can run on multiple hardware platforms and a hardware platform can run multiple cryptographic application modules.

[0036] The software on the FPGA chip includes the FPGA framework software and algorithm modules. The FPGA framework software is responsible for providing all external interfaces, internal interconnection buses, peripheral calls, clock reset resources, underlying protocol parsing and other functions, and providing services for the FPGA algorithm modules. The algorithm modules implement functions such as specific business data cipher protocol parsing and cipher algorithm implementation. The FPGA framework software and the algorithm modules interact through the FPGA module interface protocol.

[0037] The real-time operating system runs on the processor chip. The software on the processor chip includes management software and microprocessing modules. The management software is mainly used for module loading, overall scheduling of system processes, and management of cipher resources, including a resource management module, a system control module, and an FPGA communication module. The FPGA communication module is used to receive data from the microprocessing module and send it to the FPGA through the bus interface. The microprocessing module implements key derivation, resource processing, and control of the FPGA algorithm module.

[0038] The cipher application modules are uniformly stored in the FLASH. The algorithm modules are stored in the form of binary bin files, and the microprocessing modules are stored in the form of elf executable programs. After the management software is started, it reads the binary file of the FPGA algorithm module from the FLASH and sends the FPGA algorithm module to the FPGA framework software through the bus interface. The FPGA framework software loads and runs it. At the same time, the microprocessing module is started by calling the corresponding interfaces of the operating system (such as posix_spawnp). The microprocessing module runs independently in the system as a process. The management software can control the process priority of the microprocessing module according to actual application requirements. The management software conducts data interaction with the microprocessing module and the FPGA communication module through the UDP protocol socket in the AF-INET domain. The port number of the microprocessing module is uniformly assigned by the management software and is converted into a string and passed into main(int argc,char **argv) at startup. argc points to the number of passed-in parameters, and argv[1] points to the string of the passed-in parameter of the microprocessing module port number.

[0039] Furthermore, the management software can load multiple microprocessing modules at one time and implement socket communication with different microprocessing modules through different port numbers;

[0040] Furthermore, the FPGA algorithm module software and the FPGA framework software will conduct interactive management of resource data such as cipher algorithm parameters, keys, random numbers, and algorithm states;

[0041] Furthermore, the microprocessing module can implement status reporting and self-check result reporting;

[0042] Further, the FPGA framework software receives external data and sends it to the algorithm module for encryption and decryption operations.

[0043] The present invention also provides a method for using a cryptographic machine for encryption and decryption based on the above system. This method is used for encryption and decryption of multiple services and algorithms, and includes the following steps:

[0044] Step 1: The FPGA framework software starts, the management software starts and reads the algorithm module binary file from the FLASH and sends it to the FPGA framework software through the bus interface. The FPGA framework software receives and loads the algorithm module.

[0045] Step 2: The management software creates a socket socket, loads the microprocessing module in a process manner, and passes the port number as a loading parameter. The microprocessing module runs independently and waits to receive configuration information.

[0046] Step 3: The management software sends cryptographic resources such as algorithm parameters and keys to the microprocessing module through the socket interface. The microprocessing module receives the cryptographic resources and performs processes such as derivation and encapsulation, and sends the processed data to the management software through the socket. The management software sends it to the FPGA framework software through the FPGA communication module. After receiving it, the FPGA framework software passes it to the algorithm module, and the algorithm module performs algorithm self-checking.

[0047] Step 4: The algorithm module passes the algorithm self-check data to the FPGA framework software. The FPGA framework software sends it to the management software through the bus interface. The management software passes the self-check data to the microprocessing module. The microprocessing module compares the self-check data, obtains the algorithm self-check result, and reports it to the management software.

[0048] Step 5: The management software sends an algorithm module start instruction to the microprocessing module. The microprocessing module encapsulates the instruction and sends it to the FPGA communication module. The FPGA communication module forwards it to the FPGA framework software. After receiving the start instruction, the FPGA framework software starts to work, receives external encryption and decryption data input into the FPGA algorithm module for operation. Embodiment

[0049] Figure 1 It is a schematic diagram of the logical structure of the data encryption and decryption system of the present invention. The system includes a microprocessing module, an algorithm module, microprocessing module resource management, a cryptographic processor chip, a management software, an FPGA processor chip, FPGA software, and a FLASH storage medium.

[0050] The microprocessor module is an executable program file that can run on the CPU's corresponding operating system. The software source code has the characteristics of cross-platform compilation and operation of the source code. It uses a set of "interface API functions that are independent of the management software" to achieve communication with the FPGA algorithm module through the FPGA communication module, and interact with other modules on the processor. The microprocessor module is decoupled from the management software, shielding the differences between the operating system and the cryptographic machine hardware platform.

[0051] The management software is the control core of the entire system. After the system is powered on, the management software runs. According to the actual application scenario, the microprocessor module is loaded by creating a process, and the algorithm module is transmitted to the FPGA through the interface to realize the dynamic reconstruction of the algorithm module. The management software and the microprocessor module run on the processor as independent processes and communicate through sockets.

[0052] The FLASH storage medium stores password resources and binary files of multiple modules, and protects key data from being lost by leveraging the power-off protection capability of non-volatile RAM.

[0053] The framework software runs on the FPGA processor chip. The framework software receives the algorithm module transmitted by the management software, loads it dynamically, and parses the transmitted data according to the protocol and sends it to the algorithm module for encryption and decryption. The FPGA algorithm module provides a unified external interface and supports dynamic reconfiguration.

[0054] Figure 2 It is the data flow within the system. Figure 3 It is the operation process of the management software.

[0055] Step 1: The FPGA framework software is started, the management software is started, the algorithm module is read from the FLASH and sent to the FPGA framework software through the bus interface, and the FPGA framework software receives and loads the algorithm module;

[0056] Step 2: The management software creates a socket, loads the microprocessor module through a process, and passes in the port number as a loading parameter. The microprocessor module runs alone and waits to receive configuration information.

[0057] Step 3: The management software sends algorithm parameters, keys and other cryptographic resources to the microprocessor module through the socket interface. The microprocessor module receives the cryptographic resources for derivation, encapsulation and other processing, and sends the processed data to the management software through the socket. The management software sends it to the FPGA framework software through the FPGA communication module. After receiving it, the FPGA framework software passes it to the algorithm module, and the algorithm module performs algorithm self-check.

[0058] Step 4: The algorithm module transfers the algorithm self-check data to the FPGA framework software, which sends it to the management software through the bus interface. The management software transfers the self-check data to the microprocessing module, which compares the self-check data, obtains the algorithm self-check result, and reports it to the management software.

[0059] Step 5: The management software sends an algorithm module start instruction to the microprocessing module. The microprocessing module encapsulates the instruction and sends it to the FPGA communication module, which forwards it to the FPGA framework software. After receiving the start instruction, the FPGA framework software starts to work, receives external encryption and decryption data, and inputs it into the FPGA algorithm module for operation.

[0060] By adopting the modular data encryption and decryption system of the present invention, the encryption and decryption of various types of data are realized by using multiple algorithms. Through the modular design concept, the separation of calculation and management is achieved, and the problems of hardware duplicate design and duplicate replacement in multiple applications are solved; through the cross-platform compilation and operation characteristics of the microprocessing module, a microprocessing module can run on multiple hardware platforms, and multiple microprocessing modules can run on one hardware platform, solving the constraints and bottlenecks brought by the traditional mode; by adopting the standard socket interface API communication and high-speed bus communication, a data encryption and decryption system with strong scalability and high standardization is formed. Embodiment

[0061] A software-defined modular data encryption and decryption system, which includes a system-on-chip, an FPGA chip, and a non-volatile memory. The system-level processor chip includes a microprocessing module and a management software; the FPGA chip includes an algorithm module and an FPGA framework software; the microprocessing module resources are stored on the non-volatile storage medium;

[0062] The cryptographic application module is installed on the cryptographic machine hardware platform in the form of module software to implement the encryption and decryption functions of a certain service. The module software is generally divided into an FPGA algorithm module and a processor microprocessing module. Through the modular implementation method, a cryptographic application module can run on multiple hardware platforms, and multiple cryptographic application modules can run on one hardware platform;

[0063] The FPGA software includes an FPGA framework software and an FPGA algorithm module. The FPGA framework software is responsible for providing all external interfaces, internal interconnection buses, peripheral calls, clock reset resources, underlying protocol parsing and other functions, and providing services for the FPGA algorithm module. The FPGA algorithm module implements functions such as specific service data cryptographic protocol parsing and cryptographic algorithm implementation. The FPGA framework software and the FPGA algorithm module interact through the FPGA module interface protocol;

[0064] The real-time operating system runs on the CPU chip. The CPU software includes management software and processor microprocessing module software. The management software is used for module loading, overall scheduling of system processes, and management of cryptographic resources, including a resource management module, a system control module, and an FPGA communication module. The FPGA communication module is used to receive data from the microprocessing module and send it to the FPGA through the bus interface; the microprocessing module implements key derivation, resource processing, and control of the FPGA algorithm module.

[0065] Furthermore, the management software can load multiple microprocessing modules at one time and achieve socket communication with different microprocessing modules through different port numbers;

[0066] Furthermore, the FPGA framework software can dynamically reconstruct multiple algorithm modules. The microprocessing module corresponds to the algorithm module one by one. The microprocessing module can report the state of the algorithm module and the self-check result;

[0067] Furthermore, the FPGA algorithm module software and the FPGA framework software will interact with management resource data such as cryptographic algorithm parameters, keys, random numbers, and algorithm states;

[0068] Furthermore, the cryptographic application modules are uniformly stored in the FLASH. After the management software is started, the FPGA algorithm module and the microprocessing module are respectively read from the FLASH, and the FPGA algorithm module is sent to the FPGA framework software through the bus interface. The FPGA framework software loads and runs it. At the same time, the microprocessing module is started by calling the corresponding interface of the operating system (such as posix_spawnp). The microprocessing module runs independently in the system as a process. The management software can control the process priority of the microprocessing module according to actual application requirements. The management software conducts data interaction with the microprocessing module and the FPGA communication module through the AF-INET domain UDP protocol socket (socket). The port number of the microprocessing module is uniformly allocated by the management software and converted into a string and passed into main(int argc,char **argv) at startup. argv[1] points to the string of the microprocessing module port number.

[0069] Furthermore, the startup and interaction process of the software includes the following steps:

[0070] Step 1: The FPGA framework software is started. The management software is started and reads the algorithm module from the FLASH and sends it to the FPGA framework software through the bus interface. The FPGA framework software receives and loads the algorithm module;

[0071] Step 2: The management software creates a socket socket, loads the microprocessing module in a process manner, and passes the port number as a loading parameter. The microprocessing module runs independently and waits to receive configuration information;

[0072] Step 3: The management software sends cryptographic resources such as algorithm parameters and keys to the microprocessing module through the socket interface. The microprocessing module receives the cryptographic resources and performs processes such as derivation and encapsulation, and sends the processed data to the management software through the socket. The management software sends it to the FPGA framework software through the FPGA communication module. After receiving it, the FPGA framework software passes it to the algorithm module, and the algorithm module performs algorithm self-checking;

[0073] Step 4: The algorithm module passes the algorithm self-check data to the FPGA framework software. The FPGA framework software sends it to the management software through the bus interface. The management software passes the self-check data to the microprocessing module. The microprocessing module compares the self-check data, obtains the algorithm self-check result, and reports it to the management software;

[0074] Step 5: The management software sends an algorithm module start instruction to the microprocessing module. The microprocessing module encapsulates the instruction and sends it to the FPGA communication module. The FPGA communication module forwards it to the FPGA framework software. After receiving the start instruction, the FPGA framework software starts to work and receives external encryption and decryption data and inputs it into the FPGA algorithm module for operation.

[0075] The present invention proposes a modular data encryption and decryption system, which realizes the encryption and decryption of various types of data using multiple algorithms. By adopting a modular design concept, the separation of calculation and management is realized, and the problems of hardware duplicate design and duplicate replacement in multiple applications are solved; through the cross-platform compilation and operation characteristics of the microprocessing module, a microprocessing module can run on multiple hardware platforms, and multiple microprocessing modules can run on one hardware platform, solving the constraints and bottlenecks brought by the traditional mode; by adopting standard socket interface API communication and high-speed bus communication, a data encryption and decryption system with strong scalability and high standardization is formed.

[0076] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and deformations can be made, and these improvements and deformations should also be regarded as the protection scope of the present invention.

Claims

1. A modular data encryption and decryption system, characterized in that The system includes a system-level processor chip, an FPGA chip and a non-volatile memory. The system-level processor chip includes a microprocessing module and management software, and the FPGA chip includes an algorithm module and FPGA framework software. The microprocessing module resources are stored on the non-volatile storage medium. The software on the FPGA chip includes FPGA framework software and algorithm modules; the FPGA framework software is responsible for providing all external interfaces, internal interconnection buses, peripheral calls, clock reset resources, and underlying protocol parsing functions to provide services for the FPGA algorithm module; the algorithm module implements specific business data cryptographic protocol parsing and cryptographic algorithm implementation; the FPGA framework software and the algorithm module interact through the FPGA module interface protocol; The processor chip runs a real-time operating system. The software on the processor chip includes management software and microprocessor modules. The management software is used for module loading, overall scheduling of system processes, and management of cryptographic resources. It includes resource management modules, system control modules, and FPGA communication modules. The FPGA communication module is used to receive data from the microprocessor module and send it to the FPGA through the bus interface. The microprocessor module realizes key derivation, resource processing, and algorithm module control. The binary files of the algorithm module and the microprocessor module are in one-to-one correspondence and are stored in FLASH; After the management software is started, it reads the binary file of the algorithm module from the FLASH and sends the algorithm module to the FPGA framework software through the bus interface. The FPGA framework software loads and runs it. At the same time, it starts executing the microprocessor module by calling the corresponding interface of the operating system. The microprocessor module runs independently in the system as a process. The management software controls the process priority of the microprocessor module according to actual application requirements. The management software exchanges data with the microprocessor module and the FPGA communication module. The port number of the microprocessor module is uniformly allocated by the management software and converted into a string when it is started and passed into main (int argc, char **argv). argc points to the number of passed parameters, and argv[1] points to the passed parameter microprocessor module port number string.

2. The modular data encryption and decryption system according to claim 1, wherein The algorithm module is stored in binary bin file format.

3. The modular data encryption and decryption system according to claim 1, characterized in that, The microprocessor module is stored in the form of an elf executable program.

4. The modular data encryption and decryption system according to claim 1, characterized in that, The management software can load multiple microprocessor modules at one time and implement socket communication with different microprocessor modules through different port numbers.

5. The modular data encryption and decryption system according to claim 1, characterized in that, The FPGA algorithm module software interacts with the FPGA framework software to manage resource data, which includes: cryptographic algorithm parameters, keys, random numbers, and algorithm status.

6. The modular data encryption and decryption system according to claim 1, characterized in that, The microprocessor module is also used to report status and self-test results.

7. The modular data encryption and decryption system according to claim 1, wherein The FPGA framework software receives external data and sends it to the algorithm module for encryption and decryption operations.

8. The modular data encryption and decryption system according to claim 1, wherein The management software exchanges data with the microprocessor module and the FPGA communication module through the AF-INET domain UDP protocol socket.

9. A decryption and encryption method for a modular data decryption and encryption system according to any one of claims 1-8, characterized in that, The method comprises the following steps: Step 1: The FPGA framework software starts, the management software starts and reads the algorithm module binary file from the FLASH and sends it to the FPGA framework software through the bus interface. The FPGA framework software receives and loads the algorithm module; Step 2: The management software creates a socket socket, loads the microprocessing module in a process mode, and passes the port number as a loading parameter. The microprocessing module runs independently and waits to receive configuration information; Step 3: The management software sends password resources to the microprocessing module through the socket interface. The microprocessing module receives the password resources for derivation and encapsulation processing, and sends the processed data to the management software through the socket. The management software sends it to the FPGA framework software through the FPGA communication module. After receiving it, the FPGA framework software passes it to the algorithm module, and the algorithm module performs algorithm self-checking; Step 4: The algorithm module passes the algorithm self-check data to the FPGA framework software. The FPGA framework software sends it to the management software through the bus interface. The management software passes the self-check data to the microprocessing module. The microprocessing module compares the self-check data, obtains the algorithm self-check result and reports it to the management software; Step 5: The management software sends an algorithm module start instruction to the microprocessing module. The microprocessing module encapsulates the instruction and sends it to the FPGA communication module. The FPGA communication module forwards it to the FPGA framework software. After receiving the start instruction, the FPGA framework software starts to work, receives external encryption and decryption data and inputs it into the FPGA algorithm module for operation.

10. The method according to claim 9, wherein The password resources in Step 3 include: algorithm parameters and keys.

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