Formation method of semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure. The method comprises the following steps: providing a substrate; etching the substrate by adopting a first reactive ion beam etching process, and forming an initial shallow trench in the substrate; the surface of the initial shallow trench is etched through at least one second reactive ion beam etching process, a shallow trench is formed, and the surface roughness of the shallow trench is smaller than that of the initial shallow trench; the method comprises the following steps of: firstly, drawing the shape of an initial shallow trench by using a first reactive ion etching process, and then etching the surface of the initial shallow trench by using a second reactive ion beam etching process at least once, so that the problems of rough surface, bottom interface damage and load effect of the initial shallow trench in the etching process are solved in a balanced manner; the interface etching performance of the finally formed shallow trench is improved, the electrical performance of the semiconductor structure is optimized, and the application range is wide.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] With the continuous improvement of integration, the processing line width is getting smaller and smaller. Stable and good device performance poses a huge challenge to the etching process. The line width determines the gate size of the MOS, and the etching profile directly affects the electrical performance of the device. Undoubtedly, higher requirements are put forward for shallow trench etching itself, such as smooth surface and interface, no ion damage, no loading effect, etc. Unfortunately, for advanced process shallow trench etching, the current traditional ICP (Inductively Coupled Plasma) etching process has not yet had a complete solution to meet all process requirements and achieve high-etching-performance shallow trench etching.

[0003] However, the surface and interface conditions of the shallow trench, including roughness and ion damage, will directly affect the performance of the subsequent fins: specifically, for example, 1) it causes different effective heights of the fins, resulting in differences in uniformity, conductivity, and carrier mobility, and suppressing the yield; 2) the rough undulation of the trench surface and interface suppresses the process window of the device and limits the chip density; 3) it affects the subsequent germanium-silicon epitaxial growth and generates epitaxial defects; 4) it affects the sidewall angle, affects the filling effect of the subsequent dielectric, causes coating undulation, and results in leakage failure; 5) it causes feature size differences. Generally speaking, it causes electrical differences and suppresses the final electrical performance of the device.

[0004] Therefore, how to achieve a smooth surface and interface of the shallow trench, no ion damage, control the removal of polymers, and no loading effect is a technical problem that urgently needs to be solved at present. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which eliminates the surface roughness of the shallow trench, reduces the damage to the bottom interface, and the loading effect, improves the etching performance, and optimizes the electrical performance of the device.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; etching the substrate by using a first reactive ion beam etching process to form an initial shallow trench in the substrate; etching the surface of the initial shallow trench by using at least one second reactive ion beam etching process to form a shallow trench, wherein the surface roughness of the shallow trench is less than that of the initial shallow trench, and the lattice damage on the bottom surface of the shallow trench is less than that on the bottom surface of the initial shallow trench.

[0007] Optionally, the aspect ratio of the initial shallow trench is less than 5:1.

[0008] Optionally, the surface roughness of the shallow trench is less than 10 Å, and the thickness of the lattice damage of the shallow trench is less than 5 Å.

[0009] Optionally, before etching the substrate using the first reactive ion beam etching process, a mask layer is further formed on the surface of the substrate, and the substrate is etched using the mask layer as a mask.

[0010] Optionally, the mask layer includes an oxide layer on the surface of the substrate, an organic bottom structure layer on the surface of the oxide layer, a bottom anti-reflection coating on the surface of the organic bottom structure layer, and a photoresist layer on the surface of the bottom anti-reflection layer; or the mask layer includes an oxide layer on the surface of the substrate, a carbon silicon oxide layer on the surface of the oxide layer, a dielectric anti-reflection layer on the surface of the carbon silicon oxide layer, and a photoresist layer on the surface of the dielectric anti-reflection layer.

[0011] Optionally, the mask layer includes an oxide layer on the surface of the substrate, a hard mask layer on the surface of the oxide layer, an organic bottom structure layer on the surface of the hard mask layer, a bottom anti-reflection coating on the surface of the organic bottom structure layer, and a photoresist layer on the surface of the bottom anti-reflection layer; or the mask layer includes an oxide layer on the surface of the substrate, a hard mask layer on the surface of the oxide layer, a tetraethyl orthosilicate layer on the surface of the hard mask layer, a carbon silicon oxide layer on the surface of the tetraethyl orthosilicate layer, a bottom anti-reflection coating on the surface of the carbon silicon oxide layer, and a photoresist layer on the surface of the bottom anti-reflection layer; or the mask layer includes a hard mask layer on the surface of the substrate, an oxide layer on the surface of the hard mask layer, a carbon silicon oxide layer on the surface of the oxide layer, a dielectric anti-reflection layer on the surface of the carbon silicon oxide layer, and a photoresist layer on the surface of the dielectric anti-reflection layer.

[0012] Optionally, the included angle between the incident direction of the ion beam in the first reactive ion beam etching method and the normal line of the substrate ranges from 0° to 10°.

[0013] Optionally, the etching gas in the first reactive ion beam etching process includes a mixed gas of a physical gas and a chemical gas; the physical gas uses an inert gas; the chemical gas uses one or more of a fluorine-based gas and a chlorine-based gas.

[0014] Optionally, the range of the screen grid voltage in the first reactive ion beam etching process is 200V - 1000V, the range of the screen grid current is 0.1A - 1A, and the range of the ion acceleration bias voltage is 100ACV - 1000ACV.

[0015] Optionally, in the first reactive ion beam etching process, the etching chamber pressure ranges from 0.05 mT to 5 mT, the total gas flow rate ranges from 10 sccm to 100 sccm, and the etching time ranges from 50 s to 1000 s.

[0016] Optionally, in the second reactive ion beam etching process, the screen grid voltage ranges from 50 V to 400 V, the screen grid current ranges from 0.05 A to 0.3 A, and the ion acceleration bias voltage ranges from 100 ACV to 1000 ACV.

[0017] Optionally, the angle between the incident direction of the ion beam and the normal of the substrate in the second reactive ion beam etching process ranges from 0° to 80°.

[0018] Optionally, in the second reactive ion beam etching process, the etching chamber pressure ranges from 0.05 mT to 5 mT, the total gas flow rate ranges from 10 sccm to 50 sccm, and the etching time ranges from 60 s to 300 s.

[0019] Optionally, the etching gas in the second reactive ion beam etching process is one or a combination of inert gases, fluorine-based gases, and chlorine-based gases.

[0020] Optionally, the fluorine-based gas includes C x F y , where x and y are positive integers, and one or a combination of NF3, SF6, WF6, CHF3, and CH2F2.

[0021] Optionally, the chlorine-based gas includes one or a combination of Cl2, BCl3, CCl4, and SiCl4.

[0022] Optionally, after forming the shallow trench, an epitaxial layer is further formed in the shallow trench.

[0023] Optionally, after forming the epitaxial layer, the epitaxial layer is further etched to form a plurality of fin portions arranged discretely.

[0024] Optionally, the material of the epitaxial layer includes germanium silicon and silicon.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] First, use the first reactive ion etching process to outline the morphology of the initial shallow trench. This process has a low loading effect, high polymer removal ability, reduces defect generation, thereby avoiding the need for additional wet cleaning steps, improving overall productivity, and reducing costs. Then, use at least one second reactive ion beam etching process to etch the surface of the initial shallow trench, evenly solving the problems of surface roughness, underlying lattice damage, and loading effect during the etching of the initial shallow trench, improving the interface etching performance of the finally formed shallow trench, avoiding fluctuations in the effective height of the Fin, being beneficial to subsequent thin film epitaxial growth, improving carrier mobility and stability, optimizing the electrical performance of the semiconductor structure, and having a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 5 Schematic diagrams of the structures of the steps in the method for forming a semiconductor structure according to the first embodiment of the present invention;

[0028] Figures 6 to 10 Schematic diagrams of the structures of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] As described in the background art, the performance of existing semiconductor structures is poor. In the advanced Fin-FET process, silicon-based shallow trench etching is based on traditional ICP processes and there is no complete solution that can simultaneously achieve smooth surface and interface of the shallow trench, no ion damage, control of polymer removal, no loading effect, etc.

[0030] On this basis, the present invention provides a method for forming a semiconductor structure. First, use the first reactive ion etching process to outline the morphology of the initial shallow trench, and then use at least one second reactive ion beam etching process to etch the surface of the initial shallow trench, evenly solving the problems of surface roughness, underlying interface damage, and loading effect during the etching of the shallow trench, improving the interface etching performance of the shallow trench, optimizing the electrical performance of the semiconductor structure, and having a wide range of applications.

[0031] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0032] First Embodiment

[0033] Please refer to Figure 1 , and first provide a substrate 100.

[0034] In this embodiment, the material of the substrate 100 is silicon.

[0035] In other embodiments, the material of the substrate 100 may also be silicon germanium, etc.

[0036] In this embodiment, a mask layer 105 is formed on the surface of the substrate 100.

[0037] In this embodiment, the mask layer 105 includes an oxide layer 101 on the surface of the substrate 100, a silicon oxycarbide layer 102 on the surface of the oxide layer 101, a dielectric antireflection layer 103 on the surface of the silicon oxycarbide layer 102, and a photoresist layer 104 on the surface of the dielectric antireflection layer 103.

[0038] In this embodiment, a patterned layer opening 104a is formed in the photoresist layer 104.

[0039] In other embodiments, the mask layer may further include an oxide layer on the surface of the substrate, an organic bottom structure layer on the surface of the oxide layer, a bottom antireflection coating on the surface of the organic bottom structure layer, and a photoresist layer on the surface of the bottom antireflection layer; or the mask layer includes an oxide layer on the surface of the substrate, a hard mask layer on the surface of the oxide layer, an organic bottom structure layer on the surface of the hard mask layer, a bottom antireflection coating on the surface of the organic bottom structure layer, and a photoresist layer on the surface of the bottom antireflection layer; or the mask layer includes an oxide layer on the surface of the substrate, a hard mask layer on the surface of the oxide layer, a tetraethyl orthosilicate layer on the surface of the hard mask layer, a silicon oxycarbide layer on the surface of the tetraethyl orthosilicate layer, a bottom antireflection coating on the surface of the silicon oxycarbide layer, and a photoresist layer on the surface of the bottom antireflection layer; or the mask layer includes a hard mask layer on the surface of the substrate, an oxide layer on the surface of the hard mask layer, a silicon oxycarbide layer on the surface of the oxide layer, a dielectric antireflection layer on the surface of the silicon oxycarbide layer, and a photoresist layer on the surface of the dielectric antireflection layer.

[0040] Please refer to Figure 2 , and the substrate 100 is etched using a first reactive ion beam etching process to form an initial shallow trench 106 in the substrate 100.

[0041] In this embodiment, after forming the initial shallow trench 106, the dielectric antireflection layer 103 and the photoresist layer 104 are removed.

[0042] Among them, the aspect ratio of the initial shallow trench 106 is less than 5:1. The aspect ratio of the initial shallow trench 106 has an impact on the subsequent etching and modification of the surface of the initial shallow trench 106 using the second reactive ion beam etching process. This is because during the etching process, the initial shallow trenches 106 of different sizes are prone to causing loading, resulting in depth differences. After the reactive radical groups enter the initial shallow trench 106, polymers are formed with the etching by-products. In the initial shallow trench 106 with a small opening, the polymers are not easily carried away, hindering the subsequent etching reaction. In the initial shallow trench 106 with a large opening, the polymers are easily removed, and the charged particles have a charge effect, forming charge accumulation at the bottom of the initial shallow trench 106 to inhibit the continuous entry of subsequent reactive ions, further amplifying the etching performance at different sizes and forming a large depth difference. This affects the device performance accordingly.

[0043] Specifically, in this embodiment, the aspect ratio of the initial shallow trench 106 is 1:1. This aspect ratio ensures that the connection between the sidewall and the bottom of the initial shallow trench 106 is not too deep, avoiding the inability to etch the connection between the sidewall and the bottom of the initial shallow trench 106 during the second reactive ion beam etching process and improving the surface quality of the subsequent formed shallow trench; in addition, the depth and width of the initial shallow trench 106 are the same. At this time, the initial shallow trench 106 is relatively large, so that the etching effects on the bottom and sidewalls of the initial shallow trench 106 by the second reactive ion beam etching process are approximately the same, which can further eliminate the differences on the surface of the finally formed shallow trench.

[0044] Among them, in the first reactive ion beam etching process, the ion incident angle (the angle between the incident direction of the ion beam and the normal of the substrate 100) is an important parameter. The deposition energy distribution, mass redistribution effect, etc. of the incident ion beam are all related to the ion incident angle.

[0045] Among them, the angle range between the incident direction of the ion beam in the first reactive ion beam etching method and the normal of the substrate 100 is from 0° to 10°.

[0046] Specifically, in this embodiment, the angle between the incident direction of the ion beam in the first reactive ion beam etching method and the normal of the substrate 100 is 10°. The low angle realizes a steeper etching profile.

[0047] Among them, the etching gas in the first reactive ion beam etching process includes a mixed gas of physical gas and chemical gas; the physical gas uses an inert gas; the chemical gas uses one or more of fluorine-based gases and chlorine-based gases. The fluorine-based gas includes C x F y, x, and y are positive integers, and are one or more combinations of NF3, SF6, WF6, CHF3, and CH2F2. The chlorine-based gas includes one or more combinations of Cl2, BCl3, CCl4, and SiCl4.

[0048] Specifically, in this embodiment, the physical gas is an Ar inert gas, and the chemical gas is a chlorine-based gas, such as SF6. The chemical gas reacts with the etched substrate 100 to produce volatile products, while the physical gas enhances the stability of the plasma, improves the etching uniformity, and the Ar gas can enhance the ion bombardment effect to accurately define the initial shallow trench 106.

[0049] In this embodiment, by combining the physical gas and the chemical gas, the physical and chemical balance in the reaction chamber is adjusted to achieve the removal of physically assisted chemical polymers and the extraction of chemically assisted physical sputtering products. They coordinate with each other to control low etching by-products to achieve low load performance. The combined action of charge and polymer-assisted removal realizes the overall low load performance characteristics of shallow trench etching.

[0050] Among them, the range of the screen grid voltage in the first reactive ion beam etching process is 200V to 1000V, the range of the screen grid current is 0.1A to 1A, and the range of the ion acceleration bias voltage is 100ACV to 1000ACV.

[0051] Specifically, in this embodiment, the screen grid voltage in the first reactive ion beam etching process is 400V, the screen grid current is 0.3A, and the ion acceleration bias voltage is 600ACV.

[0052] Among them, in the first reactive ion beam etching process, the etching chamber pressure ranges from 0.05 mT to 5 mT, the total gas flow rate ranges from 10 sccm to 100 sccm, and the etching time ranges from 50 s to 1000 s; during the etching process, there is an obvious relationship between the reactive ion beam etching rate and the total gas flow rate. Among them, as the total gas flow rate range increases, the etching rate first rises. After reaching the maximum value, the etching rate slightly decreases at a relatively large flow rate. This is because, in the case of low flow rate, the etching rate is limited by the supply of active substances, while in the case of high flow rate, it is limited by the extraction of active substances. Therefore, the total etching gas flow rate cannot be too large; at the same time, the etching time cannot be too short, otherwise the etching effect is poor, the surface quality of the subsequent formed shallow trench is poor, and the etching time cannot be too long, otherwise over-etching will occur and the quality of the formed shallow trench is also not good; in addition, under low-pressure conditions, the mean free path of particles is very long, the directionality is good, and the ion bombardment effect is also strong. At the same time, low pressure is also conducive to the desorption of volatile etching products, and it is easy to obtain good etching results. The pressure has a great influence on the uniformity, and the uniformity is better when the pressure decreases. Therefore, low chamber pressure is beneficial to increasing the mean free path of molecules, improving ion collimation, and achieving a more uniform process modification.

[0053] Specifically, in this embodiment, in the first reactive ion beam etching process, the etching chamber pressure is 1 mT, the total gas flow rate is 30 sccm, and the etching time is 300 s.

[0054] Please refer to Figure 3 , the surface of the initial shallow trench 106 is etched by using at least one second reactive ion beam etching process to form a shallow trench 107, the surface roughness of the shallow trench 107 is less than the surface roughness of the initial shallow trench 106, and the lattice damage on the bottom surface of the shallow trench 107 is less than the lattice damage on the bottom surface of the initial shallow trench 106.

[0055] In this embodiment, at least one of the second reactive ion beam etching processes etches the surface of the initial shallow trench 106, evenly solving the problems of surface roughness, unevenness, bottom interface damage, and loading effect during the etching of the initial shallow trench 106, improving the interface etching performance of the finally formed shallow trench 107, and optimizing the electrical performance of the semiconductor structure, with a relatively wide range of applications.

[0056] Among them, the surface roughness of the shallow trench 107 is less than 10 Å, and the lattice damage thickness of the shallow trench 107 is less than 5 Å.

[0057] In this embodiment, the surface roughness of the shallow trench 107 is less than 10 angstroms, and the lattice damage thickness of the shallow trench 107 is less than 5 angstroms, which ensures the quality of the epitaxial layer formed in the shallow trench 107 subsequently, eliminates the defects of misalignment in the formation of the epitaxial layer, and avoids the deposition angle during the growth of the epitaxial layer, thereby affecting the stress transfer to the device channel and causing electrical expression.

[0058] Among them, the included angle range between the incident direction of the ion beam in the second reactive ion beam etching process and the normal line of the substrate 100 is 0° to 80°. If the included angle between the incident direction of the ion beam in the second reactive ion beam etching process and the normal line of the substrate 100 is greater than 80°, it will cause different ion beam energy distributions due to the too large included angle, resulting in the transformation of the surface of the initial shallow trench 106 from smooth to rough, which is not conducive to forming the shallow trench 107 with good surface quality.

[0059] Specifically, in this embodiment, the included angle between the incident direction of the ion beam in the second reactive ion beam etching process and the normal line of the substrate 100 is 0°.

[0060] Among them, the range of the screen grid voltage (ion energy) in the second reactive ion beam etching process is 50V to 400V, the range of the screen grid current (ion density) is 0.05A to 0.3A, and the range of the ion acceleration bias voltage is 100ACV to 1000ACV. The larger the screen grid voltage, the greater the impact energy of the ion beam on the etched substrate 100, and the higher the etching efficiency; however, the larger the screen grid voltage, due to the stronger thermal effect generated during the impact, the surface of the initial shallow trench 106 is damaged and deformed, thereby reducing the etching efficiency. The screen grid voltage cannot be too large or too small. Considering comprehensive factors, the range of the screen grid voltage (ion energy) in this embodiment is 50V to 400V.

[0061] During the etching process, the larger the screen grid current, the more ions, and the higher the etching efficiency. However, the larger the screen grid current, the more ions, which will increase the mutual collision and scattering between ion beams, thereby affecting the etching rate. Considering comprehensive factors, the range of the screen grid current (ion density) is 0.05A to 0.3A.

[0062] And the larger the ion acceleration bias voltage, the etching rate increases significantly. However, if the ion acceleration bias voltage is too large, it will cause the step morphology to deteriorate, which is not conducive to forming the shallow trench 107 with good surface quality. Considering comprehensively, the range of the ion acceleration bias voltage is 100ACV to 1000ACV.

[0063] Specifically, in this embodiment, in the second reactive ion beam etching process, the screen grid voltage is 100V, the screen grid current is 0.1A, and the ion acceleration bias voltage is 200ACV, which can not only ensure an appropriate etching rate but also ensure the quality of the etching interface.

[0064] Among them, the etching gas in the second reactive ion beam etching process is one or a combination of an inert gas, a fluorine-based gas, and a chlorine-based gas. The fluorine-based gas includes C x F y , where x and y are positive integers, and one or a combination of NF3, SF6, WF6, CHF3, and CH2F2. The chlorine-based gas includes one or a combination of Cl2, BCl3, CCl4, and SiCl4.

[0065] Specifically, in this embodiment, the etching gas in the second reactive ion beam etching process is a combination of the inert gas Ar and the fluorine-based gas CHF3.

[0066] Among them, the etching chamber pressure range in the second reactive ion beam etching process is 0.05mT to 5mT, the total gas flow rate range is 10sccm to 50sccm, and the etching time range is 60s to 300s.

[0067] Specifically, in this embodiment, in the second reactive ion beam etching process, the etching chamber pressure is 1mT, the total gas flow rate is 20sccm, and the etching time is 100s.

[0068] Please refer to Figure 4 , and an epitaxial layer 108 is formed in the shallow trench 107.

[0069] In this embodiment, the material of the epitaxial layer 108 is germanium silicon.

[0070] In other embodiments, the material of the epitaxial layer can also be silicon, etc.

[0071] In this embodiment, after multiple modifications of the second reactive ion beam etching process, the surface of the shallow trench 107 has good quality, thereby reducing the defects of the formed epitaxial layer, avoiding fluctuations in the effective height of the subsequent fins, improving device stability, improving the device process window, increasing the integration density, and improving the overall electrical performance.

[0072] Please refer to Figure 5 , and the epitaxial layer 108 is etched to form a plurality of discretely arranged fins 109.

[0073] In this embodiment, based on filling the shallow trench 107 with the high-quality epitaxial layer, back-end etching is performed to define high-carrier-mobility fins, improving the carrier mobility of the device and the device stability.

[0074] In this embodiment, after forming the initial shallow trench 106 with an aspect ratio of 1:1, based on the reactive ion beam etching equipment (RIBE), the sidewalls of the initial shallow trench 106 are modified, such as eliminating the loading effect, reducing the surface roughness of the initial shallow trench 106, and reducing lattice damage, to form the shallow trench 107 that meets the requirements. Then, during the IBE etching process, the energy of the ions, the ion density, the ion acceleration bias voltage, the etching time, and the incident angle of the ion beam are all selected and coordinated specifically, and they need to be closely linked.

[0075] Second Embodiment

[0076] The difference between the second embodiment and the first embodiment lies in the different structure of the mask layer 105, as well as the different parameters of the first reactive ion beam etching process and the second reactive ion beam etching process.

[0077] Please refer to Figure 6 , first, a substrate 200 is provided.

[0078] In this embodiment, the material of the substrate 200 is silicon, and a mask layer 201 is formed on the surface of the substrate 200.

[0079] In this embodiment, the mask layer 201 includes an oxide layer 202 located on the surface of the substrate 200, a hard mask layer 203 located on the surface of the oxide layer 202, an organic bottom structure layer 204 located on the surface of the hard mask layer 203, a bottom anti-reflection coating 205 located on the surface of the organic bottom structure layer 204, a photoresist layer 206 located on the surface of the bottom anti-reflection layer 205, and an opening 206a is formed in the photoresist 206.

[0080] Please refer to Figure 7 , and the substrate 200 is etched using the first reactive ion beam etching process to form an initial shallow trench 207 in the substrate 200.

[0081] In this embodiment, after forming the initial shallow trench 207, part of the mask layer is removed.

[0082] In this embodiment, the aspect ratio of the initial shallow trench 207 is 3:1. This aspect ratio ensures that the connection between the sidewall and the bottom of the initial shallow trench 207 is not too deep, avoiding the situation that the connection between the sidewall and the bottom of the initial shallow trench 207 cannot be etched during the second reactive ion beam etching process, and improving the surface quality of the subsequently formed shallow trench; in addition, the depth of the initial shallow trench 207 is greater than the width, and at this time, the initial shallow trench 207 is larger, so that the second reactive ion beam etching process can more easily act on the surfaces of the bottom and sidewalls of the initial shallow trench 207, improving the surface quality of the finally formed shallow trench.

[0083] In this embodiment, the angle between the incident direction of the ion beam in the first reactive ion beam etching method and the normal of the substrate 200 is 0°. A low angle enables a steeper etching profile, and the incident angle is adjustable according to the device structure.

[0084] In this embodiment, the physical gas is an inert gas Kr, and the chemical gas is a chlorine-based gas, such as CF4. The chemical gas reacts with the etched substrate 200 to produce volatile products, while the physical gas enhances the stability of the plasma, improves etching uniformity, and the Kr gas can enhance the ion bombardment effect to accurately define the initial shallow trench 207.

[0085] In this embodiment, in the first reactive ion beam etching process, the screen grid voltage is 300V, the screen grid current is 0.2A, and the ion acceleration bias voltage is 400ACV.

[0086] In this embodiment, in the first reactive ion beam etching process, the etching chamber pressure is 0.5mT, the total gas flow rate is 50sccm, and the etching time is 240s.

[0087] Please refer to Figure 8 , and at least one second reactive ion beam etching process is used to etch the surface of the initial shallow trench 207 to form a shallow trench 208, and the surface roughness of the shallow trench 208 is less than that of the initial shallow trench 207.

[0088] In this embodiment, at least one of the second reactive ion beam etching processes etches the surface of the initial shallow trench 106 to evenly solve the problems of surface roughness, bottom interface damage, and loading effect during the etching of the initial shallow trench 207, improve the interface etching performance of the finally formed shallow trench 208, optimize the electrical performance of the semiconductor structure, and has a wide range of applications.

[0089] Among them, the surface roughness of the shallow trench 208 is less than 10 Å, and the lattice damage thickness of the shallow trench 208 is less than 5 Å.

[0090] In this embodiment, the angle between the incident direction of the ion beam in the second reactive ion beam etching process and the normal of the substrate 100 is 10°.

[0091] In this embodiment, in the second reactive ion beam etching process, the screen grid voltage is 50V, the screen grid current is 0.05A, and the ion acceleration bias voltage is 400ACV. The low-energy process is beneficial to the control of sputtering products, the modification of surface roughness, and the repair of damage.

[0092] In this embodiment, the etching gas in the second reactive ion beam etching process uses a combination of an inert gas Ar and a fluorine-based gas CHF3. The etching chamber pressure in the second reactive ion beam etching process is 0.5 mT, the total gas flow rate is 20 sccm, and the etching time is 60 s. A low chamber pressure is beneficial to increasing the mean free path of molecules, improving ion collimation, and achieving a more uniform process modification. The etching time is adjusted according to the surface roughness fluctuations and damage conditions of the surface interface. The core principle is to efficiently remove the surface interface fluctuations and simultaneously remove the damaged layer.

[0093] Please refer to Figure 9 , and an epitaxial layer 209 is formed in the shallow trench 208.

[0094] In this embodiment, the material of the epitaxial layer 209 is germanium silicon.

[0095] In other embodiments, the material of the epitaxial layer 209 can also be silicon or the like.

[0096] In this embodiment, after multiple modifications of the second reactive ion beam etching process, the surface of the shallow trench 208 has good quality, thereby reducing the defects of the formed epitaxial layer, avoiding fluctuations in the effective height of the subsequent fins, improving device stability, improving the device process window, increasing the integration density, and improving the overall electrical performance.

[0097] Please refer to Figure 10 , and the epitaxial layer 209 is etched to form a plurality of discretely arranged fins 210.

[0098] In this embodiment, based on filling the shallow trench 208 with the high-quality epitaxial layer 209, back-end etching is performed to define high-carrier-mobility fins 210, improving the carrier mobility of the device and the device stability.

[0099] In this embodiment, the aspect ratio (3:1) of the initial shallow trench is greater than the aspect ratio (1:1) of the initial shallow trench in the first embodiment. Then, during the etching process, since the depth of the initial shallow trench increases, the incident angle of the ion beam in this embodiment will become smaller to 0°, while the incident angle of the ion beam in the first embodiment is 10°. At this time, the etched morphology becomes steeper. Then, the ion energy, ion density, ion acceleration bias voltage, and the flow rate of the etching gas provided in this embodiment will be smaller than those in the first embodiment because the incident angle of the ion beam becomes smaller. At this time, if the etching force of the ion beam is too large, the steeper the etched morphology, the more likely it is to cause over-etching. Therefore, based on the aspect ratio of the initial shallow trench and the decrease in the incident angle of the ion beam, the required ion energy, ion density, ion acceleration bias voltage, chamber pressure, and the flow rate of the etching gas are reasonably selected to form the shallow trench that meets the requirements, which has a wide range of applications.

[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Etching the substrate by using a first reactive ion beam etching process to form an initial shallow trench in the substrate; Etching the surface of the initial shallow trench by using at least one second reactive ion beam etching process to form a shallow trench, wherein the surface roughness of the shallow trench is less than that of the initial shallow trench, and the lattice damage on the bottom surface of the shallow trench is less than that on the bottom surface of the initial shallow trench.

2. The method for forming a semiconductor structure according to claim 1, wherein The aspect ratio of the initial shallow trench is less than 5:

1.

3. The method for forming a semiconductor structure according to claim 1, wherein, The surface roughness of the shallow trench is less than 10 Å, and the lattice damage thickness of the shallow trench is less than 5 Å.

4. The method for forming a semiconductor structure according to claim 1, wherein Before etching the substrate by using the first reactive ion beam etching process, it further includes forming a mask layer on the surface of the substrate and etching the substrate with the mask layer as a mask.

5. The method for forming a semiconductor structure according to claim 1, wherein, The included angle range between the incident direction of the ion beam in the first reactive ion beam etching method and the normal line of the substrate is 0° to 10°.

6. The method for forming a semiconductor structure according to claim 1, wherein The etching gas in the first reactive ion beam etching process includes a mixed gas of a physical gas and a chemical gas; the physical gas uses an inert gas; the chemical gas uses one or more of a fluorine-based gas and a chlorine-based gas.

7. The method for forming a semiconductor structure according to claim 1, wherein, In the first reactive ion beam etching process, the range of the screen grid voltage is 200V - 1000V, the range of the screen grid current is 0.1A - 1A, and the range of the ion acceleration bias voltage is 100ACV - 1000ACV.

8. The method for forming a semiconductor structure according to claim 1, wherein In the first reactive ion beam etching process, the etching chamber pressure range is 0.05mT - 5mT, the total gas flow rate range is 10sccm - 100sccm, and the etching time range is 50s - 1000s.

9. The method for forming a semiconductor structure according to claim 1, wherein, In the second reactive ion beam etching process, the range of the screen grid voltage is 50V - 400V, the range of the screen grid current is 0.05A - 0.3A, and the range of the ion acceleration bias voltage is 100ACV - 1000ACV.

10. The method for forming a semiconductor structure as described in claim 1, wherein, The included angle range between the incident direction of the ion beam in the second reactive ion beam etching process and the normal line of the substrate is 0° to 80°.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, In the second reactive ion beam etching process, the etching chamber pressure range is 0.05mT - 5mT, the total gas flow rate range is 10sccm - 50sccm, and the etching time range is 60s - 300s.

12. The method for forming a semiconductor structure according to claim 1, wherein, The etching gas in the second reactive ion beam etching process uses one or more combinations of an inert gas, a fluorine-based gas, and a chlorine-based gas.

13. The method for forming a semiconductor structure according to claim 6 or 12, wherein The fluorine-based gas includes C x F y , where x and y are positive integers, and it is one or a combination of NF3, SF6, WF6, CHF3, and CH2F2.

14. The method for forming a semiconductor structure according to claim 6 or 12, wherein The chlorine-based gas includes one or more combinations of Cl2, BCl3, CCl4, and SiCl4.

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