Wafer test method and device, electronic equipment and storage medium
By obtaining the wafer failure probability mapping relationship and the initial test results, the wafer retest is selectively carried out, which solves the problem of time-consuming and low efficiency of retesting in wafer tests, and achieves efficient and low-cost testing results.
Patent Information
- Application Number
- CN202311873056.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-07-01
AI Technical Summary
In the prior art, the retesting time is too long and the efficiency is low, resulting in increased testing costs and low retest recovery.
By obtaining the wafer failure probability mapping relationship and the initial test results, we determine whether to retest the target wafer, selectively perform retesting, and reduce unnecessary retesting.
It improves wafer testing efficiency, reduces test costs, and maintains the stability of wafer yield and the accuracy of test results.
Smart Images
Figure CN120237031A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a wafer testing method, apparatus, electronic device, and storage medium. Background Art
[0002] The manufacturing process of semiconductor components includes multiple stages such as wafer manufacturing, wafer testing, packaging, and finished product testing. Among them, wafer testing is to test the die on the whole wafer.
[0003] In the prior art, when testing a wafer, usually all the die on the whole wafer are first tested initially, and then the wafers with failed initial test results are retested. The final test results will comprehensively consider the initial test and retest results, generate a test report, and select the good products to enter the next process.
[0004] However, too many wafers need to be retested, resulting in a long retest time and low efficiency. Summary of the Invention
[0005] This application provides a wafer testing method, apparatus, electronic device, and storage medium to solve the problem of excessive time consumption and low efficiency in retesting wafers in the prior art.
[0006] In a first aspect, this application provides a wafer testing method, which is applied to a wafer probe test station. The method includes:
[0007] Obtain the wafer failure probability mapping relationship and the initial test result of the target wafer; wherein, the wafer failure probability mapping relationship includes the corresponding relationship between the initial failure type of the wafer and the failure probability of the wafer for retesting; the initial failure type of the wafer is the failure type when the initial test result of the wafer is a test failure.
[0008] Determine whether to retest the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship.
[0009] Optionally, determining whether to retest the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship specifically includes:
[0010] If the initial test result of the target wafer is a test failure, determine the failure probability of the target wafer for retesting according to the initial failure type of the target wafer and the wafer failure probability mapping relationship;
[0011] If the failure probability of the target wafer for retesting is greater than a preset threshold, determine not to retest the target wafer.
[0012] Optionally, determining whether to retest the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship specifically includes:
[0013] If the initial test result of the target wafer passes the test, it is determined not to retest the target wafer.
[0014] Optionally, it is determined whether to retest the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship, which specifically includes:
[0015] If the initial test result of the target wafer fails the test and the failure type is low reliability, it is determined not to retest the target wafer.
[0016] Optionally, determining whether to retest the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship further includes:
[0017] If the failure probability of the target wafer during retesting is less than or equal to a preset threshold, it is determined to retest the target wafer.
[0018] Optionally, the method further includes:
[0019] Generate a configuration file for the wafer probe test station according to the determination result of whether to retest the target wafer;
[0020] Configure the test system of the wafer probe test station according to the configuration file, so that the test system of the wafer probe test station operates according to the determination result.
[0021] In a second aspect, the present application provides a wafer testing device, including:
[0022] An acquisition module, configured to acquire the wafer failure probability mapping relationship and the initial test result of the target wafer; wherein, the wafer failure probability mapping relationship includes the corresponding relationship between the initial failure type of the wafer and the failure probability of the wafer during retesting; the initial failure type of the wafer is the failure type when the initial test result of the wafer fails the test;
[0023] A determination module, configured to determine whether to retest the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship.
[0024] In a third aspect, the present application provides an electronic device, including: a memory and a processor;
[0025] The memory is used to store a computer program; the processor is used to execute the computer program stored in the memory to implement the wafer testing method in the first aspect and any one of the embodiments of the first aspect.
[0026] In a fourth aspect, the present application provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, it implements the wafer testing method in the first aspect and any one of the embodiments of the first aspect.
[0027] In a fifth aspect, the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the wafer testing method in the first aspect and any one of the embodiments of the first aspect.
[0028] The wafer testing method, device, electronic device, and storage medium provided by the present application determine whether to retest a target wafer by mapping the wafer failure probability relationship and the initial test result of the target wafer, achieving the effects of reducing the number of wafers to be retested, improving the wafer testing efficiency, and maintaining the stable yield of the target wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following briefly introduces the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0030] Figure 1 It is a schematic diagram of a wafer testing scenario provided by an embodiment of the present application;
[0031] Figure 2 It is a flowchart of a wafer testing method provided by an embodiment of the present application;
[0032] Figure 3 It is a flowchart of another wafer testing method provided by an embodiment of the present application;
[0033] Figure 4 It is a schematic diagram of a configuration file of a wafer probe testing platform in the prior art;
[0034] Figure 5 It is a schematic diagram of a configuration file of a wafer probe testing platform provided by an embodiment of the present application;
[0035] Figure 6 It is a schematic diagram of the retest quantity of a target wafer in the prior art;
[0036] Figure 7 It is a schematic diagram of the retest quantity of a target wafer provided by an embodiment of the present application;
[0037] Figure 8 It is a schematic diagram of the structure of a wafer testing device provided by an embodiment of the present application;
[0038] Figure 9 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0039] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings in this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts shall fall within the scope of protection of this application.
[0040] Depending on the context, the term "if" as used in this application may be interpreted as "when" or "while" or "in response to determining".
[0041] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
[0042] It should be further understood that the terms "comprising", "including" indicate the presence of features, steps, operations, elements, components, items, types, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups.
[0043] In the prior art, during wafer testing, usually all the devices on the entire wafer are tested once first, which is called the initial test. Then, the devices that fail the test are retested, and the final test result will comprehensively consider the results of the initial test and the retest, generate a test report, and select the good products to enter the next process.
[0044] As the scale of semiconductor integrated circuits becomes larger and the process becomes more advanced, etc., if the test time of the device under test is long or the test yield is low, the retest time will have a greater impact on the overall test cost. Taking an advanced process as an example, if the yield is only 50%, it means that the test duration of the retest will increase by 50% compared to the initial test, and the test cost will also increase by 50% accordingly. In addition, the retest recovery rate is also low, resulting in too high test costs.
[0045] In view of the above problems, this application proposes a wafer testing method, device, electronic device, and storage medium. By selectively retesting the devices that fail the initial test, the retest amount is reduced, and the wafer yield is not reduced, achieving the effects of improving the test efficiency and reducing the test cost.
[0046] The technical solutions of this application will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.
[0047] Figure 1 shows a schematic diagram of a wafer testing scenario provided by an embodiment of this application. AsFigure 1 As shown, the wafer is initially tested to obtain the initial test results. According to the initial test results, the wafers that need to be retested are determined, and the retest results are obtained. By integrating the initial test results and the retest results, the good wafers are selected to enter the next process. In the prior art, according to the initial test results, the wafers that need to be retested are determined by retesting all the wafers that failed in the initial test results. In this application, selective retesting is performed on the wafers that failed in the initial test results, which improves the test efficiency and does not reduce the wafer yield at the same time.
[0048] In this application, the wafer probe test station is used as the execution entity to execute the wafer test method of the following embodiments. Specifically, the execution entity can be the hardware device of the wafer probe test station, or the software application implemented in the wafer probe test station, or the computer-readable storage medium installed with the software application implementing the following embodiments, or the code of the software application implementing the following embodiments.
[0049] Figure 2 The flowchart of a wafer test method provided by an embodiment of this application is shown. As Figure 2 shown, with the wafer probe test station as the execution entity, the method of this embodiment may include the following steps:
[0050] S101. Obtain the wafer failure probability mapping relationship and the initial test results of the target wafer.
[0051] In this embodiment, the wafer failure probability mapping relationship includes the corresponding relationship between the initial failure type of the wafer and the failure probability of the wafer for retesting. The initial failure type of the wafer is the failure type when the initial test result of the wafer is a failed test.
[0052] The wafer failure probability mapping relationship can be obtained based on the initial test results and the retest results of multiple batches of wafers. The target wafer can be the wafer of the current test batch. This embodiment aims to determine whether to retest the target wafer.
[0053] S102. Determine whether to retest the target wafer according to the initial test results of the target wafer and the wafer failure probability mapping relationship.
[0054] In this embodiment, different initial failure types of wafers correspond to different retest failure probabilities. The initial test results of the target wafer can also be divided into multiple initial failure types, and then according to the retest failure probability corresponding to the initial failure type, it is determined whether to retest it.
[0055] The wafer testing method provided in this embodiment determines whether to retest a target wafer according to the wafer failure probability mapping relationship and the initial test result of the target wafer, realizes selective retesting of the target wafer, and improves the testing efficiency. At the same time, due to the wafer failure probability mapping relationship, it can be ensured that the target wafers that are not retested will not affect the final test yield.
[0056] Figure 3 The flowchart of another wafer testing method provided in an embodiment of the present application is shown. As Figure 3 shown, taking the wafer probe test station as the execution main body, the method of this embodiment may include the following steps:
[0057] S201. Obtain the wafer failure probability mapping relationship and the initial test result of the target wafer.
[0058] Among them, the implementation of step S201 is similar to that of Figure 2 step S101 in the embodiment, and will not be elaborated here in this embodiment.
[0059] S202. If the initial test result of the target wafer fails the test, determine the failure probability of the target wafer for retesting according to the initial failure type of the target wafer and the wafer failure probability mapping relationship.
[0060] In this embodiment, if the initial test result fails the test, that is, it is a failure type wafer, which can be further divided into multiple failure types, such as material aging, performance defects, etc. The failure probabilities of wafers with different failure types for retesting are different.
[0061] In one example, after step S202, step S2021 is executed: if the failure probability of the target wafer for retesting is greater than the preset threshold, determine not to retest the target wafer.
[0062] If the failure probability is greater than the preset threshold, for example, the result of retesting a wafer of a certain failure type is always a failure, or the failure probability is greater than 98%, it indicates that retesting only increases the test cost and is not beneficial to improving the wafer yield. Therefore, it can be directly determined not to retest.
[0063] In one example, after step S202, step S2022 is executed: if the failure probability of the target wafer for retesting is less than or equal to the preset threshold, determine to retest the target wafer.
[0064] If the failure probability is less than or equal to the preset threshold, it indicates that retesting may improve the wafer yield and the test cost is controllable. Therefore, the target wafer can be retested.
[0065] The wafer testing method provided in this embodiment selectively retests the target wafer by calculating the failure probability of the target wafer during retesting, reducing the impact on the yield of the target wafer, improving the testing efficiency, and ensuring the accuracy of the test results.
[0066] Continuing to refer to Figure 3 , in one example, after step S201, step S203 may further be executed: If the initial test result of the target wafer is a pass, it is determined not to retest the target wafer.
[0067] In this example, it is determined not to retest the target wafer with a passing initial test result, reducing the testing cost and not affecting the accuracy of the test results of the target wafer.
[0068] Continuing to refer to Figure 3 , in one example, after step S201, step S204 may further be executed: If the initial test result of the target wafer is a fail and the failure type is low reliability, it is determined not to retest the target wafer.
[0069] In this example, the failure type of low reliability may be that the functional test result of the target wafer shows a functional defect, or the material test result of the target wafer shows material aging, etc., resulting in a reliability risk when the target wafer is in use. In addition, low reliability may also cause the failure probability during retesting to be greater than the preset threshold. In this example, such target wafers are not retested.
[0070] The wafer testing method provided in this example does not retest the target wafers with a failure type of low reliability in the initial test result, improving the testing efficiency, not affecting the test yield of the target wafers, and reducing the testing cost.
[0071] Based on the above embodiments, the present application further provides a wafer testing method, with the wafer probe test station as the execution entity. The wafer testing method of this embodiment further includes the following steps:
[0072] Step 1: Generate a configuration file for the wafer probe test station according to the determination result of whether to retest the target wafer.
[0073] Figure 4 It is a schematic diagram of a configuration file of a wafer probe test station in the prior art. As Figure 4 shown, in the prior art, wafers with a failed initial test result are archived into categories 2 - 6 and category 9, and all wafers in these categories are retested.
[0074] Figure 5 It is a schematic diagram of a configuration file of a wafer probe test station provided in an embodiment of the present application. As Figure 5As shown, after the wafers with failed initial test results are selected, the wafers that need to be retested are filed into category 2, and only the wafers in this category are retested. Optionally, the wafers with passed initial test results can be filed into category 1, the wafers selected for retesting are filed into category 2, and the remaining wafers not undergoing retesting are filed into category 0, such as wafers with a retest failure probability greater than 98%.
[0075] Step 2: Configure the test system of the wafer probe station according to the configuration file, so that the test system of the wafer probe station operates according to the determined results.
[0076] Figure 6 It is a schematic diagram of the amount of retesting of a target wafer in the prior art. As Figure 6 shown, the black grains in the figure represent the parts with failed initial test results. In the prior art, all these grains need to be retested, resulting in a large test volume. The results of the prior art retesting are shown in Table 1. The average total test duration is 82 minutes, and the yield obtained from the test results is 82.81%.
[0077] Table 1 Example of test results of seven wafers in the prior art
[0078] Wafer ID Process Throughput Total Quantity Yield Test Duration 1 CP1 738 875 84.34％ 1：40：12 2 CP1 757 875 86.51％ 1：25：15 3 CP1 758 875 86.63％ 1：15：22 4 CP1 736 875 84.11％ 1：14：09 5 CP1 747 875 85.37％ 1：17：13 6 CP1 739 875 84.46％ 1：20：02 7 CP1 597 875 68.23％ 1：22：00 Statistics CP1 5072 6125 82.81％ 1：22：02
[0079] Figure 7 It is a schematic diagram of the amount of retesting of a target wafer provided by an embodiment of the present application. As Figure 7 shown, the number of black grains in the figure is significantly reduced, that is, the workload of retesting is reduced, and the efficiency of wafer testing can be improved. Using the test method of the present application, the results of the retesting are shown in Table 2. The average total test duration is 20 minutes, and the yield obtained from the test results is 82.95%.
[0080] Table 2 Example of initial test and retest results of seven wafers in the present application
[0081] Wafer ID Process Throughput Total Quantity Yield Test Duration 1 CP1 739 875 84.46％ 1：18：43 2 CP1 758 875 86.63％ 0：53：24 3 CP1 760 875 86.86％ 0：42：37 4 CP1 738 875 84.34％ 0：41：57 5 CP1 747 875 85.37％ 0：48：12 6 CP1 740 875 84.57％ 0：48：39 7 CP1 598 875 68.42％ 0：42：53 Statistics CP1 5080 6125 82.95％ 0：50：55
[0082] It can be seen that the wafer testing method provided by the embodiment of the present application can significantly shorten the test time, improve the test efficiency, and at the same time, the wafer yields in the test results are relatively close. That is to say, the wafer testing method of the present application can improve the test efficiency, reduce the test cost, and will not affect the test results.
[0083] Figure 8 shows a schematic structural diagram of a wafer testing device provided by an embodiment of the present application. As Figure 8 shown, the wafer testing device 10 of this embodiment is used to implement the operations corresponding to the wafer probe station in any of the above method embodiments. The wafer testing device 10 of this embodiment includes:
[0084] An acquisition module 11, configured to acquire a wafer failure probability mapping relationship and an initial test result of a target wafer; wherein, the wafer failure probability mapping relationship includes a correspondence between an initial failure type of the wafer and a failure probability of the wafer for a retest; the initial failure type of the wafer is the failure type when the initial test result of the wafer is a failed test.
[0085] A determination module 12, configured to determine whether to retest the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship.
[0086] In one example, the determination module 12 is further configured to, if the initial test result of the target wafer is a failed test, determine the failure probability of the target wafer for a retest according to the initial failure type of the target wafer and the wafer failure probability mapping relationship.
[0087] If the failure probability of the target wafer for a retest is greater than a preset threshold, determine not to retest the target wafer.
[0088] In one example, the determination module 12 is further configured to, if the initial test result of the target wafer is a passed test, determine not to retest the target wafer.
[0089] In one example, the determination module 12 is further configured to, if the initial test result of the target wafer is a failed test and the failure type is low reliability, determine not to retest the target wafer.
[0090] In one example, the determination module 12 is further configured to, if the failure probability of the target wafer for a retest is less than or equal to the preset threshold, determine to retest the target wafer.
[0091] In one example, the wafer testing device 10 further includes a configuration module, configured to generate a configuration file for a wafer probe test station according to a determination result of whether to retest the target wafer.
[0092] Configure the test system of the wafer probe test station according to the configuration file, so that the test system of the wafer probe test station operates according to the determination result.
[0093] The wafer testing device 10 provided in the embodiment of the present application can execute the above method embodiment, and for its specific implementation principle and technical effect, reference can be made to the above method embodiment, which will not be elaborated here in this embodiment.
[0094] Figure 9 Shows a schematic hardware structure diagram of an electronic device provided in an embodiment of the present application. As Figure 9As shown, the electronic device 20 is used to implement the operations corresponding to the wafer probe test bench in any of the above method embodiments. The electronic device 20 in this embodiment may include: a memory 21, a processor 22, and a communication interface 24.
[0095] The memory 21 is used to store computer programs. The memory 21 may include high-speed random access memory (Random Access Memory, RAM), and may also include non-volatile storage (Non-Volatile Memory, NVM), such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a disk, or an optical disc, etc.
[0096] The processor 22 is used to execute the computer programs stored in the memory to implement the wafer testing method in the above embodiments. For specific details, reference may be made to the relevant descriptions in the foregoing method embodiments. The processor 22 may be a central processing unit (Central Processing Unit, CPU), or may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the invention can be directly implemented by the execution of the hardware processor, or can be implemented by the combination of the hardware and software modules in the processor.
[0097] Optionally, the memory 21 may be either independent or integrated with the processor 22.
[0098] When the memory 21 is a device independent of the processor 22, the electronic device 20 may further include a bus 23. The bus 23 is used to connect the memory 21 and the processor 22. The bus 23 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.
[0099] The communication interface 24 may be connected to the processor 22 through the bus 23. The processor 22 may control the communication interface 24 to implement the functions of signal reception and transmission.
[0100] The electronic device 20 provided in this embodiment can be used to execute the above-mentioned wafer testing method, and its implementation manner and technical effect are similar, which will not be elaborated here in this embodiment.
[0101] This application also provides a computer-readable storage medium, in which computer programs / instructions are stored. When the computer programs / instructions are executed by a processor, they are used to implement the methods provided by the above various embodiments.
[0102] Among them, the computer-readable storage medium can be a computer storage medium or a communication medium. The communication medium includes any medium that facilitates the transmission of computer programs from one place to another. The computer storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer. For example, the computer-readable storage medium is coupled to the processor, so that the processor can read information from the computer-readable storage medium and write information to the computer-readable storage medium. Of course, the computer-readable storage medium can also be a component of the processor. The processor and the computer-readable storage medium can be located in an application specific integrated circuit (ASIC). In addition, the ASIC can be located in a user device. Of course, the processor and the computer-readable storage medium can also exist as discrete components in a communication device.
[0103] Specifically, the computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk or an optical disc. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.
[0104] The present application also provides a computer program product, which includes computer programs / instructions stored in a computer-readable storage medium. At least one processor of the device can read the computer programs / instructions from the computer-readable storage medium, and the execution of the computer programs / instructions by the at least one processor enables the device to implement the methods provided by the various embodiments described above.
[0105] In several embodiments provided by the present application, it should be understood that the disclosed device and method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or module can be in an electrical, mechanical or other form.
[0106] Among them, each module can be physically separated. For example, it can be installed at different positions of a device, or installed on different devices, or distributed to multiple network units, or distributed to multiple processors. Each module can also be integrated together. For example, it can be installed in the same device, or integrated in a set of codes. Each module can exist in the form of hardware, or can also exist in the form of software, or can also be implemented in the form of software plus hardware. The present application can select some or all of the modules according to actual needs to achieve the purpose of the solution of this embodiment.
[0107] It should be understood that although the steps in the flowcharts in the above embodiments are displayed in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and they can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. Their execution order is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A wafer testing method, characterized in that, The method is applied to a wafer probe test bench, and the method includes: Obtaining a wafer failure probability mapping relationship and the initial test result of a target wafer; wherein, the wafer failure probability mapping relationship includes the corresponding relationship between the initial failure type of the wafer and the failure probability of the wafer for re - testing; the initial failure type of the wafer is the failure type when the initial test result of the wafer is a failed test; Determining whether to re - test the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship.
2. The wafer testing method according to claim 1, wherein Determining whether to re - test the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship specifically includes: If the initial test result of the target wafer is a failed test, determining the failure probability of the target wafer for re - testing according to the initial failure type of the target wafer and the wafer failure probability mapping relationship; If the failure probability of the target wafer for re - testing is greater than a preset threshold, determining not to re - test the target wafer.
3. The wafer testing method according to claim 1, wherein Determining whether to re - test the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship specifically includes: If the initial test result of the target wafer is a passed test, determining not to re - test the target wafer.
4. The wafer testing method according to claim 1, wherein Determining whether to re - test the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship specifically includes: If the initial test result of the target wafer is a failed test and the failure type is low reliability, determining not to re - test the target wafer.
5. The wafer testing method according to claim 2, wherein Determining whether to re - test the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship further includes: If the failure probability of the target wafer for re - testing is less than or equal to the preset threshold, determining to re - test the target wafer.
6. The wafer testing method according to any one of claims 1 to 5, characterized in that The method further includes: Generating a configuration file of the wafer probe test bench according to the determination result of whether to re - test the target wafer; Configuring the test system of the wafer probe test bench according to the configuration file, so that the test system of the wafer probe test bench operates according to the determination result.
7. A wafer testing device, characterized in that, The device includes: An obtaining module, configured to obtain a wafer failure probability mapping relationship and the initial test result of a target wafer; wherein, the wafer failure probability mapping relationship includes the corresponding relationship between the initial failure type of the wafer and the failure probability of the wafer for re - testing; the initial failure type of the wafer is the failure type when the initial test result of the wafer is a failed test; A determining module, configured to determine whether to re - test the target wafer according to the initial test result of the target wafer and the wafer failure probability mapping relationship.
8. An electronic device, characterized in that, The device includes: a memory and a processor; The memory is used for storing a computer program; The processor is used for executing the computer program stored in the memory to implement the wafer testing method according to any one of claims 1 - 6.
9. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, it is used to implement the wafer testing method described in any one of claims 1-6.
10. A computer program product, characterized in that, The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the wafer testing method described in any one of claims 1-6.