Wafer defect detection method, device and equipment
By conducting multi-level detection of wafers, analyzing its COP distribution and further detecting of defects for each wafer, the problem of inaccurate identification of different types of defects in the prior art is solved, and high-accurate defect detection is achieved.
Patent Information
- Application Number
- CN202510380745.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-01
AI Technical Summary
The prior art is difficult to accurately identify different types of wafer defects, and it is prone to misjudgment or misjudgment.
By obtaining the first wafer defect map of the wafer and analyzing its COP distribution, if there is no COP defect, further defect detection is performed on each wafer to obtain the first defect detection result to achieve accurate identification of different types of defects.
Multi-level detection of wafers is realized, and COP defects and other types of defects are accurately identified, avoiding disk leakage or misjudgment, and improving the accuracy of detection.
Smart Images
Figure CN120237034A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a method, device, and equipment for detecting wafer defects. Background Art
[0002] During the manufacturing process of wafers, various types of defects may occur on the wafer surface, such as crystal originated particles (COP) and continuity defects. When detecting wafer defects, defect identification and classification usually rely on a single-level judgment criterion. However, when using this judgment criterion to detect different types of defects on wafers, misjudgment or missed judgment often occurs, and different types of defects cannot be accurately identified. Summary of the Invention
[0003] Embodiments of the present invention provide a method, device, and equipment for detecting wafer defects to solve the problem in the prior art that different types of defects cannot be identified.
[0004] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:
[0005] In a first aspect, an embodiment of the present invention provides a method for detecting wafer defects, including:
[0006] Obtain a first wafer defect map of a first batch of wafers, where the first batch of wafers includes multiple wafers, and the first wafer defect map indicates the distribution of crystal originated particles (COP) of the wafers in the first batch of wafers;
[0007] Based on the first wafer defect map, obtain a first COP detection result of the first batch of wafers;
[0008] In the case where the first COP detection result indicates that there are no COP defects in the first batch of wafers, perform defect detection on each wafer in the first batch of wafers respectively to obtain a first defect detection result of the wafer, where the first defect detection result is used to indicate whether there is a first defect on the wafer, and the first defect is a defect other than the COP defect.
[0009] In some embodiments, obtaining a first wafer defect map of a first batch of wafers includes:
[0010] Use a particle counter to scan each wafer in the first batch of wafers to obtain a first defect map of the wafer, and the first defect map is used to indicate defect information at different positions on the wafer;
[0011] Project the first defect map of each of the wafers onto the first defect map of the first wafer to obtain the first wafer defect map, where the first wafer is any wafer in the first batch of wafers.
[0012] In some embodiments, obtaining the first COP detection result of the first batch of wafers according to the first wafer defect map includes:
[0013] Obtain the defect distribution characteristics on the first batch of wafers according to the first wafer defect map;
[0014] When the defect distribution characteristics satisfy at least one of the following, determine that the first COP detection result indicates that the first batch of wafers has COP defects; otherwise, determine that the first COP detection result indicates that the first batch of wafers does not have COP defects:
[0015] The defect distribution aggregates in the edge region of the first wafer defect map;
[0016] The defect distribution aggregates in the central region of the first wafer defect map.
[0017] In some embodiments, the method further includes:
[0018] When the first COP detection result indicates that the first batch of wafers has COP defects, determine to intercept the first batch of wafers.
[0019] In some embodiments, defect detection is performed on each wafer in the first batch of wafers to obtain the first defect detection result of the wafer, including:
[0020] Perform defect detection on each of the wafers respectively to obtain the spatial defect distribution map of the wafer;
[0021] Obtain the first defect detection result of the wafer according to the spatial defect distribution map.
[0022] In some embodiments, the first defect includes at least one of the following:
[0023] Cluster type defects;
[0024] Micro-graphic defects of continuous target shapes;
[0025] Micro-graphic defects of discontinuous target shapes.
[0026] In some embodiments, the method further includes:
[0027] Determine the second wafers in the first batch of wafers that have the first defect according to the first defect detection result;
[0028] Remove the second wafer from the first batch of wafers to obtain a second batch of wafers;
[0029] Perform quality inspection on the second batch of wafers to obtain the quality inspection result of the second batch of wafers.
[0030] In some embodiments, performing quality inspection on the second batch of wafers to obtain the quality inspection result of the second batch of wafers includes:
[0031] Obtain a second wafer defect map of the second batch of wafers, where the second batch of wafers includes at least one wafer, and the second wafer defect map indicates the COP distribution of the wafers in the second batch of wafers;
[0032] Obtain a second COP inspection result of the second batch of wafers according to the second wafer defect map;
[0033] When the second COP inspection result indicates that there are no COP defects in the second batch of wafers, determine that the quality inspection result indicates that the second batch of wafers is qualified in quality.
[0034] In a second aspect, an embodiment of the present invention further provides a wafer defect detection device, including:
[0035] A first acquisition module, configured to acquire a first wafer defect map of a first batch of wafers, where the first batch of wafers includes a plurality of wafers, and the first wafer defect map indicates the crystal native defect COP distribution of the wafers in the first batch of wafers;
[0036] A first processing module, configured to obtain a first COP inspection result of the first batch of wafers according to the first wafer defect map;
[0037] A second processing module, configured to, when the first COP inspection result indicates that there are no COP defects in the first batch of wafers, perform defect detection on each wafer in the first batch of wafers respectively to obtain a first defect detection result of the wafer, where the first defect detection result is used to indicate whether there is a first defect on the wafer, and the first defect is a defect other than the COP defect.
[0038] In a third aspect, an embodiment of the present invention further provides a wafer defect detection device, including: a processor, a memory, and a program stored on the memory and executable on the processor, where when the program is executed by the processor, the steps in any one of the above wafer defect detection methods are implemented.
[0039] The embodiments of the present invention have the following beneficial effects:
[0040] The wafer defect detection method provided by the embodiments of the present invention performs defect detection on the wafers of the first batch to obtain a first wafer defect map of the wafers of the first batch. This first wafer defect map indicates the COP distribution of the wafers in the first batch. According to this first wafer defect map, a first COP defect detection result of the wafers of the first batch is obtained. Based on this first COP defect detection result, it can be identified whether there are COP removal defects on the wafers of the first batch. If there are no COP defects on the wafers of the first batch, defect detection is respectively performed on each wafer to obtain a first defect detection result of the wafer. According to this first defect detection result, it can be determined whether there are first defects on the wafer, thereby realizing multi-level detection of the wafer to detect COP defects and other types of defects other than COP defects on the wafer, achieving the purpose of accurately identifying different types of defects and avoiding missing or misjudging wafer defects. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 It represents a flowchart of the wafer defect detection method provided by the embodiments of the present invention;
[0042] Figure 2 It represents a schematic structural diagram of the wafer defect detection device provided by the embodiments of the present invention;
[0043] Figure 3 It represents a schematic structural diagram of the circular defect detection device provided by the embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0044] To make the technical problems, technical solutions, and advantages to be solved by the embodiments of the present invention clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments.
[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention fall within the scope of protection of the present invention.
[0046] To solve the problem in the prior art that it is impossible to identify different types of defects, the embodiments of the present invention provide a wafer defect detection method, device, and equipment.
[0047] As Figure 1 shown, the embodiments of the present invention provide a wafer defect detection method, including:
[0048] Step 101: Obtain the first wafer defect map of the first batch of wafers. The first batch of wafers includes multiple wafers, and the first wafer defect map indicates the distribution of crystal originated particles (COP) of the wafers in the first batch of wafers.
[0049] It should be noted that the first batch of wafers can be any batch of wafers or the current batch of wafers. A batch of wafers includes multiple wafers, and a batch of wafers can also be understood as including the wafers in one wafer cassette or the wafers in several wafer cassettes.
[0050] In this step, through the initial batch inspection of the first batch of wafers, the first wafer defect map (wafer MAP) of the first batch of wafers is obtained. This first wafer defect map indicates the surface defect information of all wafers in the first batch of wafers. Moreover, since the COP defects of wafers often exhibit the characteristic of batch distribution, the first wafer defect map of the first batch of wafers can show the COP defect distribution of the wafers, that is, the first wafer defect map can reflect whether the first batch of wafers has the defect distribution characteristic of the COP type.
[0051] It can be understood that the first wafer defect map includes the positions on the wafer and the defect information of each position on the wafer. Whether the wafer has the defect distribution characteristic of the COP type is determined according to the defect information of different positions on the wafer.
[0052] Step 102: Obtain the first COP detection result of the first batch of wafers according to the first wafer defect map.
[0053] In this step, by analyzing the first wafer defect map, it is judged whether the COP defect characteristic appears in the first wafer defect map, that is, whether the current first batch of wafers shown in the first wafer defect map conforms to the COP defect distribution characteristic is used as the first COP detection result of the first batch of wafers.
[0054] Step 103: In the case where the first COP detection result indicates that the first batch of wafers has no COP defects, defect detection is respectively performed on each wafer in the first batch of wafers to obtain the first defect detection result of the wafer, where the first defect detection result is used to indicate whether there is a first defect on the wafer, and the first defect is a defect other than the COP defect.
[0055] In this step, according to the first COP detection result, it is determined that the first batch of wafers does not conform to the COP defect distribution characteristic, and then it is determined that the first batch of wafers has no COP defects, that is, the COP defect detection of the first batch of wafers is realized, and whether there are COP defects on the first batch of wafers is identified.
[0056] In the case where there are no COP defects in the first batch of wafers, defect detection is performed on each wafer in the first batch of wafers, that is, single-wafer detection is performed on the wafers without COP defects to obtain the first defect detection result of the wafers, and whether there are first defects on the wafers is identified according to the first defect detection result.
[0057] Among them, the first defects include at least one of the following:
[0058] Cluster type defects (i.e., defects of the aggregated cluster type);
[0059] Micro-graphic defects of continuous target shapes (i.e., continuous Special pattern);
[0060] Micro-graphic defects of discontinuous target shapes (i.e., un-continuous Special pattern).
[0061] Among them, the target shape can be a special shape such as a ring shape, a linear shape, etc.
[0062] In this step, the types of defects are refined for single-wafer defects, improving the accuracy of defect detection.
[0063] In the embodiments of the present invention, through multi-level detection of wafers, COP defects of the wafers and other types of defects other than COP defects are detected, so as to achieve the purpose of accurately identifying different types of defects and avoid missing or misjudging wafer defects.
[0064] In some embodiments, obtaining the first wafer defect map of the first batch of wafers includes:
[0065] Scanning each wafer in the first batch of wafers with a Particle Counter to obtain the first defect map of the wafer. The first defect map is used to indicate defect information at different positions on a single wafer, that is, scanning each single wafer with a Particle Counter on the crystal surface to detect defect features on the wafer surface and their position coordinates on the wafer, and generating the first defect map according to the defects at different positions on the wafer.
[0066] Projecting the first defect map of each wafer onto the first defect map of the first wafer to obtain the first wafer defect map, where the first wafer is any wafer in the first batch of wafers.
[0067] Specifically, after scanning the surface of each wafer and generating the first defect map corresponding to each wafer, through the spatial image overlay technology, the defect information shown in the first defect maps of the entire batch of wafers is projected onto the first defect map of one of the wafers, and then the first wafer defect map of the first batch of wafers is obtained.
[0068] In some embodiments, according to the first wafer defect map, the first crystal native defect COP detection result of the first batch of wafers is obtained, including:
[0069] According to the first wafer defect map, the defect distribution characteristics on the first batch of wafers are obtained. Specifically, by using the Automatic Defect Classification (ADC) technology, through judging the first wafer defect map, the defect distribution characteristics shown in the first wafer defect map are obtained, and the defect distribution characteristics include the position of the defect on the wafer, the size of the defect, the shape of the defect, etc.
[0070] It should be noted that since the COP defect has the characteristic of batch characteristics, therefore, when performing overlay analysis on wafers of the same batch, a regular distribution pattern may appear in the first wafer defect map, but it may show a normal state on a single wafer. Therefore, in this embodiment, overlay analysis is performed on the entire batch of wafers to obtain the defect distribution characteristics of the first batch of wafers.
[0071] Among them, the extraction method of the defect distribution characteristics on the first batch of wafers can be to extract gray-scale characteristics, etc.
[0072] When the defect distribution characteristics satisfy at least one of the following conditions, it is determined that the first COP detection result of the first batch of wafers indicates that the first batch of wafers has COP defects; otherwise, it is determined that the first COP detection result indicates that the first batch of wafers does not have COP defects:
[0073] The defect distribution gathers in the edge area of the first wafer defect map;
[0074] The defect distribution gathers in the central area of the first wafer defect map.
[0075] Among them, the area where the radial distance between the first wafer defect map and the edge of the wafer is less than or equal to the first preset distance is defined as the edge area of the first wafer defect map, and the area where the radial distance between the first wafer defect map and the center of the wafer is less than or equal to the second preset distance is defined as the central area of the first wafer defect map.
[0076] If the overlay result of the first wafer defect map shows that the wafers within the batch conform to the COP defect distribution characteristics, such as edge aggregation, center aggregation, and edge plus center aggregation, it is determined that the first batch of wafers has COP defects, and it is judged that the entire first batch of wafers is unqualified.
[0077] Further, the method further includes:
[0078] In the case where the first COP detection result indicates that the first batch of wafers has COP defects, it is determined to intercept the first batch of wafers.
[0079] That is, in the case where the wafers have COP defects, it is determined that the entire first batch of wafers is unqualified, and it is necessary to intercept the first batch of wafers without performing the subsequent step of detecting and identifying the defect types of individual wafers, thereby improving the detection efficiency.
[0080] In some embodiments, defect detection is respectively performed on each wafer in the first batch of wafers to obtain the first defect detection result of the wafer, including:
[0081] Defect detection is respectively performed on each wafer to obtain the spatial defect distribution map of the wafer. Among them, when performing defect detection on the wafer, the wafer can be respectively detected by laser scanning technology, electron beam detection technology, etc. to identify different defects of the wafer. The spatial defect distribution map of the wafer is used to indicate the distribution of the first defects on the wafer.
[0082] According to the spatial defect distribution map, the first defect detection result of the wafer is obtained.
[0083] Specifically, image preprocessing and image feature extraction are performed on the spatial defect distribution map, and the ADC technology is used to classify and identify the defects on the wafer, so as to detect whether there are first defects on the wafer and what specific first defects the first defects have.
[0084] The single-wafer judgment at this stage refines the defect classification and improves the accuracy of defect identification.
[0085] Further, the method further includes:
[0086] In the case where the first defect detection result indicates that the wafer has a first defect, the wafer is intercepted.
[0087] That is, in the case where it is detected that the wafer has a first defect, the quality of the single wafer is defective, and then the wafer is intercepted.
[0088] Further, the method further includes:
[0089] Based on the first defect detection result, determine the second wafers with the first defect in the first batch of wafers. Specifically, after obtaining the first defect detection result for a single wafer, if it is determined according to the first defect detection result that there is no first defect in the wafer, then it is determined that the quality of the wafer is qualified (OK) and marked as "OK", that is, the second wafer; if it is determined according to the first defect detection result that there is a first defect in the wafer, then it is determined that the quality of the wafer is unqualified (NG) and marked as "NG".
[0090] Remove the second wafers from the first batch of wafers to obtain a second batch of wafers. After the single-wafer judgment stage, intercept the second wafers with unqualified quality in the first batch of wafers, and the remaining wafers are the second batch of wafers;
[0091] Perform a quality inspection on the second batch of wafers to obtain the quality inspection result of the second batch of wafers. That is, after the single-wafer inspection of the wafers, batch review all the remaining wafers and perform a second batch judgment. According to the quality inspection result of the second batch of wafers, determine whether the second batch of wafers is qualified in quality.
[0092] Optionally, performing a quality inspection on the second batch of wafers to obtain the quality inspection result of the second batch of wafers includes:
[0093] Obtain the second wafer defect map of the second batch of wafers, where the second batch of wafers includes at least one wafer, and the second wafer defect map indicates the COP distribution of the wafers in the second batch of wafers;
[0094] Based on the second wafer defect map, obtain the second COP detection result of the second batch of wafers.
[0095] It should be noted that the process of obtaining the second wafer defect map of the second batch of wafers is basically the same as the process of obtaining the first wafer defect map of the first batch of wafers above, and the second wafer defect map and the first wafer defect map have the same indicated meaning, except for the specific parameter values. Also, the process of obtaining the second COP detection result is basically the same as the process of obtaining the first COP detection result, and the second COP detection result and the first COP detection result have the same indicated meaning, except for the specific parameter values.
[0096] In the case where the second COP detection result indicates that there are no COP defects in the second batch of wafers, determine that the quality inspection result indicates that the second batch of wafers is qualified in quality.
[0097] That is, in the case where the second COP detection result indicates that there are no COP defects in the second batch of wafers, mark the second batch of wafers as "OK", and this batch passes the inspection and enters the shipping process.
[0098] In the case that the second COP detection result indicates that the second batch of wafers has COP defects, mark the second batch of wafers as "NG", and intercept the second batch of wafers to prevent potentially defective products from flowing into the shipping process and ensure the shipping quality.
[0099] Furthermore, conduct an engineer review on the second batch of wafers marked as "NG" to prevent batch defects that do not meet the single-piece NG standard.
[0100] In summary, in the embodiments of the present invention, through a multi-level process of initial batch judgment, single-piece detection, and secondary batch judgment, COP defects are effectively distinguished from other defects, COP defect batches are intercepted in advance, misjudgment and missed judgment are reduced, and the shipping yield is ensured; the first batch of wafers is subjected to the first detection, and early interception of serious defects such as COP is achieved, reducing unnecessary detection operations, thereby improving the detection efficiency; the phased interception process significantly reduces the repetition rate of detection, reduces resource waste caused by misjudgment, and thus saves the detection cost; through the secondary batch judgment mechanism, the detection accuracy before shipping is improved, and the shipping stability of wafer products is improved.
[0101] As Figure 2 shown, the embodiments of the present invention also provide a wafer defect detection device, including:
[0102] A first acquisition module 201, configured to acquire a first wafer defect map of the first batch of wafers, where the first batch of wafers includes multiple wafers, and the first wafer defect map indicates the distribution of crystal native defects COP of the wafers in the first batch of wafers;
[0103] A first processing module 202, configured to obtain a first COP detection result of the first batch of wafers according to the first wafer defect map;
[0104] A second processing module 203, configured to, in the case that the first COP detection result indicates that the first batch of wafers does not have COP defects, perform defect detection on each wafer in the first batch of wafers respectively to obtain a first defect detection result of the wafer, where the first defect detection result is used to indicate whether there is a first defect on the wafer, and the first defect is a defect other than the COP defect.
[0105] Optionally, the first acquisition module 201 includes:
[0106] A first processing unit, configured to scan each wafer in the first batch of wafers by using a particle counter to obtain a first defect map of the wafer, where the first defect map is used to indicate defect information at different positions on the wafer;
[0107] A first acquisition unit, configured to project the first defect map of each of the wafers onto the first defect map of the first wafer, to obtain the first wafer defect map, where the first wafer is any wafer in the first batch of wafers.
[0108] Optionally, the first processing module 202 includes:
[0109] A second processing unit, configured to obtain the defect distribution characteristics on the first batch of wafers according to the first wafer defect map;
[0110] A third processing unit, configured to determine that the first COP detection result indicates that the first batch of wafers has COP defects when the defect distribution characteristics satisfy at least one of the following conditions; otherwise, determine that the first COP detection result indicates that the first batch of wafers does not have COP defects:
[0111] The defect distribution aggregates in the edge region of the first wafer defect map;
[0112] The defect distribution aggregates in the central region of the first wafer defect map.
[0113] Optionally, the device further includes:
[0114] A third processing module, configured to determine to intercept the first batch of wafers when the first COP detection result indicates that the first batch of wafers has COP defects.
[0115] Optionally, the second processing module 203 includes:
[0116] A fourth processing unit, configured to perform defect detection on each of the wafers respectively, to obtain the spatial defect distribution map of the wafers;
[0117] A fifth processing unit, configured to obtain the first defect detection result of the wafers according to the spatial defect distribution map.
[0118] Optionally, the first defect includes at least one of the following:
[0119] Cluster type defects;
[0120] Continuous target-shaped micro-graphic defects;
[0121] Discontinuous target-shaped micro-graphic defects.
[0122] Optionally, the device further includes:
[0123] A fourth processing module, configured to determine a second wafer with the first defect in the first batch of wafers according to the first defect detection result;
[0124] The fifth processing module is used to remove the second wafer from the first batch of wafers to obtain a second batch of wafers;
[0125] The sixth processing module is used to perform quality inspection on the second batch of wafers to obtain the quality inspection result of the second batch of wafers.
[0126] Optionally, the sixth processing module includes:
[0127] The second acquisition unit is used to acquire the second wafer defect map of the second batch of wafers, where the second batch of wafers includes at least one wafer, and the second wafer defect map indicates the COP distribution of the wafers in the second batch of wafers;
[0128] The sixth processing unit is used to obtain the second COP inspection result of the second batch of wafers according to the second wafer defect map;
[0129] The seventh processing unit is used to determine that the quality inspection result indicates that the second batch of wafers is qualified when the second COP inspection result indicates that there are no COP defects in the second batch of wafers.
[0130] It should be noted that the wafer defect detection device provided in the embodiments of the present invention is a device capable of executing the above-mentioned wafer defect detection method. Therefore, all the embodiments of the above-mentioned wafer defect detection are applicable to this device and can achieve the same or similar technical effects.
[0131] As Figure 3 shown, the embodiments of the present invention further provide a silicon wafer topography adjustment device, including: a processor 301; and a memory 303 connected to the processor 301 through a bus interface 302. The memory 303 is used to store the programs and data used by the processor 301 when performing operations, and the processor 301 calls and executes the programs and data stored in the memory 303.
[0132] Wherein, the transceiver 304 is connected to the bus interface 302 and is used to receive and send data under the control of the processor 301. Specifically, the processor 301 is used to read the program in the memory 303, and the processor 301 is used to perform the following processes:
[0133] Acquire the first wafer defect map of the first batch of wafers, where the first batch of wafers includes multiple wafers, and the first wafer defect map indicates the distribution of crystal native defects COP of the wafers in the first batch of wafers;
[0134] Obtain the first COP inspection result of the first batch of wafers according to the first wafer defect map;
[0135] When the first COP detection result indicates that there are no COP defects in the first batch of wafers, defect detection is respectively performed on each wafer in the first batch of wafers to obtain the first defect detection result of the wafer, where the first defect detection result is used to indicate whether there are first defects on the wafer, and the first defects are defects other than the COP defects.
[0136] Optionally, the processor 301 is configured to:
[0137] Use a particle counter to scan each wafer in the first batch of wafers to obtain the first defect map of the wafer, where the first defect map is used to indicate defect information at different positions on the wafer;
[0138] Project the first defect map of each wafer onto the first defect map of the first wafer to obtain the first wafer defect map, where the first wafer is any wafer in the first batch of wafers.
[0139] Optionally, the processor 301 is configured to:
[0140] Obtain the defect distribution characteristics on the first batch of wafers according to the first wafer defect map;
[0141] When the defect distribution characteristics satisfy at least one of the following, determine that the first COP detection result indicates that there are COP defects in the first batch of wafers, otherwise, determine that the first COP detection result indicates that there are no COP defects in the first batch of wafers:
[0142] The defect distribution is concentrated in the edge area of the first wafer defect map;
[0143] The defect distribution is concentrated in the central area of the first wafer defect map.
[0144] Optionally, the processor 301 is further configured to:
[0145] When the first COP detection result indicates that there are COP defects in the first batch of wafers, determine to intercept the first batch of wafers.
[0146] Optionally, the processor 301 is configured to:
[0147] Respectively perform defect detection on each wafer to obtain the spatial defect distribution map of the wafer;
[0148] Obtain the first defect detection result of the wafer according to the spatial defect distribution map.
[0149] Optionally, the first defects include at least one of the following:
[0150] Cluster type defect;
[0151] Micrographic defect of a continuous target shape;
[0152] Micrographic defect of a discontinuous target shape.
[0153] Optionally, the processor 301 is further configured to:
[0154] Determine a second wafer with the first defect in the first batch of wafers according to the first defect detection result;
[0155] Remove the second wafer from the first batch of wafers to obtain a second batch of wafers;
[0156] Perform quality inspection on the second batch of wafers to obtain the quality inspection result of the second batch of wafers.
[0157] Optionally, the processor 301 is specifically configured to:
[0158] Obtain a second wafer defect map of the second batch of wafers, where the second batch of wafers includes at least one wafer, and the second wafer defect map indicates the COP distribution of the wafers in the second batch of wafers;
[0159] Obtain a second COP detection result of the second batch of wafers according to the second wafer defect map;
[0160] When the second COP detection result indicates that there is no COP defect in the second batch of wafers, determine that the quality inspection result indicates that the second batch of wafers is qualified.
[0161] Wherein, in Figure 3 The bus architecture may include any number of interconnected buses and bridges, specifically various circuits of one or more processors represented by the processor 301 and the memory represented by the memory 303 are linked together. The bus architecture can also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, etc., which are well known in the art, so they will not be further described herein. The bus interface provides the user interface 305. The transceiver 304 can be multiple components, that is, including a transmitter and a receiver, and provides a unit for communicating with various other devices on the transmission medium. The processor 301 is responsible for managing the bus architecture and general processing, and the memory 303 can store the data used by the processor 301 when performing operations.
[0162] The above are the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A wafer defect detection method, characterized in that: include: Obtaining a first wafer defect map of a first batch of wafers, wherein the first batch of wafers includes a plurality of wafers, and the first wafer defect map indicates a distribution of crystal native defects (COPs) of wafers in the first batch of wafers; Obtaining a first COP test result of the first batch of wafers according to the first wafer defect map; When the first COP detection result indicates that the first batch of wafers does not have a COP defect, defect detection is performed on each wafer in the first batch of wafers to obtain a first defect detection result of the wafer, wherein the first defect detection result is used to indicate whether there is a first defect on the wafer, and the first defect is a defect other than the COP defect.
2. The wafer defect detection method according to claim 1, characterized in that: Obtain the first wafer defect map for the first batch of wafers, including: Scanning each wafer in the first batch of wafers using a particle counter to obtain a first defect map of the wafer, where the first defect map is used to indicate defect information at different positions on the wafer; The first defect map of each wafer is projected onto the first defect map of the first wafer to obtain the first wafer defect map, wherein the first wafer is any wafer in the first batch of wafers.
3. The wafer defect detection method according to claim 1, characterized in that: Obtaining a first COP test result of the first batch of wafers according to the first wafer defect map includes: Obtaining defect distribution characteristics on the first batch of wafers according to the first wafer defect map; When the defect distribution characteristic satisfies at least one of the following, it is determined that the first COP test result indicates that the first batch of wafers has a COP defect; otherwise, it is determined that the first COP test result indicates that the first batch of wafers does not have a COP defect: The defect distribution is concentrated in the edge area of the first wafer defect map; The defect distribution is concentrated in a central area of the first wafer defect map.
4. The wafer defect detection method according to claim 1, characterized in that: The method further comprises: When the first COP detection result indicates that the first batch of wafers has COP defects, it is determined to intercept the first batch of wafers.
5. The wafer defect detection method according to claim 1, characterized in that: Performing defect detection on each wafer in the first batch of wafers respectively to obtain a first defect detection result of the wafer includes: Performing defect detection on each of the wafers respectively to obtain a spatial defect distribution map of the wafer; A first defect detection result of the wafer is obtained according to the spatial defect distribution map.
6. The wafer defect detection method according to claim 1, characterized in that: The first defect includes at least one of the following: Cluster type defects; Micro-pattern defects of continuous target shapes; Micro-pattern defects with discontinuous target shapes.
7. The wafer defect detection method according to claim 1, characterized in that: The method further comprises: Determine, according to the first defect detection result, a second wafer in the first batch of wafers that has the first defect; removing the second wafer from the first batch of wafers to obtain a second batch of wafers; Performing quality inspection on the second batch of wafers to obtain quality inspection results of the second batch of wafers.
8. The wafer defect detection method according to claim 7, characterized in that: Performing quality inspection on the second batch of wafers to obtain quality inspection results of the second batch of wafers includes: Acquire a second wafer defect map of the second batch of wafers, wherein the second batch of wafers includes at least one wafer, and the second wafer defect map indicates COP distribution of wafers in the second batch of wafers; Obtaining a second COP test result of the second batch of wafers according to the second wafer defect map; In a case where the second COP inspection result indicates that the second batch of wafers has no COP defects, it is determined that the quality inspection result indicates that the second batch of wafers has qualified quality.
9. A wafer defect detection device, characterized in that: include: A first acquisition module is used to acquire a first wafer defect map of a first batch of wafers, wherein the first batch of wafers includes a plurality of wafers, and the first wafer defect map indicates a distribution of crystal native defects (COPs) of wafers in the first batch of wafers; A first processing module, configured to obtain a first COP detection result of the first batch of wafers according to the first wafer defect map; The second processing module is used to perform defect detection on each wafer in the first batch of wafers to obtain a first defect detection result of the wafer when the first COP detection result indicates that the first batch of wafers does not have a COP defect, wherein the first defect detection result is used to indicate whether there is a first defect on the wafer, and the first defect is a defect other than the COP defect.
10. A wafer defect detection device, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps in the wafer defect detection method as claimed in any one of claims 1 to 8.