Electronic component

Abstract

An electronic component includes an integrated circuit die having an upper surface including a plurality of pads electrically connected to a circuit of the integrated circuit die; and at least one passive element electrically connected to the plurality of pads in a welding manner.

Description

Technical Field

[0001] The present invention relates to an electronic component, and particularly to an electronic component that can reduce the circuit board area, effectively maintain electrical characteristics, improve internal power integrity, high-speed signal integrity, and radio frequency interference resistance ability. Background Art

[0002] With the progress of technology, the functions of electronic products such as wearable devices, handheld devices, Internet of Things devices, artificial intelligence devices, and wireless communication devices are becoming more and more diverse, driving a large demand for ICs. However, users' demands are becoming thinner, lighter, and more portable. In particular, many applications require ICs with strict requirements for line width / line pitch density and pay attention to production costs. Coupled with the increasing demand for homogeneous and heterogeneous integration of chips in end products, it is very important to reduce the volume of electronic devices. Among them, reducing the area of the circuit board is a key factor because the circuit board is one of the most space-consuming components in an electronic device. Reducing the area of the circuit board can not only save material costs but also improve the performance and reliability of the electronic device, such as reducing signal transmission delay and interference. Therefore, reducing the area of the circuit board is an important goal in the design and manufacture of electronic devices. Summary of the Invention

[0003] Therefore, the main object of the present invention is to provide an electronic component to increase the electrical characteristic efficiency of IC integrated packaging.

[0004] The present invention provides an electronic component, including an integrated circuit die, an upper surface of which includes a plurality of pads, and the plurality of pads are electrically connected to a circuit of the integrated circuit die; and at least one passive component, which is electrically connected to the plurality of pads in a welding manner. Brief Description of the Drawings

[0005] Figure 1 It is a schematic diagram of an electronic component according to Embodiment 1 of the present invention.

[0006] Figure 2A And Figure 2B Is Figure 1 A schematic diagram of a passive component in it.

[0007] Figure 3 Is Figure 1 A schematic diagram of an embodiment of an integrated circuit die in it.

[0008] Figure 4 It is a schematic diagram of an electronic device according to Embodiment 1 of the present invention.

[0009] Explanation of the reference numerals: 10 - electronic component; 102 - integrated circuit die; 104_1~104_n - passive components; 106 - solder pad; FG - pin; BP - input / output bump; A - area; 300 - substrate; 302 - metal layer; 304 - power and ground layer; 306 - redistribution layer; 40 - electronic device; 400 - plastic package. DETAILED DESCRIPTION

[0010] Please refer to Figure 1 , Figure 1 Schematic diagram of an electronic component 10 according to an embodiment of the present invention. The electronic component 10 can be used in electronic products such as wearable devices, handheld devices, Internet of Things devices, artificial intelligence devices, wireless communication devices, etc. It can integrate passive components to reduce the circuit board area required for electronic products. At the same time, when the electronic component 10 realizes the power supply network of the electronic product, the electronic component 10 has good electrical characteristics, which can improve the internal power integrity (PI), high-speed signal integrity (SI) and anti-radio frequency interference (RFI) capabilities. Specifically, the electronic component 10 includes an integrated circuit die 102 and passive components 104_1~104_n. A plurality of input and output bumps BP are formed on the upper surface of the integrated circuit die 102, and the input and output bumps BP are electrically connected to a plurality of pins FG through gold wires. This structure should be well known in the art. In addition, a plurality of pads 106 are formed on the upper surface of the integrated circuit die 102 for electrically connecting the passive components 104_1~104_n by welding. That is, the passive components 104_1-104_n are directly disposed on the upper surface of the integrated circuit die 102, and are electrically connected to the internal circuit of the integrated circuit die 102 through the bonding pad 106. In this case, the passive components 104_1-104_n do not need to occupy the circuit board space, which can reduce the circuit board area, and the passive components 104_1-104_n and the integrated circuit die 102 do not need to be connected through wiring or gold wires, which can effectively increase good electrical characteristics, thereby improving the internal power integrity, high-speed signal integrity and anti-radio frequency interference capability.

[0011] In short, in the electronic component 10, the passive components 104_1 to 104_n are not disposed on the circuit board and connected to the integrated circuit die 102 through circuit board traces or additional gold wires, but are directly disposed on the upper surface of the integrated circuit die 102 through the pads 106. In this case, the passive components 104_1 to 104_n and the integrated circuit die 102 are electrically connected through an extremely short path formed by the pads 106, which is beneficial to the transmission of electrical signals. Selecting different values of the passive components can also improve the anti-interference and anti-noise capabilities. Specifically, please continue to refer to Figure 2A and Figure 2B , Figure 2A and Figure 2B which are Figure 1 a partial enlarged view and a top view of a region A in [reference], showing the structure of the passive component 104_1 relative to the integrated circuit die 102. As shown in Figure 2A and Figure 2B , the passive component 104_1 is electrically connected to the integrated circuit die 102 through four pads 106. Since the pads 106 are formed on the upper surface of the integrated circuit die 102, that is, the passive component 104_1 is disposed on the integrated circuit die 102 and is electrically connected to the internal circuit of the integrated circuit die 102 through an extremely short path (formed by the pads 106), it does not occupy the circuit board space, and due to its extremely short path, the electrical characteristics can be ensured, and the internal power integrity, high-speed signal integrity, and radio frequency interference resistance can be improved.

[0012] It should be noted that Figure 2A and Figure 2B show the structure related to the passive component 104_1. The remaining passive components 104_2 to 104_n also have a similar structure, which will not be elaborated here. Furthermore, the electronic component 10 is an embodiment of the present invention. Those of ordinary skill in the art can make different modifications according to this, and are not limited thereto. For example, Figure 3 is a schematic diagram of an embodiment of the integrated circuit die 102. In this example, the electronic component 10 is used to implement a power supply chip. Then, the integrated circuit die 102 includes a substrate 300, at least one metal layer 302, a power supply and ground layer 304, and a redistribution layer 306. The metal layer 302 is disposed on the substrate 300 and is used to form a circuit. The power supply and ground layer 304 is disposed on the metal layer 302 and is used to provide power supply and ground to the internal circuit of the metal layer 302. The redistribution layer 306 is disposed between the power supply and ground layer 304 and the pads 106 and is used to connect the power supply and ground layer 304 and the pads 106. It should be noted that the redistribution layer 306 changes the contact positions of the integrated circuit die 102 through a wafer-level metal wiring process and a bump process, so that the integrated circuit die 102 can be applied to different component modules. In Figure 3In the example, it is the setting position of the passive component 104_1. Among them, the so-called wafer-level metal wiring process is to coat a protective layer on the passive component 104_1 first, then define a new wire pattern by exposure and development, and then use electroplating and etching technologies to fabricate new metal wires to connect the original circuit contacts and the new pads 106, so as to achieve the purpose of circuit redistribution. However, not limited thereto, any method that can adjust the contact positions of the integrated circuit die 102 to conform to the required passive component setting method is applicable to the present invention.

[0013] In addition, the passive components 104_1 to 104_n can be passive components such as capacitors, inductors, and resistors, and their sizes preferably conform to a 01005 specification, that is, their length × width is about 0.4 mm × 0.2 mm, but not limited thereto. In addition, in Figure 1 the setting positions of the passive components 104_1 to 104_n (or the positions of the pads 106) are close to the edge of the integrated circuit die 102, but not limited thereto. The passive components 104_1 to 104_n can also be arranged in the center or any appropriate position of the integrated circuit die 102. Furthermore, those of ordinary skill in the art can appropriately adjust the number n of the passive components 104_1 to 104_n according to the requirements of the system.

[0014] Similarly, the implementation methods, processes, materials, quantities, etc. of the integrated circuit die 102, the pads 106, the input / output bumps BP, and the pins FG are not limited either. Those of ordinary skill in the art should be able to appropriately adjust them according to the requirements of the system.

[0015] On the other hand, Figure 1 shows the basic structure of the electronic component 10. In practical applications, various packaging procedures can be adopted to protect the electronic component 10. In one embodiment, the electronic component 10 can adopt a Quad Flat Non-leaded package. Please refer to Figure 4 Figure 4 which is a schematic diagram of the electronic device 40 according to the first embodiment of the present invention. The electronic device 40 protects the Figure 1 electronic component 10 with a Quad Flat Non-leaded package, that is, uses a plastic package 400 to protect the electronic component 10. As shown in Figure 4As shown, for the quad flat no-lead package, the pin FG can be exposed under the encapsulant of the package, which can further reduce the required circuit board area. Coupled with the passive components 104_1 to 104_n of the electronic component 10 being directly disposed on the upper surface of the integrated circuit die 102, the required circuit board area can be effectively reduced. It should be noted that when using the quad flat no-lead package for the electronic component 10, those of ordinary skill in the art can appropriately adjust the process of the quad flat no-lead package to meet the requirements for disposing the passive components 104_1 to 104_n. For example, in one embodiment, before encapsulation, a space for disposing the passive components 104_1 to 104_n can be reserved, and then the passive components 104_1 to 104_n are soldered subsequently; in another embodiment, after encapsulation, holes can be opened in the plastic package 400 to dispose the passive components 104_1 to 104_n. However, no matter how the encapsulation is carried out, as long as the electronic component 10 can be protected and the passive components 104_1 to 104_n can be appropriately disposed on the integrated circuit die 102, it falls within the scope of the present invention.

[0016] In the prior art, passive components are disposed on a circuit board and are electrically connected to an integrated circuit chip through circuit board traces. Under this structure, in addition to occupying the circuit board area, design factors such as the length and width of the traces, the extension method, and the position also affect the anti-interference ability, electrical characteristics, etc. In contrast, in the present invention, the passive components are not disposed on the circuit board and connected to the integrated circuit die through circuit board traces, but are directly disposed on the integrated circuit die. Therefore, the passive components in the embodiments of the present invention do not need to occupy the circuit board space, can reduce the circuit board area, and the extremely short connection path between the passive components and the integrated circuit die can effectively maintain the electrical characteristics, thereby improving the internal power integrity, high-speed signal integrity, and radio frequency interference resistance.

[0017] In summary, by disposing the passive components on the integrated circuit die, the electronic component of the present invention can reduce the circuit board area, effectively improve good electrical characteristics, and enhance the internal power integrity, high-speed signal integrity, and radio frequency interference resistance.

[0018] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope covered by the present invention.

Claims

1. An electronic component, characterized in that: Contains: An integrated circuit die, a top surface of which includes a plurality of bonding pads, the plurality of bonding pads being electrically connected to a circuit of the integrated circuit die; and At least one passive component is electrically connected to the plurality of pads by welding.

2. The electronic component according to claim 1, wherein: The integrated circuit die includes: a substrate; At least one metal layer, disposed on the substrate, for forming the circuit; a power and ground layer disposed on the at least one metal layer for providing power and ground to the circuit; as well as A redistribution layer is disposed between the power and ground layers and the plurality of pads, and is used to connect the power and ground layers and the plurality of pads.

3. The electronic component according to claim 1, wherein: The at least one passive component is selected from a capacitor, an inductor and a resistor.

4. The electronic component according to claim 1, wherein: The size of the at least one passive component complies with a 01005 specification.

5. The electronic component according to claim 1, wherein: The electronic component is protected by a square planar pinless package.

6. The electronic component according to claim 5, characterized in that The quad planar leadless package is formed with at least one hole corresponding to the at least one connector.

7. The electronic component according to claim 1, wherein: The plurality of bonding pads are formed at the edge of the integrated circuit die.

8. The electronic component according to claim 1, wherein: The electronic component is used for supplying power to an electronic device.

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