Undervoltage locking circuit

Abstract

The invention provides an undervoltage lock-out (UVLO) circuit, which is characterized in that the undervoltage lock-out (UVLO) circuit is provided; the undervoltage locking circuit comprises a current mirror circuit, a current source, a first reference transistor, a second reference transistor and a comparison circuit. The current mirror circuit is coupled to a system high voltage. The current mirror circuit comprises a first connecting end and a second connecting end. The current source is coupled to the first connection end. The first end of the first reference transistor is coupled to the second connection end. The second end of the first reference transistor provides reference voltage. The first end of the second reference transistor is coupled to the second end of the first reference transistor. The second terminal of the second reference transistor is coupled to a system low voltage. The comparison circuit receives an input voltage and a reference voltage at the first connection end. The comparison circuit generates an undervoltage locking signal according to an input voltage and a reference voltage.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and more particularly to an undervoltage-lockout (UVLO) circuit. Background Art

[0002] Figure 1 FIG. is a schematic circuit diagram of an undervoltage-lockout (UVLO) circuit currently used in an electronic circuit. The undervoltage-lockout circuit 10 can determine whether to stop the operation of the electronic circuit according to the voltage value of the system high voltage VDD. The undervoltage-lockout circuit 10 includes resistors R1, R2, R3, transistor MP, comparator CP, and inverter IVT. The undervoltage-lockout circuit 10 uses resistors R1, R2, R3, and transistor MP to divide the system high voltage VDD to generate an input voltage VB. Comparator CP compares input voltage VB and reference voltage VREF. When the voltage value of input voltage VB is higher than the voltage value of reference voltage VREF, comparator CP provides a signal with a low voltage level. Therefore, inverter IVT provides an undervoltage-lockout signal VOUT with a high voltage level. The undervoltage-lockout signal VOUT with a high voltage level can enable the electronic circuit to continue operating. At this time, transistor MP is turned on. Therefore, resistor R1 is bypassed. The voltage value of input voltage VB rises.

[0003] When the voltage value of input voltage VB is lower than the voltage value of reference voltage VREF, comparator CP provides a signal with a high voltage level. Therefore, inverter IVT provides an undervoltage-lockout signal VOUT with a low voltage level. The undervoltage-lockout signal VOUT with a low voltage level can enable the electronic circuit to stop operating. At this time, transistor MP is turned off. Therefore, resistor R1 is not bypassed. The voltage value of input voltage VB drops. Transistor MP provides a hysteresis function.

[0004] However, the undervoltage-lockout circuit 10 uses resistors R1, R2, R3 to divide the system high voltage VDD. Therefore, the undervoltage-lockout circuit 10 has a large power consumption. If the power consumption of the undervoltage-lockout circuit 10 is to be reduced, the resistance values of resistors R1, R2, R3 need to be increased. Therefore, the layout area of resistors R1, R2, R3 is greatly increased. Therefore, how to provide an undervoltage-lockout circuit with low power consumption and low layout area is one of the research focuses of those skilled in the art. Summary of the Invention

[0005] The present invention provides an undervoltage-lockout circuit with low power consumption and low layout area.

[0006] The under-voltage lockout circuit of the present invention includes a current mirror circuit, a current source, a first reference transistor, a second reference transistor, and a comparison circuit. The current mirror circuit is coupled to the system high voltage. The current mirror circuit includes a first connection end and a second connection end. The current source is coupled to the first connection end. The first end of the first reference transistor is coupled to the second connection end. The second end of the first reference transistor provides a reference voltage. The first end of the second reference transistor is coupled to the second end of the first reference transistor. The second end of the second reference transistor is coupled to the system low voltage. The comparison circuit is coupled to the second end of the first reference transistor and the first connection end. The comparison circuit receives the input voltage at the first connection end and the reference voltage. The comparison circuit generates an under-voltage lockout signal based on the input voltage and the reference voltage.

[0007] Based on the above, the under-voltage lockout circuit generates an under-voltage lockout signal based on the input voltage at the first connection end and the reference voltage at the second end of the first reference transistor. It should be noted that the present invention uses a current mirror circuit and a current source to provide the input voltage corresponding to the system high voltage. Therefore, the under-voltage lockout circuit does not need to use multiple resistors to divide the system high voltage to generate the input voltage. In this way, the layout area and power consumption of the under-voltage lockout circuit can be significantly reduced. Description of the Drawings

[0008] Figure 1 is a circuit schematic diagram of a current under-voltage lockout circuit;

[0009] Figure 2 is a circuit schematic diagram of the under-voltage lockout circuit according to an embodiment of the present invention;

[0010] Figure 3 is a signal schematic diagram according to an embodiment of the present invention;

[0011] Figure 4 is a circuit schematic diagram of the under-voltage lockout circuit according to an embodiment of the present invention;

[0012] Figure 5 is a circuit schematic diagram of the under-voltage lockout circuit according to an embodiment of the present invention.

[0013] Description of Reference Numerals

[0014] 10, 100, 200, 300: Under-voltage lockout circuit

[0015] 110, 210, 310: Current mirror circuit

[0016] 120, 220, 320: Current source

[0017] 130, 230, 330: Comparator

[0018] 140, 240, 340: Inverting circuit

[0019] CP: Comparator

[0020] CPC: Comparison circuit

[0021] IVT: Inverter

[0022] MN1, MN2: Reference transistor

[0023] MN3, MN4: Current source transistor

[0024] MP: Transistor

[0025] MP1, MP2, MP3: Current mirror transistor

[0026] ND1: First connection terminal

[0027] ND2: Second connection terminal

[0028] R, R1, R2, R3: Resistor

[0029] SC: Comparison signal

[0030] tp0, tp1, tp2, tp3, tp4: Time point

[0031] VB: Input voltage

[0032] VDD: System high voltage

[0033] VOUT: Under-voltage lockout signal

[0034] VREF: Reference voltage

[0035] VSS: System low voltage Detailed implementation manners

[0036] Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the component symbols cited in the following description, when the same component symbols appear in different drawings, they will be regarded as the same or similar components. These embodiments are only a part of the present invention and do not disclose all the implementable manners of the present invention. More precisely, these embodiments are only examples within the scope of the patent application of the present invention.

[0037] Please refer to Figure 2 , Figure 2It is a circuit schematic diagram of an under-voltage lockout circuit shown according to an embodiment of the present invention. The under-voltage lockout circuit 100 can determine whether to stop the operation of the electronic circuit according to the voltage value of the system high voltage VDD of the electronic circuit. In this embodiment, the under-voltage lockout circuit 100 includes a current mirror circuit 110, a current source 120, reference transistors MN1, MN2, and a comparison circuit CPC. The current mirror circuit 110 is coupled to the system high voltage VDD. The current mirror circuit 110 includes a first connection end ND1 and a second connection end ND2. The current source 120 is coupled to the first connection end ND1. The current source 120 can provide a certain current value. The first end of the reference transistor MN1 is coupled to the second connection end ND2. The second end of the reference transistor MN1 provides a reference voltage VREF. The first end of the reference transistor MN2 is coupled to the second end of the reference transistor MN1. The second end of the reference transistor MN2 is coupled to the system low voltage VSS (such as ground).

[0038] In this embodiment, the comparison circuit CPC is coupled to the second end of the reference transistor MN1 and the first connection end ND1. The comparison circuit CPC receives the input voltage VB at the first connection end ND1 and the reference voltage VREF. The comparison circuit CPC generates an under-voltage lockout signal VOUT according to the input voltage VB and the reference voltage VREF.

[0039] It is worth mentioning here that the under-voltage lockout circuit 100 generates an under-voltage lockout signal VOUT according to the input voltage VB at the first connection end ND1 and the reference voltage VREF at the second end of the reference transistor MN1. It should be noted that the under-voltage lockout circuit 100 uses the current mirror circuit 110 and the current source 120 to provide the input voltage VB corresponding to the system high voltage VDD. Therefore, the under-voltage lockout circuit 100 does not need to use a plurality of resistors to divide the system high voltage VDD to generate the input voltage VB. In this way, the layout area and power consumption of the under-voltage lockout circuit 100 can be greatly reduced.

[0040] In this embodiment, the current mirror circuit 110 further includes current mirror transistors MP1, MP2. The first end of the current mirror transistor MP1 is coupled to the system high voltage VDD. The second end of the current mirror transistor MP1 is coupled to the first connection end ND1 and the control end of the current mirror transistor MP1. The first end of the current mirror transistor MP2 is coupled to the system high voltage VDD. The second end of the current mirror transistor MP2 is coupled to the second connection end ND2. The control end of the current mirror transistor MP2 is coupled to the first connection end ND1.

[0041] In this embodiment, the current mirror transistors MP1, MP2 can be implemented by P-type transistors respectively. The reference transistors MN1, MN2 can be implemented by N-type transistors respectively.

[0042] In this embodiment, the control terminals of the reference transistors MN1 and MN2 are coupled to the second connection terminal ND2. Thus, based on the coupling manner of the reference transistors MN1 and MN2, the reference transistor MN1 operates in the weak inversion region, and the reference transistor MN2 operates in the linear region. Therefore, the reference transistors MN1 and MN2 operate based on the sub-threshold current of the reference transistor MN1. In this way, the reference transistors MN1 and MN2 have very low power consumption.

[0043] In addition, the reference voltage VREF is provided by the under-voltage lockout circuit 100 itself. In other words, the under-voltage lockout circuit 100 does not need to receive an external reference voltage through a port.

[0044] To further illustrate, the voltage value of the reference voltage VREF can be determined based on the threshold voltage values of the reference transistors MN1 and MN2. Further, the reference voltage VREF can be determined by equations (1), (2), and (3).

[0045] VREF = (Vth1 - Vth2) + VT × ln(S1 / S2) …… Equation (1)

[0046] S1 = (W1 / L1) × Cox1 …… Equation (2)

[0047] S2 = (W2 / L2) × Cox2 …… Equation (3)

[0048] "Vth1" is the threshold voltage value of the reference transistor MN1. "Vth2" is the threshold voltage value of the reference transistor MN2. "VT" is the thermal voltage, approximately 0.026 volts. "S1" is the S parameter of the reference transistor MN1. "S2" is the S parameter of the reference transistor MN2. "L1" is the channel length of the reference transistor MN1. "W1" is the channel width of the reference transistor MN1. "Cox1" is the gate oxide capacitance value of the reference transistor MN1. "L2" is the channel length of the reference transistor MN2. "W2" is the channel width of the reference transistor MN2. "Cox2" is the gate oxide capacitance value of the reference transistor MN2. In addition, "ln(S1 / S2)" is the natural logarithm of S1 divided by S2.

[0049] It should be noted that, as can be seen from Equation (1), since the difference between the critical voltage value Vth1 of the reference transistor MN1 and the critical voltage value Vth2 of the reference transistor MN2 (i.e., Vth1 - Vth2) is a fixed value and changes less with temperature, the reference voltage VREF is less affected by temperature changes.

[0050] In this embodiment, the comparison circuit CPC includes a comparator 130 and an inverter circuit 140. The comparator 130 is coupled to the second end and the first connection end ND1 of the reference transistor MN1. The comparator 130 compares the input voltage VB and the reference voltage VREF to generate a comparison signal SC. Taking this embodiment as an example, the inverting input terminal of the comparator 130 is coupled to the first connection end ND1. The comparator 130 uses the inverting input terminal to receive the input voltage VB. The non-inverting input terminal of the comparator 130 is coupled to the second end of the reference transistor MN1. The comparator 130 uses the non-inverting input terminal to receive the reference voltage VREF.

[0051] The inverter circuit 140 is coupled to the comparator 130. The inverter circuit 140 generates an undervoltage lockout signal VOUT according to the comparison signal SC. Taking this embodiment as an example, the input terminal of the inverter circuit 140 receives the comparison signal SC. The inverter circuit 140 performs an inversion operation on the comparison signal SC to generate the undervoltage lockout signal VOUT.

[0052] Please refer to Figure 2 and Figure 3 , Figure 3 is a signal schematic diagram shown according to an embodiment of the present invention. In this embodiment, at time point tp0, the voltage value of the system high voltage VDD of the electronic circuit starts to rise. After time point tp0, the undervoltage lockout circuit 100 starts to operate. Therefore, the reference voltage VREF and the input voltage VB are generated. The voltage value of the input voltage VB changes following the change of the voltage value of the system high voltage VDD. Based on the current mirror circuit 110 and the current source 120, the voltage difference between the voltage value of the input voltage VB and the voltage value of the system high voltage VDD is generally maintained.

[0053] Between time point tp0 and time point tp2, the voltage value of the system high voltage VDD gradually rises. The voltage value of the input voltage VB gradually rises. However, between time point tp0 and time point tp1, the voltage value of the input voltage VB is lower than the voltage value of the reference voltage VREF. The comparator 130 provides a comparison signal SC with a high voltage level. Therefore, the inverter circuit 140 provides an undervoltage lockout signal VOUT with a low voltage level. The undervoltage lockout signal VOUT with a low voltage level can cause the electronic circuit to stop operating.

[0054] After time point tp1, the voltage value of the input voltage VB is higher than the voltage value of the reference voltage VREF. The comparator 130 provides a comparison signal SC with a low voltage level. Therefore, the inverter circuit 140 provides an undervoltage lockout signal VOUT with a high voltage level. The undervoltage lockout signal VOUT with a high voltage level enables the electronic circuit to operate. In this embodiment, when the voltage value of the input voltage VB is higher than the voltage value of the reference voltage VREF, the voltage value of the undervoltage lockout signal VOUT can follow the voltage values of the input voltage VB and the system high voltage VDD.

[0055] In some embodiments, when the voltage value of the input voltage VB is higher than the voltage value of the reference voltage VREF, the voltage value of the undervoltage lockout signal VOUT can be a fixed voltage value.

[0056] Between time point tp2 and time point tp3, the voltage value of the system high voltage VDD is stable. Therefore, the voltage value of the input voltage VB is also stable.

[0057] After time point tp3, the voltage value of the system high voltage VDD starts to decrease. The voltage value of the input voltage VB also starts to decrease. Between time point tp3 and time point tp4, the voltage value of the input voltage VB is still higher than the voltage value of the reference voltage VREF. The comparator 130 provides a comparison signal SC with a low voltage level. Therefore, the inverter circuit 140 provides an undervoltage lockout signal VOUT with a high voltage level.

[0058] After time point tp4, the voltage value of the system high voltage VDD drops below the voltage value of the reference voltage VREF. Therefore, the comparator 130 provides a comparison signal SC with a high voltage level. Therefore, the inverter circuit 140 provides an undervoltage lockout signal VOUT with a low voltage level.

[0059] In this embodiment, the comparator 130 is a comparator with a hysteresis function. Therefore, when the voltage value of the input voltage VB oscillates at the voltage value of the reference voltage VREF, the comparator 130 can slow down the oscillation of the comparison signal SC between the high voltage level and the low voltage level.

[0060] In some embodiments, the comparator 130 uses the non-inverting input terminal to receive the input voltage VB. The comparator 130 uses the inverting input terminal to receive the reference voltage VREF. Therefore, in some embodiments, the inverter circuit 140 can be omitted.

[0061] Please refer to Figure 4 , Figure 4It is a circuit schematic diagram of an under-voltage lockout circuit shown in an embodiment of the present invention. In this embodiment, the under-voltage lockout circuit 200 includes a current mirror circuit 210, a current source 220, reference transistors MN1, MN2, and a comparison circuit CPC. The current mirror circuit 210 includes a first connection terminal ND1, a second connection terminal ND2, and current mirror transistors MP1, MP2, MP3. The first end of the current mirror transistor MP1 is coupled to the system high voltage VDD. The second end of the current mirror transistor MP1 is coupled to the first connection terminal ND1 and the control end of the current mirror transistor MP1. The first end of the current mirror transistor MP2 is coupled to the system high voltage VDD. The second end of the current mirror transistor MP2 is coupled to the current source 220. The control end of the current mirror transistor MP2 is coupled to the first connection terminal ND1. The first end of the current mirror transistor MP3 is coupled to the system high voltage VDD. The second end of the current mirror transistor MP3 is coupled to the second connection terminal ND2. The control end of the current mirror transistor MP3 is coupled to the first connection terminal ND1.

[0062] In this embodiment, the current source 220 includes current source transistors MN3, MN4, and a resistor R. The first end of the current source transistor MN3 is coupled to the first connection terminal ND1. The control end of the current source transistor MN3 is coupled to the second end of the current mirror transistor MP2. The resistor R is coupled between the second end of the current source transistor MN3 and the system low voltage VSS. The first end of the current source transistor MN4 is coupled to the second end of the current mirror transistor MP2, the control end of the current source transistor MN3, and the control end of the current source transistor MN4. The second end of the current source transistor MN4 is coupled to the system low voltage VSS.

[0063] In this embodiment, the first end of the reference transistor MN1 is coupled to the second connection terminal ND2. The second end of the reference transistor MN1 provides a reference voltage VREF. The control end of the reference transistor MN1 is coupled to the second connection terminal ND2. The first end of the reference transistor MN2 is coupled to the second end of the reference transistor MN1. The second end of the reference transistor MN2 is coupled to the system low voltage VSS. The control end of the reference transistor MN2 is coupled to the second connection terminal ND2. The reference transistor MN1 operates in the weak inversion region. The reference transistor MN2 operates in the linear region.

[0064] In this embodiment, the current mirror transistors MP1, MP2 and the current source transistors MN3, MN4 can form a stacked current mirror. Therefore, the voltage value of the input voltage VB can accurately follow the voltage value of the system high voltage VDD.

[0065] In this embodiment, the comparison circuit CPC includes a comparator 230 and an inverter circuit 240. The implementation manners of the comparator 230 and the inverter circuit 240 are as Figure 2The implementation manners of the comparator 130 and the inverter circuit 140 shown are substantially the same, so they will not be restated here.

[0066] In this embodiment, the current mirror transistors MP1, MP2, and MP3 can be implemented by P-type transistors respectively. The reference transistors MN1, MN2 and the current source transistors MN3, MN4 can be implemented by N-type transistors respectively.

[0067] Please refer to Figure 5 , Figure 5 FIG. is a circuit schematic diagram of an under-voltage lockout circuit according to an embodiment of the present invention. In this embodiment, the under-voltage lockout circuit 300 includes a current mirror circuit 310, a current source 320, reference transistors MN1, MN2, and a comparison circuit CPC. The current mirror circuit 310 includes a first connection end ND1, a second connection end ND2, and current mirror transistors MP1, MP2, MP3. The current source 320 includes current source transistors MN3, MN4, and a resistor R. The comparison circuit CPC includes a comparator 330 and an inverter circuit 340. The implementation manners of the current mirror circuit 310, the current source 320, and the comparison circuit CPC are substantially the same as those of the current mirror circuit 210, the current source 220, and the comparison circuit CPC shown in Figure 3 so they will not be restated here.

[0068] In this embodiment, the first end of the reference transistor MN1 is coupled to the second connection end ND2. The second end of the reference transistor MN1 provides a reference voltage VREF. The control end of the reference transistor MN1 is coupled to the second end of the current mirror transistor MP2. The first end of the reference transistor MN2 is coupled to the second end of the reference transistor MN1. The second end of the reference transistor MN2 is coupled to the system low voltage VSS. The control end of the reference transistor MN2 is coupled to the second end of the current mirror transistor MP2. The reference transistor MN1 operates in the weak inversion region. The reference transistor MN2 operates in the linear region.

[0069] In summary, the under-voltage lockout circuit of the present invention generates an under-voltage lockout signal based on the input voltage at the first connection end and the reference voltage at the second end of the first reference transistor. It should be noted that the under-voltage lockout circuit uses a current mirror circuit and a current source to provide an input voltage corresponding to the system high voltage. Therefore, the under-voltage lockout circuit does not need to use a plurality of resistors to divide the system high voltage to generate the input voltage. In this way, the layout area and power consumption of the under-voltage lockout circuit can be greatly reduced. In addition, the reference voltage is provided by the under-voltage lockout circuit itself. In this way, the under-voltage lockout circuit does not need to receive a reference voltage from the outside through a port.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An undervoltage lockout circuit, characterized in that: The under-voltage lockout circuit comprises: A current mirror circuit is coupled to the system high voltage and includes a first connection terminal and a second connection terminal; a current source, coupled to the first connection terminal; a first reference transistor, wherein a first terminal of the first reference transistor is coupled to the second connection terminal, and a second terminal of the first reference transistor provides a reference voltage; a second reference transistor, a first terminal of the second reference transistor being coupled to a second terminal of the first reference transistor, and a second terminal of the second reference transistor being coupled to a system low voltage; and The comparison circuit is coupled to the second terminal of the first reference transistor and the first connection terminal, and is configured to receive an input voltage at the first connection terminal and the reference voltage, and generate an under-voltage lockout signal according to the input voltage and the reference voltage.

2. The under-voltage lockout circuit according to claim 1, characterized in that: The first reference transistor operates in a weak inversion region, and The second reference transistor operates in a linear region.

3. The under-voltage lockout circuit according to claim 1, characterized in that: The voltage value of the reference voltage is determined based on the threshold voltage value of the first reference transistor and the threshold voltage value of the second reference transistor.

4. The under-voltage lockout circuit according to claim 1, characterized in that: The current mirror circuit further includes: A first current mirror transistor, wherein a first terminal of the first current mirror transistor is coupled to the system high voltage, and a second terminal of the first current mirror transistor is coupled to the first connection terminal and a control terminal of the first current mirror transistor; and A second current mirror transistor, wherein a first terminal of the second current mirror transistor is coupled to the system high voltage, a second terminal of the second current mirror transistor is coupled to the second connection terminal, and a control terminal of the second current mirror transistor is coupled to the first connection terminal.

5. The under-voltage lockout circuit according to claim 4, characterized in that: The control end of the first reference transistor and the control end of the second reference transistor are coupled to the second connection end.

6. The under-voltage lockout circuit according to claim 1, characterized in that: The current mirror circuit further includes: A first current mirror transistor, wherein a first terminal of the first current mirror transistor is coupled to the system high voltage, and a second terminal of the first current mirror transistor is coupled to the first connection terminal and the first current mirror transistor; a second current mirror transistor, wherein a first terminal of the second current mirror transistor is coupled to the system high voltage, a second terminal of the second current mirror transistor is coupled to the current source, and a control terminal of the second current mirror transistor is coupled to the first connection terminal; and A third current mirror transistor, wherein a first end of the third current mirror transistor is coupled to the system high voltage, a second end of the third current mirror transistor is coupled to the second connection end, and a control end of the third current mirror transistor is coupled to the first connection end.

7. The under-voltage lockout circuit according to claim 6, characterized in that: The control end of the first reference transistor and the control end of the second reference transistor are coupled to the second connection end.

8. The under-voltage lockout circuit according to claim 6, characterized in that: The current source comprises: A first current source transistor, wherein a first terminal of the first current source transistor is coupled to the first connection terminal, and a control terminal of the first current source transistor is coupled to a second terminal of the second current mirror transistor; a resistor coupled between the second terminal of the first current source transistor and the system low voltage; and A second current source transistor, wherein a first end of the second current source transistor is coupled to a second end of the second current mirror transistor, a control end of the first current source transistor and a control end of the second current source transistor, and a second end of the second current source transistor is coupled to the system low voltage.

9. The under-voltage lockout circuit according to claim 8, characterized in that: The control terminal of the first reference transistor and the control terminal of the second reference transistor are coupled to the second terminal of the second current mirror transistor.

10. The under-voltage lockout circuit according to claim 1, characterized in that: The comparison circuit comprises: a comparator coupled to the second terminal of the first reference transistor and the first connection terminal, configured to compare the input voltage and the reference voltage to generate a comparison signal; and The inverting circuit is coupled to the comparator and configured to generate the under-voltage lockout signal according to the comparison signal.

Images