High-speed low-power-consumption dynamic comparator
Through the clock control of the dynamic preamplifier and bias unit, the kickback noise and power consumption problems of the dynamic comparator are solved, and the high-speed and low-power comparator design is realized, which improves the performance of the analog-to-digital converter.
Patent Information
- Application Number
- CN202510312209.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-07-01
AI Technical Summary
Existing dynamic comparators have problems with kickback noise and high power consumption, especially traditional preamps still consume current when they are not operating, affecting circuit speed and performance.
The dynamic preamplifier unit and the dynamic bias unit are used to control the clock signal to turn off in the reset phase, and only work in the comparison phase. Combined with the positive feedback structure of the latch unit, the input signal and latch voltage changes are isolated, thereby reducing kickback noise and reducing power consumption.
It effectively reduces the impact of kickback noise, improves the comparison speed of the circuit and reduces power consumption, and improves the performance of the water-type analog-to-digital converter.
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Figure CN120238103A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a high-speed dynamic comparator Background Art
[0002] With the continuous development of semiconductor technology, integrated circuits have become an important pillar of the information industry. Integrated circuits can complete functions such as information collection, amplification, comparison, transformation, transmission, and power supply, and will play an important role in modern information systems such as information sensing, communication, processing, control, and use. Digital information is easy to store and transmit, while sound, light, heat, electricity, force and other information in the actual physical world are all analog information. In order to connect two different worlds and realize the mutual conversion of analog information and digital information, a data converter was proposed. The comparator is an important component of a high-performance data converter, and its performance has an important impact on the performance of the entire circuit.
[0003] Comparators can be divided into open-loop comparators and dynamic comparators according to their working modes. An open-loop comparator is an operational transconductance amplifier that uses an open-loop configuration. Its characteristic is that the amplifier is not compensated to obtain a higher low-frequency gain and a larger bandwidth. Its working characteristics are fast first and slow later, that is, at the beginning, due to its open-loop characteristics, the output will be established quickly, but when it is close to the ideal value to be amplified, it will undergo a small signal establishment process, so that the output establishment speed slows down. And because its structure is an operational amplifier, it needs to consume static current, which will generate a large power consumption; at the same time, it is affected by bandwidth and is not suitable for high-speed design. The dynamic amplifier is the opposite of the open-loop amplifier. Its components are usually latches, which are composed of back-to-back inverters. The working characteristics are slow first and fast later, that is, at the beginning, the two outputs will be close, and the differential output voltage will increase slowly. Then, as the output voltage increases, the positive feedback circuit formed by the back-to-back inverters starts to work, thereby further accelerating the differential output voltage. Because it contains an inverter circuit, its output has only a low-resistance path to the power supply or ground in a stable state, and the power supply and ground are high-resistance, which means that it does not consume static current and has low power consumption. Dynamic comparators are widely used for their fast response speed and low static power consumption.
[0004] There are two relatively serious problems with ordinary single-stage dynamic comparators, namely offset and kickback noise. The offset of the latch is generally large, and the kickback noise is caused by the large rail-to-rail change range at the output end. Through the gate-drain parasitic capacitance coupling of the input transistors, it will affect the voltage of the upper plate of the capacitor array. Since one end of the output converges to the power supply and the other end goes to ground, the coupling effects of the two on the capacitor array are not consistent, resulting in a differential voltage error, which is manifested in the form of noise. The introduction of the preamplifier stage can effectively alleviate the above two non-ideal effects. However, the existing preamplifier will continue to work even when the comparator is not working, increasing the overall power consumption, and the gain of the existing amplifier circuit is low, affecting the speed of the circuit. Summary of the Invention
[0005] In view of the above problems, the present invention proposes a high-speed dynamic comparator to solve the problems of obvious kickback noise generated by the comparator and increased power consumption caused by the introduction of a preamplifier in the related art.
[0006] To achieve the above object, the present invention adopts the following technical solutions:
[0007] A high-speed dynamic comparator, comprising:
[0008] A latch unit, including a pair of back-to-back inverters and four reset transistors. The four reset transistors restore the circuit during the reset stage, and the back-to-back inverters generate an output signal pair through positive feedback during the comparison stage;
[0009] A dynamic preamplifier unit, including an input differential pair and a control transistor. The control transistor is controlled to be turned off by a clock control signal during the reset stage to reduce power consumption, and the input transistor converts the input voltage into current during the comparison stage;
[0010] A dynamic bias unit, which is controlled by a clock signal to be turned off during the reset stage and turned on by the clock signal during the comparison stage to provide a bias current for the circuit.
[0011] The pair of back-to-back inverters includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is connected to the gate of the third transistor as the first output terminal of the latch unit, the gate of the second transistor is connected to the gate of the fourth transistor as the second output terminal of the latch stage, the drain of the first transistor is connected to the drain of the first reset transistor and the drain of the third transistor, the source of the first transistor is connected to a reference voltage, the drain of the second transistor is connected to the drain of the second reset transistor and the drain of the third transistor, the source of the second transistor is connected to a reference voltage, the source of the third transistor is connected to the drain of the third reset transistor, and the source of the fourth transistor is connected to the drain of the fourth reset transistor.
[0012] The four reset transistors include: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gates of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected to a clock control signal. The sources of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected to a reference voltage. The drain of the fifth transistor is connected to the drain of the first transistor. The drain of the sixth transistor is connected to the drain of the second transistor. The drain of the seventh transistor is connected to the source of the third transistor. The drain of the eighth transistor is connected to the source of the fourth transistor.
[0013] The input differential pair includes: a ninth transistor and a tenth transistor. The gate of the ninth transistor is connected to the input voltage, and the source is grounded. The tenth transistor is connected to the input voltage, and the source is grounded.
[0014] The control transistors include: an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is connected to the clock signal, the source is connected to the drain of the ninth transistor, and the drain is connected to the source of the third transistor. The twelfth transistor is connected to the clock signal, the source is connected to the drain of the tenth transistor, and the drain is connected to the source of the fourth transistor.
[0015] The dynamic bias unit includes: a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The gate of the thirteenth transistor is connected to the clock signal, the source is grounded, and the drain is connected to the sources of the fourteenth transistor and the fifteenth transistor. The gate of the fourteenth transistor is connected to the drain of the fourteenth transistor, and the gate of the fifteenth transistor is connected to the gate of the fifteenth transistor.
[0016] The first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.
[0017] The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS transistors.
[0018] The ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors.
[0019] The beneficial effect of the present invention is that a dynamic preamplifier circuit is used to replace the traditional preamplifier. The dynamic preamplifier only works in the comparison stage to convert the input voltage into current, which can effectively reduce power consumption. And through the isolation of the amplifier, the voltage change of the latch unit during operation cannot affect the input signal through capacitive coupling, effectively reducing the impact of kickback noise. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 is a structural diagram of the high-speed and low-power dynamic comparator proposed in this application;
[0021] Figure 2 Schematic diagram of the equivalent circuit in the reset stage of the high-speed and low-power dynamic comparator proposed in this application;
[0022] Figure 3 Schematic diagram of the equivalent circuit in the comparison stage of the high-speed and low-power dynamic comparator proposed in this application;
[0023] Figure 4 Schematic diagram of a traditional dynamic comparator.
[0024] Figure 5 Transient simulation diagram of the input waveform of a traditional dynamic comparator.
[0025] Figure 6 Transient simulation diagram of the input waveform of the high-speed and low-power dynamic comparator proposed in this application. Specific implementation manners
[0026] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific implementations.
[0027] In an embodiment of this application, a high-speed dynamic comparator connects nodes X and Y to the output terminals of a dynamic preamplifier. The gates of NMOS transistors M3 and M4 are connected to a clock signal CLK. The clock signal is used to control NMOS transistors M10 and M11 to turn off during the reset stage, so that the dynamic preamplifier does not work during the reset stage to reduce power consumption. During the comparison stage, the clock signal is used to control NMOS transistors M3 and M4 to conduct. The dynamic preamplifier converts the input signal into a current, and the current pulls down the voltages of nodes X and Y. The gates and drains of NMOS transistors M6 and M7 and node X are connected to form a diode. By changing the voltage of node X, the gate voltage of the diode-connected NMOS transistor changes, and the current flowing through the transistor changes. Through the action of the two currents, the voltage changes of nodes X and Y are accelerated, providing a larger voltage difference for the latch unit to work, thereby improving the comparison speed. At the same time, nodes X and Y are isolated from the input signal by NMOS transistors M3 and M4, which can effectively suppress kickback noise. The latch unit adopts a comparison circuit structure with a positive feedback structure formed by two inverters connected back-to-back cross-coupled, which improves the circuit comparison speed.
[0028] Figure 1 The high-speed and low-power dynamic comparator proposed in this application includes a latch unit, a dynamic preamplifier unit, and a dynamic bias unit. The clock signal CLK is used to control the dynamic preamplifier unit and the dynamic bias unit to make them not work during the reset stage to reduce power consumption. The output terminals of the dynamic preamplifier unit and the dynamic bias unit are connected to the input terminals of the latch. During the comparison stage, a larger input voltage difference is provided for the latch unit to improve the comparison speed, thereby realizing a high-speed dynamic comparator.
[0029] The dynamic preamplifier unit includes: NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, and NMOS transistor M4. The gate of NMOS transistor M1 is connected to the input signal VIN, the source of NMOS transistor M1 is grounded, the drain of NMOS transistor M1 is connected to the source of NMOS transistor M3, the gate of NMOS transistor M2 is connected to the input signal VIP, the source of NMOS transistor M2 is grounded, the drain of NMOS transistor M2 is connected to the source of NMOS transistor M4, the gate of NMOS transistor M3 is connected to the clock signal CLK, the drain of NMOS transistor M3 is connected to the input node X of the latch, the gate of NMOS transistor M4 is connected to the clock signal CLK, and the drain of NMOS transistor M4 is connected to the input node Y of the latch.
[0030] The dynamic bias unit includes: NMOS transistor M5, NMOS transistor M6, and NMOS transistor M7. The gate of NMOS transistor M5 is connected to the clock signal CLK, the source of NMOS transistor M5 is connected to the ground, the drain of NMOS transistor M5 is connected to the source of NMOS transistor M6 and the source of NMOS transistor M7, the gate of NMOS transistor M6 is connected to the drain of NMOS transistor M6 and the input node X of the latch, and the gate of NMOS transistor M7 is connected to the drain of NMOS transistor M7 and the input node Y of the latch.
[0031] The latch unit includes: NMOS transistor M8, NMOS transistor M9, PMOS transistor M10, PMOS transistor M11, PMOS transistor M12, PMOS transistor M13, PMOS transistor M14, and PMOS transistor M15. The gate of NMOS transistor M8 is connected to the gate of PMOS transistor M10, the drain of NMOS transistor M9, the drain of PMOS transistor M11, and the drain of PMOS transistor M12. The source of NMOS transistor M8 is connected to the drain of PMOS transistor M14. The gate of NMOS transistor M9 is connected to the gate of PMOS transistor M11, the drain of NMOS transistor M8, the drain of PMOS transistor M10, and the drain of PMOS transistor M13. The source of NMOS transistor M9 is connected to the drain of PMOS transistor M15. The sources of PMOS transistor M10, PMOS transistor M11, PMOS transistor M12, PMOS transistor M13, PMOS transistor M14, and PMOS transistor M15 are connected to the reference voltage.
[0032] Further, in the dynamic preamplifier unit, the gates of NMOS transistors M3 and M4 are connected to the clock signal CLK. NMOS transistors M3 and M4 are controlled by the clock signal CLK, enabling the preamplifier unit to operate only in the comparison stage, reducing the power consumption of the circuit. Meanwhile, in the comparison stage, NMOS transistors M3 and M4 play an isolation role, preventing the input signal from being affected by the voltage change of the latch, and reducing the kickback noise. NMOS transistors M1 and M2 convert the input voltage signal into current in the comparison stage to more quickly pull down the high level of node X, providing a larger voltage difference for the latch during operation and improving the comparison speed of the circuit.
[0033] Further, in the dynamic biasing unit, NMOS transistor M5 is controlled by the clock signal CLK to provide current only in the comparison stage, reducing the power consumption of the circuit. The gate of NMOS transistor M6 is connected to the drain of NMOS transistor M6 and the input node X of the latch. The gate of NMOS transistor M7 is connected to the drain of NMOS transistor M7 and the input node Y of the latch. NMOS transistors M6 and M7 are connected in diode configuration. When nodes X and Y change, the leakage current passing through NMOS transistors M6 and M7 changes, and the change in the leakage current causes the voltage change speed of nodes X and Y to change, providing a larger voltage difference for the latch during operation and improving the comparison speed of the circuit.
[0034] Further, in the latch unit, PMOS transistors M12, M13, M14, and M15 are controlled by the clock signal. When the clock signal is at a low level, PMOS transistors M12, M13, M14, and M15 reset the circuit. PMOS transistors M12 and M13 reset the circuit nodes X and Y to a high level, and PMOS transistors M14 and M15 reset the output terminal of the latch to a high level. When the clock signal is at a high level, the latch enters the comparison stage. As the dynamic biasing unit and the dynamic preamplifier operate, the high levels of nodes X and Y are pulled down, causing the latch to enter the normal operating state. The latch forms a positive feedback through a pair of back-to-back connected inverters to accelerate the comparison speed and obtain the output result.
[0035] As Figure 2 shown, in the reset stage, the clock signal is at a low level, the output terminal of the latch and the input nodes X and Y are reset to a high level, and the dynamic biasing unit and the dynamic preamplifier stop operating, reducing the power consumption of the circuit.
[0036] As Figure 3As shown, in the comparison stage, the clock signal is at a high level and the circuit starts the comparison operation. When the input signal VIN is greater than VIP, the drain currents I flowing through NMOS transistor M1 and NMOS transistor M2 D = gm 1,2 *v in . At this time, since the input signal VIN is greater than VIP, the drain current I flowing through NMOS transistor M1 D1 is greater than the drain current I flowing through NMOS transistor M2 D2 . At the start of the comparison stage, the drain currents I D1 and I D2 extract charges from nodes X and Y, starting to pull down the levels of nodes X and Y. The voltage changes of nodes X and Y are V X,Y = I D1,2 / C X,Y , where C X,Y is the capacitance at nodes X and Y. The drain current I D1 flowing through NMOS transistor M1 is greater than the drain current I D2 flowing through NMOS transistor M2, causing the voltage change of node X to be greater than that of node Y. For the diode-connected NMOS transistors M6 and M7, when starting to work, both nodes X and Y are at a high level, and the drain currents flowing through NMOS transistors M6 and M7 are both I SS / 2, where I SS is the tail current provided for NMOS transistor M5. The drain currents of NMOS transistors M6 and M7 also extract charges from nodes X and Y, accelerating the comparison speed. When the voltage drop values of nodes X and Y reach the threshold voltages of NMOS transistors M8 and M9,
[0037] NMOS transistors M8 and M9 turn on, and the drain currents of NMOS transistors M8 and M9 start to extract charges from the output terminal, causing the output terminal voltage to start to drop from a high level. When the output terminal voltage drops to the threshold voltages of PMOS transistors M10 and M11, PMOS transistors M10 and M11 turn on, and the latch unit starts to work, and a positive feedback loop formed by NMOS transistors M8 and M9, PMOS transistors M10 and M11 quickly performs the comparison to obtain the comparison result.
[0038] As Figure 4 shown, Figure 4 it is a traditional dynamic comparator.
[0039] As Figure 5 shown, when the traditional dynamic comparator performs the comparison, the voltage change during the comparison of the internal circuit is coupled to the input signal through the capacitance of the input transistor, resulting in the input signal being affected by a relatively large kickback noise as Figure 5 shown.
[0040] As Figure 6 shown, from the transient simulation results of the circuit, it can be seen that while the high-speed dynamic comparator quickly completes the comparison, it reduces the impact of kickback noise and obtains a good input signal. In the use of a pipelined analog-to-digital converter, the high-speed dynamic comparator of the present application can obtain an input signal that is not affected by kickback noise, improving the performance of the pipelined analog-to-digital converter.
[0041] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a commodity or system including a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such commodity or system. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the commodity or system including said element. "Substantially" means within an acceptable error range, and those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect.
[0042] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, it generally includes the plural of the corresponding term. Similarly, the phrases "comprising" and "including" shall be construed as inclusive rather than exclusive. Likewise, the term "including" and "or" shall be construed as inclusive, unless such construction is expressly prohibited herein. Where the term "example" is used in this specification, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or extensive.
Claims
1. A high-speed, low-power dynamic comparator, characterized in that: include: A latch unit, comprising a pair of back-to-back inverters and four reset tubes, wherein the four reset tubes restore the circuit in a reset phase, and the back-to-back inverters generate an output signal pair through positive feedback in a comparison phase; A dynamic preamplifier unit includes an input differential pair and a control transistor, wherein the control transistor is turned off by a clock control signal in a reset phase to reduce power consumption, and the input transistor converts the input voltage into a current in a comparison phase; The dynamic bias unit is controlled by a clock signal to be closed in the reset phase and is controlled by a clock signal to be opened in the comparison phase to provide a bias current for the circuit.
2. The high-speed, low-power dynamic comparator according to claim 1, characterized in that: The pair of back-to-back inverters include: a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is connected to the gate of the third transistor as the first output end of the latch unit, the gate of the second transistor is connected to the gate of the fourth transistor as the second output end of the latch level, the drain of the first transistor is connected to the drain of the first reset tube and the drain of the third transistor, the source of the first transistor is connected to a reference voltage, the drain of the second transistor is connected to the drain of the second reset tube and the drain of the third transistor, the source of the second transistor is connected to the reference voltage, the source of the third transistor is connected to the drain of the third reset tube, and the source of the fourth transistor is connected to the drain of the fourth reset tube.
3. The high-speed, low-power dynamic comparator according to claim 2, characterized in that: The four reset transistors include: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the fifth transistor, the gate of the sixth transistor, the gate of the seventh transistor, and the gate of the eighth transistor are connected to a clock control signal, the source of the fifth transistor, the source of the sixth transistor, the source of the seventh transistor, and the source of the eighth transistor are connected to a reference voltage, the drain of the fifth transistor is connected to the drain of the first transistor, the drain of the sixth transistor is connected to the drain of the second transistor, the drain of the seventh transistor is connected to the source of the third transistor, and the drain of the eighth transistor is connected to the source of the fourth transistor.
4. The high-speed, low-power dynamic comparator according to claim 3, characterized in that: The input differential pair includes: a ninth transistor and a tenth transistor, wherein the gate of the ninth transistor is connected to the input voltage and the source is grounded, and the tenth transistor is connected to the input voltage and the source is grounded.
5. The high-speed, low-power dynamic comparator according to claim 4, characterized in that: The control transistor includes: an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected to the clock signal, the source is connected to the drain of the ninth transistor, and the drain is connected to the source of the third transistor; the twelfth transistor is connected to the clock signal, the source is connected to the drain of the tenth transistor, and the drain is connected to the source of the fourth transistor.
6. The high-speed, low-power dynamic comparator according to claim 5, characterized in that: The dynamic bias unit includes: a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, the gate of the thirteenth transistor is connected to the clock signal, the source is grounded, the drain is connected to the source of the fourteenth transistor and the source of the fifteenth transistor, the gate of the fourteenth transistor is connected to the drain of the fourteenth transistor, and the gate of the fifteenth transistor is connected to the gate of the fifteenth transistor.
7. The high-speed, low-power dynamic comparator according to claim 2, characterized in that: The first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors.
8. The high-speed, low-power dynamic comparator according to claim 3, characterized in that: The fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are PMOS transistors.
9. The high-speed, low-power dynamic comparator according to any one of claims 4 to 6, characterized in that: The ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the eleventh transistor, and the twelfth transistor are NMOS transistors.