A level shifter circuit, a high-speed digital-to-analog converter, and a high-speed analog-to-digital converter

Abstract

The application discloses a kind of level shifter circuit, high-speed digital-to-analog converter and high-speed analog-to-digital converter, level shifter circuit includes MOS tube PM1b, MOS tube PM2b, MOS tube PM2a, MOS tube PM1a, current mode logic unit and clocked latch, the source of MOS tube PM1b, MOS tube PM2b, MOS tube PM2a and MOS tube PM1a is connected to voltage VDDA, the gate of MOS tube PM2b and the gate of MOS tube PM2a are interconnected, the drain of MOS tube PM1b and the drain of MOS tube PM2b are connected, the drain of MOS tube PM2a and the drain of MOS tube PM1a are connected.The current mode logic unit includes MOS tube NM2b, MOS tube NM2a, MOS tube NM1b, MOS tube NM1a, current source IB, resistance R1b, resistance R1a, MOS tube PM3b, MOS tube PM3a, MOS tube NM3b, MOS tube NM3a and first inverter.The high-voltage MOS tube NM3a or high-voltage MOS tube NM3b with gate bias at a suitable potential VBN isolates the upper and lower low-voltage devices, so that the low-voltage devices do not appear overvoltage process, solve the problem that existing level shifter uses low-voltage devices prone to overvoltage, reduce the production cost of level shifter.

Description

A level shifter circuit, a high-speed digital-to-analog converter, and a high-speed analog-to-digital converter. Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to a level shifter circuit, a high-speed digital-to-analog converter, and a high-speed analog-to-digital converter. Background Technology

[0002] Level shifter circuits are crucial components of high-speed digital-to-analog converter (DAC) and analog-to-digital converter (ADC) chips, used to enable data transmission between different power domains. As shown in Figure 1, in a high-speed ADC, the digital signal output from the quantizer, after calibration and filtering, is shifted along with the synchronization clock to the power domain of the high-speed serial port via a level shifter, and finally converted into a serial signal for off-chip output. In a high-speed DAC, the input data, after being received by the receiver, is shifted along with the synchronization clock to the power domain of the decoding logic, latches, and current source switches via a level shifter, controlling the current flow of each current source unit.

[0003] In existing technologies, level shifter circuits operate between the power supply voltage and ground. However, since the voltage difference between the power supply voltage and ground typically exceeds the standard operating voltage of low-voltage MOSFETs, most existing level shifters are implemented using high-voltage MOSFETs, which undoubtedly increases the production cost of level shifters. Furthermore, because the cutoff frequency of high-voltage MOSFETs is much lower than that of low-voltage MOSFETs, it also limits the ability of level shifters to achieve higher data transmission rates.

[0004] Therefore, a new technological solution is needed. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a level shifter circuit, a high-speed digital-to-analog converter, and a high-speed analog-to-digital converter to at least solve the problems existing in the use of high-voltage MOSFETs in existing level shifters.

[0006] The embodiments of the present invention provide the following technical solutions:

[0007] This invention provides a level shifter circuit, including MOSFET PM1b, MOSFET PM2b, MOSFET PM2a, MOSFET PM1a, a current-mode logic unit, and a clocked latch. The sources of MOSFETs PM1b, PM2b, PM2a, and PM1a are all connected to voltage VDDA. The gates of MOSFETs PM2b and PM2a are interconnected. The drains of MOSFETs PM1b and PM2b are connected, and the drains of MOSFETs PM2a and PM1a are connected.

[0008] The current-mode logic unit includes MOSFET NM2b, MOSFET NM2a, MOSFET NM1b, MOSFET NM1a, current source IB, resistor R1b, resistor R1a, MOSFET PM3b, MOSFET PM3a, MOSFET NM3b, MOSFET NM3a and a first inverter;

[0009] The drain of the MOS transistor NM2b is connected to the drain of the MOS transistor PM1b, the source is connected to the drain of the MOS transistor NM1b, and the gate is connected to the gate of the MOS transistor NM2a1 and then connected to the clock signal CLKA, the gate of the MOS transistor PM2b, and the gate of the MOS transistor PM2a1, respectively.

[0010] The drain of the MOS transistor NM2a is connected to the drain of the MOS transistor PM1a, and the source is connected to the drain of the MOS transistor NM1a.

[0011] The gate of the MOSFET NM1a is connected to the input signal DA and the gate of the MOSFET PM1a, respectively. The source of the MOSFET NM1b is connected to the source of the MOSFET NM1b and then connected to the voltage VSSA through the current source IB. The gate of the MOSFET NM1b is connected to the input signal DA and the gate of the MOSFET PM1b, respectively.

[0012] The source of the MOS transistor PM3b is connected to the voltage VDDB through the resistor R1b, and the gate is connected to the gate of the MOS transistor PM3a.

[0013] The source of the MOS transistor PM3a is connected to the voltage VDDB through the resistor R1a, and the drain is connected to the drain of the MOS transistor NM3a to form a node VON.

[0014] The source of the MOS transistor NM3a is connected to the drain of the MOS transistor NM2a, and the gate is connected to the bias voltage VBN and the voltage VSSA, respectively.

[0015] The gate of the MOS transistor NM3b is connected to the bias voltage VBN and the voltage VSSA, respectively. The drain is connected to the drain of the MOS transistor PM3b to form node VOP. The source of the MOS transistor NM3b is connected to the drain of the MOS transistor NM2b.

[0016] The first inverter operates between the voltage VDDB and the voltage VSSB, and its input is connected to the clock signal CLKB. Its output is connected between the gates of the MOS transistor PM3b and the MOS transistor PM3a, and to the clock latch. The clock latch is also connected to the node VOP and the node VON.

[0017] Furthermore, the gate of the MOS transistor NM1b is connected to the input signal DA via a second inverter.

[0018] Furthermore, MOSFETs NM3b and NM3a are high-voltage MOSFETs, while MOSFETs PM1b, PM2b, PM2a, PM1a, NM2b, NM2a, NM1b, NM1a, PM3b, and PM3a are all low-voltage MOSFETs.

[0019] Furthermore, the difference between the bias voltage and the voltage VDDA is less than the threshold voltage of the MOS transistor NM3a or the MOS transistor NM3b.

[0020] Furthermore, the clock-controlled latch includes MOSFET NM4, MOSFET PM4, MOSFET PM5a, MOSFET PM5b, MOSFET NM5a, and MOSFET NM5b;

[0021] The gate of the MOS transistor NM4 is connected to the output of the first inverter, and the source is connected to the voltage VSSB.

[0022] The gate of the MOS transistor PM4 is connected to the gate of the MOS transistor NM4, the source is connected to the voltage VDDB, and the drain is connected to the source of the MOS transistor NM5a.

[0023] The gate of the MOS transistor NM5a is connected to the drain of the MOS transistor PM5b and the gate of the MOS transistor PM5a, respectively. The drain is connected to the drain of the MOS transistor PM5a, the gate of the MOS transistor PM5b, and node VON, respectively. The source is connected to the source of the MOS transistor NM5b and then to the drain of the MOS transistor NM4.

[0024] The gate of the MOS transistor NM5b is connected to the gate of the MOS transistor PM5b. The drain of the MOS transistor NM5b is connected to the node VOP and the drain of the MOS transistor PM5b, respectively. The sources of the MOS transistors PM5b and PM5a are both connected to the voltage VDDB.

[0025] Furthermore, when both clock signals CLKA and CLKB are high, the clock-controlled latch is in the off state; after MOSFETs PM3a and PM3b are turned off, the clock-controlled latch is in the active state.

[0026] Furthermore, when both clock signal CLKA and clock signal CLKB are high, MOSFET PM4 is turned on and MOSFET NM4 is turned off. At this time, all MOSFETs in the clock-controlled latch are in the off state.

[0027] After MOSFETs PM3a and PM3b are turned off, MOSFET PM4 is turned off, MOSFET NM4 is turned on, and the clock latch is activated.

[0028] Furthermore, it also includes a D flip-flop, which operates between the voltage VDDB and the voltage VSSB, and its input is connected between the drain of the MOS transistor NM5a and the drain of the MOS transistor PM5a.

[0029] The present invention also provides a high-speed digital-to-analog converter, including any of the level shifter circuits described above.

[0030] The present invention also provides a high-speed analog-to-digital converter, including the level shifter circuit described in any of the above.

[0031] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least:

[0032] The present invention discloses a level shifter circuit that operates under the voltage difference between voltage VDDB and voltage VSSA through a current-mode logic unit. By using a high-voltage MOSFET NM3a or NM3b with its gate biased at a suitable potential VBN to isolate the upper and lower low-voltage devices, all low-voltage devices are prevented from experiencing overvoltage. This solves the problem of easy overvoltage when using low-voltage devices in existing level shifters and reduces the production cost of level shifters. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 is a simplified diagram of the internal data transmission architecture of an existing high-speed ADC / DAC chip;

[0035] Figure 2 shows the existing data transmission level shifter circuit and clock coupling circuit;

[0036] Figure 3 shows the timing diagram of data and clock transmission across the power domain for existing level shifters;

[0037] Figure 4 shows another implementation of an existing level shifter circuit;

[0038] Figure 5 is a circuit diagram of a level shifter circuit according to the present invention;

[0039] Figure 6 is a transmission timing diagram of the level shifter circuit of the present invention. Detailed Implementation

[0040] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0041] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0043] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0045] Figure 2 illustrates a conventional level shifter circuit and clock coupler circuit for data transmission between different power domains. Taking signal transmission from a low power domain to a high power domain as an example, its working principle is as follows: Input signal DA and clock signal CLKA are the data and synchronization clock for the VDDA / VSSA power domain, respectively. Input signal DA first passes through a low-voltage to high-voltage level shifter composed of MOSFETs NM1a / NM1b and PM1a / PM1b, shifting its logic voltage from VDDA / VSSA to VDDB / VSSA. Then, it passes through a high-voltage to low-voltage level shifter composed of MOSFETs PM2a / PM2b and NM2a / NM2b, shifting the logic voltage from VDDB / VSSA to VDDB / VSSB, completing the cross-power domain data transmission. Clock signals CLKA and CLKB are the in-phase clocks for the VDDA / VSSA and VDDB / VSSB power domains, respectively, and are transmitted through the circuit shown in the dashed box at the bottom of Figure 2. Finally, the D flip-flops in the VDDB / VSSB domain use the clock signal CLKB to sample the data and complete the synchronization of clock data in the VDDB / VSSB power domain.

[0046] Figure 3 shows the timing diagram of the circuit shown in Figure 2. In this structure, since the voltage difference between VDDB and VSSA exceeds the standard operating voltage of the low-voltage devices, MOSFETs NM1a / NM1b, PM1a / PM1b, and PM2a / PM2b must be implemented using high-voltage devices. However, the cutoff frequency of the high-voltage devices is much lower than that of the low-voltage devices. Therefore, this data level shifter circuit is difficult to achieve a high transmission speed.

[0047] Figure 4 shows another existing data level shifting circuit. Compared to the conventional structure in Figure 2, protection transistors NM3a / NM3b with their gates biased at a suitable potential VBN are stacked on top of input transistors NM1a / NM1b. When input transistors NM1a / NM1b are turned off, their drain voltage is clamped at VBN minus the threshold voltage of the protection transistors NM3a / NM3b, which allows input transistors NM1a / NM1b to be implemented using low-voltage devices. The diode-connected MOSFETs PM3a / PM3b are connected in series between MOSFETs PM1a / PM1b and protection diodes NM3a / NM3b. When MOSFETs NM1a / NM1b are turned on, MOSFETs PM3a / PM3b are also turned on. The gate potential of MOSFETs PM1a / PM1b will drop to at least the on-gate-source voltage VGSP3 of MOSFETs PM3a / PM3b. At this time, the gate-source voltage between MOSFETs PM1a / PM1b will be clamped at VDDB-VSSA-VGSP3. By reasonably setting the width-to-length ratio of MOSFETs PM3a / PM3b, VDDB-VSSA-VGSP3 is made smaller than the rated operating voltage of low-voltage devices. MOSFETs PM1a / PM1b and PM2a / PM2b can also be implemented using low-voltage devices, thus avoiding the speed reduction caused by driving high-voltage devices in the signal transmission path. However, this data level shifting circuit is severely affected by process angle variations. During the design process, sufficient margin needs to be left for the gate-source voltage VGSP3 when PM3a / PM3b is turned on to ensure that MOSFET PM1a / PM1b will not experience overvoltage under all process angles. This will severely compress the turn-on gate-source voltage of MOSFET PM1a / PM1b under certain extreme process angles, reducing the switching speed and the robustness of the circuit.

[0048] Based on this, the embodiments of this specification propose a processing scheme: As shown in Figure 1, the level shifter circuit of the present invention adopts a two-stage structure composed of a preamplifier based on current-mode logic unit and a subsequent latch. Only high-voltage devices are used for isolation protection between different power domains, and the driving of digital signals is implemented entirely using low-voltage devices. Compared with existing level conversion circuits, the level shifter circuit of the present invention has a faster transmission speed and higher robustness.

[0049] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0050] The level shifter circuit for data transmission provided by this invention will be described using the example of data transmission from a low power domain to a high power domain.

[0051] As shown in Figures 5-6, the present invention provides a level shifter circuit, including MOSFET PM1b, MOSFET PM2b, MOSFET PM2a, MOSFET PM1a, a current-mode logic unit and a clocked latch. The sources of MOSFETs PM1b, PM2b, PM2a and PM1a are all connected to voltage VDDA. The gates of MOSFET PM2b and PM2a are connected to each other. The drains of MOSFET PM1b and PM2b are connected. The drains of MOSFET PM2a and PM1a are connected.

[0052] The current-mode logic unit includes MOSFETs NM2b, NM2a, NM1b, NM1a, a current source IB, resistors R1b and R1a, MOSFETs PM3b, PM3a, NM3b, NM3a, and a first inverter. The drain of MOSFET NM2b is connected to the drain of MOSFET PM1b, and its source is connected to the drain of MOSFET NM1b. Its gate is connected to the gate of MOSFET NM2a and then connected to the clock signal CLKA, the gate of MOSFET PM2b, and the gate of MOSFET PM2a1, respectively. The drain of MOSFET NM2a is connected to the drain of MOSFET PM1a, and its source is connected to the drain of MOSFET NM1a. The gate of MOSFET NM1a is connected to the input signal DA and the gate of MOSFET PM1a, respectively. Its source is connected to the source of MOSFET NM1b and then connected to the voltage VSSA through the current source IB. The gate of MOSFET NM1b is connected to the input signal DA. A. The gate of MOSFET PM1b; the source of MOSFET PM3b is connected to voltage VDDB through resistor R1b, and its gate is connected to the gate of MOSFET PM3a; the source of MOSFET PM3a is connected to voltage VDDB through resistor R1a, and its drain is connected to the drain of MOSFET NM3a to form node VON; the source of MOSFET NM3a is connected to the drain of MOSFET NM2a, and its gate is connected to bias voltage VBN and voltage VSSA respectively; the gate of MOSFET NM3b is connected to bias voltage VBN and voltage VSSA respectively, and its drain is connected to the drain of MOSFET PM3b to form node VOP; the source of MOSFET NM3b is connected to the drain of MOSFET NM2b; the first inverter operates between voltage VDDB and voltage VSSB, and its input is connected to clock signal CLKB, and its output is connected between the gates of MOSFET PM3b and MOSFET PM3a, and to a clock latch. The clock latch is also connected to nodes VOP and VON respectively.

[0053] Among them, resistors R1a and R1b are used to limit the current and prevent overload.

[0054] The gate of the MOSFET NM1b is connected to the input signal DA via a second inverter.

[0055] Among them, MOSFETs NM3b and NM3a are high-voltage MOSFETs, while MOSFETs PM1b, PM2b, PM2a, PM1a, NM2b, NM2a, NM1b, NM1a, PM3b, and PM3a are low-voltage MOSFETs.

[0056] The difference between the bias voltage and the voltage VDDA is less than the threshold voltage of MOSFET NM3a or MOSFET NM3b.

[0057] The bias voltage is used to provide operating point control to control the turn-on state of MOSFETs NM3a and NM3b, so as to provide a stable operating point.

[0058] In some embodiments, the clock-controlled latch includes MOSFETs NM4, PM4, PM5a, PM5b, NM5a, and NM5b; the gate of MOSFET NM4 is connected to the output of the first inverter, and its source is connected to the voltage VSSB; the gate of MOSFET PM4 is connected to the gate of MOSFET NM4, its source is connected to the voltage VDDB, and its drain is connected to the source of MOSFET NM5a; the gate of MOSFET NM5a is connected to the gate of MOSFET PM5a. The drain of transistor b is connected to the gate of MOSFET PM5a. The drain of b is connected to the drain of MOSFET PM5a, the gate of MOSFET PM5b, and node VON. The source of b is connected to the source of MOSFET NM5b and then to the drain of MOSFET NM4. The gate of MOSFET NM5b is connected to the gate of MOSFET PM5b. The drain of MOSFET NM5b is connected to node VOP and the drain of MOSFET PM5b. The sources of MOSFET PM5b and MOSFET PM5a are both connected to voltage VDDB.

[0059] Specifically, when both clock signals CLKA and CLKB are high, the clock latch is in the off state; after MOSFETs PM3a and PM3b are turned off, the clock latch is in the active state to correctly transmit the signal to the next unit.

[0060] Specifically, when both clock signals CLKA and CLKB are high, MOSFET PM4 is turned on and MOSFET NM4 is turned off, so all MOSFETs in this clock-controlled latch are in the off state; after MOSFETs PM3a and PM3b are turned off, MOSFET PM4 is turned off and MOSFET NM4 is turned on, and the clock-controlled latch is activated.

[0061] In some embodiments, the level shifter circuit further includes a D flip-flop that operates between voltage VDDB and voltage VSSB, and whose input is connected between the drain of MOSFET NM5a and the drain of MOSFET PM5a.

[0062] The working principle of the level shifter circuit of this invention is as follows:

[0063] When the logic voltage of the input signal DA is high, if the clock signals CLKA and CLKB are high, MOSFET PM4 is turned on and MOSFET NM4 is turned off. All MOSFETs in the clocked latch are in the off state, and MOSFETs NM2a, NM2b, PM3a, and PM3b are turned on. MOSFET NM1a is turned on and MOSFET NM1b is turned off. The current source IB flows through MOSFET NM1a to resistor R1a, generating a voltage drop IB*R1 across resistor R1a. At this time, the voltage at node VON is VDDB-IB*R1.

[0064] Simultaneously, MOSFET PM1b turns on, pulling its drain voltage towards VDDA. Since the bias voltage VBN is designed to ensure VBN-VDDA is less than the threshold voltage of NM3a / NM3b, MOSFET NM3b is turned off at this time. The node VOP voltage is pulled up to VDDB by resistor R1b and MOSFET PM3b, and the voltage difference between nodes VOP and VON is IB*R1. When the falling edge of clock signals CLKA and CLKB arrives, MOSFETs NM2a / NM2b turn off, MOSFETs PM2a / PM2b turn on, and the sources of MOSFETs NM3a / NM3b are pulled to the low power domain voltage VDDA. MOSFETs NM3a / NM3b then turn off, completely isolating the low-voltage devices from the high and low power domains.

[0065] After MOSFETs PM3a and PM3b are turned off, nodes VOP and VON are disconnected from resistors R1a and R1b. MOSFET NM4 is turned on, and MOSFET PM4 is turned off. The clock latch is activated, further amplifying the initial voltage IB*R1 established at nodes VOP and VON when the clock is high into a digital logic signal in the VDDB / VSSB domain. This digital logic signal will be sampled by the tail-stage D flip-flop when the rising edge of the clock signal CLKB arrives, completing the synchronization of data with the clock CLKB in the VDDB / VSSB power domain. Figure 6 shows the operating timing of the level shifter proposed in this invention.

[0066] As can be seen from the above analysis, the signal of the data level shift circuit proposed in this invention only drives the gate of the low-voltage device during the transmission across power domains. When the clock is high, the input digital signal is pre-amplified to a certain initial value at the internal node of the clock-controlled latch by taking advantage of the high-speed characteristics of the current-mode logic unit. When the clock signal is low, the switching speed of the clock-controlled latch is improved because the initial operating voltage of the clock-controlled latch is already at a large value. Therefore, the level shifter circuit proposed in this invention has a high transmission speed.

[0067] Furthermore, when MOSFETs NM3a and NM3b are turned on, the voltage difference between the low voltages at nodes VOP and VON and VDDB is controlled at IB*R1. The voltage difference between the two power domains is entirely borne by the source-drain voltage of the high-voltage devices MOSFETs NM3a and NM3b, and all low-voltage devices are free from overvoltage risk. Compared to the scheme reported in Figure 4, which uses multiple low-voltage devices stacked together to solve the overvoltage process, the level shifting circuit proposed in this invention has higher robustness.

[0068] This application uses low-voltage MOSFETs for signal driving, which improves circuit speed and meets the requirements of high-speed digital signal transmission. Furthermore, it uses only a small number of high-voltage MOSFETs between high and low power domains, achieving isolation protection and significantly reducing manufacturing costs.

[0069] The superior effect of this invention is that it uses only high-voltage devices for voltage isolation between different power domains, which is faster than using only low-voltage devices for signal driving, and avoids the use of high-voltage devices to drive signals on the data transmission path across power domains, thereby improving the transmission speed and robustness of the level shifter circuit.

[0070] The present invention also provides a high-speed digital-to-analog converter, including a level shifter circuit, a data receiver, decoding logic and latches, and a current source array as described above.

[0071] The data receiver, level shifter, decoding logic and latch, and current source array are connected in series.

[0072] The present invention also provides a high-speed analog-to-digital converter, including a level shifter circuit, a quantizer, a digital signal processing module, and an output serial port as described above.

[0073] Specifically, the quantizer, digital signal processing module, level shifter, and output serial port are connected in series to form an analog-to-digital converter.

[0074] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0075] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A level shifter circuit, characterized in that, The system includes MOSFETs PM1b, PM2b, PM2a, and PM1a, whose sources are connected to voltage VDDA; a current-mode logic unit; and a clocked latch. The gates of MOSFETs PM2b and PM2a are connected, the drains of MOSFETs PM1b and PM2b are connected, and the drains of MOSFETs PM2a and PM1a are connected. The current-mode logic unit includes MOSFETs NM2b, NM2a, NM1b, and NM1a; a current source IB; and resistors R1b and R1a. The circuit consists of MOSFETs PM3b, PM3a, NM3b, NM3a, and a first inverter. The drain of MOSFET NM2b is connected to the drain of MOSFET PM1b, and its source is connected to the drain of MOSFET NM1b. Its gate is connected to the gate of MOSFET NM2a and then to the clock signal CLKA and the gate of MOSFET PM2b, respectively. The drain of MOSFET NM2a is connected to the drain of MOSFET PM1a, and its source is connected to the drain of MOSFET NM1a. The gate of MOSFET NM1a is connected to the input signal DA and the gate of MOSFET PM1a, respectively. The gate and source of transistor a are connected to the source of MOSFET NM1b and then connected to voltage VSSA via current source IB. The gate of MOSFET NM1b is connected to the input signal DA and the gate of MOSFET PM1b, respectively. The source of MOSFET PM3b is connected to voltage VDDB via resistor R1b, and its gate is connected to the gate of MOSFET PM3a. The source of MOSFET PM3a is connected to voltage VDDB via resistor R1a, and its drain is connected to the drain of MOSFET NM3a to form node VON. The source of MOSFET NM3a is connected to the gate of MOSFET NM2a. The drain and gate of the transistor are connected to the bias voltage VBN and the voltage VSSA, respectively. The gate of the MOSFET NM3b is connected to the bias voltage VBN and the voltage VSSA, and its drain is connected to the drain of the MOSFET PM3b to form node VOP. The source of the MOSFET NM3b is connected to the drain of the MOSFET NM2b. The first inverter operates between the voltage VDDB and the voltage VSSB, and its input is connected to the clock signal CLKB. Its output is connected to the MOSFET PM3b and the clock latch, and the clock latch is also connected to node VOP and node VON, respectively.MOSFETs NM3b and NM3a are high-voltage MOSFETs, while MOSFETs PM1b, PM2b, PM2a, PM1a, NM2b, NM2a, NM1b, NM1a, PM3b, and PM3a are all low-voltage MOSFETs. The difference between the bias voltage and the voltage VDDA is less than the threshold voltage of either MOSFET NM3a or NM3b.

2. The level shifter circuit according to claim 1, characterized in that, The gate of the MOS transistor NM1b is connected to the input signal DA via a second inverter.

3. The level shifter circuit according to any one of claims 1 to 2, characterized in that, The clock-controlled latch includes MOSFETs NM4, PM4, PM5a, PM5b, NM5a, and NM5b; the gate of MOSFET NM4 is connected to the output of the first inverter, and its source is connected to the voltage VSSB; the gate of MOSFET PM4 is connected to the gate of MOSFET NM4, its source is connected to the voltage VDDB, and its drain is connected to the source of MOSFET NM5a; the gate of MOSFET NM5a is connected to the drain of MOSFET PM5b, and the clock-controlled latch includes MOSFETs NM4, PM4, PM5a, PM5b, NM5a, and NM5b. The gate of S-channel transistor PM5a is connected to the gate of MOSFET PM5a, the drain of MOSFET PM5b is connected to the drain of MOSFET PM5a, the gate of MOSFET PM5b, and node VON, respectively, and the source of MOSFET NM5b is connected to the source of MOSFET NM4. The gate of MOSFET NM5b is connected to the gate of MOSFET PM5b, the drain of MOSFET NM5b is connected to node VOP and the drain of MOSFET PM5b, respectively, and the sources of MOSFET PM5b and MOSFET PM5a are both connected to the voltage VDDB.

4. The level shifter circuit according to claim 3, characterized in that, When both clock signals CLKA and CLKB are high, the clock-controlled latch is in the off state; after MOSFETs PM3a and PM3b are turned off, the clock-controlled latch is in the active state.

5. The level shifter circuit according to claim 4, characterized in that, When both clock signals CLKA and CLKB are high, MOSFET PM4 is turned on and MOSFET NM4 is turned off, and all MOSFETs in the clock-controlled latch are in the off state at this time. After MOSFETs PM3a and PM3b are turned off, MOSFET PM4 is turned off and MOSFET NM4 is turned on, and the clock-controlled latch is activated.

6. The level shifter circuit according to claim 1, characterized in that, It also includes a D flip-flop, which operates between the voltage VDDB and the voltage VSSB, and its input is connected between the drain of the MOS transistor NM5a and the drain of the MOS transistor PM5a.

7. A high-speed digital-to-analog converter, characterized in that, Includes the level shifter circuit as described in any one of claims 1 to 6.

8. A high-speed analog-to-digital converter, characterized in that, Includes the level shifter circuit as described in any one of claims 1 to 6.

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