High-rate QC-LDPC check matrix construction method, device, medium and product for NAND

Abstract

This application discloses a high-code-rate QC-LDPC check matrix construction method, device, medium and product for NAND, which relates to the field of channel coding technology. The method includes: first, generating an initial check matrix with uniform row weight distribution and no four-ring structure; second, traversing a preset shift value range for each non-zero item in the initial check matrix, selecting the shift value that minimizes the number of six rings to generate an intermediate check matrix; finally, based on the number of six rings in which each non-zero item in the intermediate check matrix participates, sequentially eliminating the non-zero items with the largest number of six rings to obtain a target check matrix. This method significantly improves the error correction performance of the check matrix and reduces decoding delay by progressively optimizing the four-ring, six-ring and global balance, adapting to the reliability requirements of high-code-rate NAND flash memory.

Description

Technical Field

[0001] The present application relates to the field of channel coding technology, and in particular to a method, device, medium, and product for constructing a high-rate QC-LDPC check matrix for NAND. Background Art

[0002] With the increasing storage density of NAND flash memory, high-rate QC-LDPC codes have become a core error correction solution due to their error correction capabilities and hardware friendliness. However, the construction of high-rate QC-LDPC parity check matrices in existing technologies faces two major challenges: First, in high-rate scenarios, the parity check matrix is prone to short loop structures such as four- and six-loops, forming "trap sets" that hinder decoding convergence and reduce error correction performance; second, uneven row weight distribution reduces the stability of the normalized minimum sum decoding algorithm, affecting decoding efficiency. In addition, existing methods lack systematic optimization of short loops, making it difficult to balance high code rate and low complexity requirements.

[0003] Therefore, there is an urgent need for a high-rate QC-LDPC check matrix construction method suitable for NAND flash memory, which can effectively eliminate the four-ring structure, minimize the number of six-rings and achieve uniform row weight distribution. Summary of the Invention

[0004] The present application provides a high-code-rate QC-LDPC check matrix construction method, device, medium and product for NAND to solve the problem that existing solutions cannot systematically eliminate short loops and destroy row weight uniformity in high-code-rate scenarios.

[0005] The present application provides a method for constructing a high-rate QC-LDPC check matrix for NAND, the method comprising:

[0006] Generate an initial check matrix; the rows of the initial check matrix are uniformly distributed and do not have a four-ring structure;

[0007] For each non-zero entry in the initial parity check matrix, traverse the preset shift value range and select the shift value that minimizes the number of six rings to generate an intermediate parity check matrix;

[0008] Based on the number of six-rings that each non-zero item in the intermediate check matrix participates in, the non-zero items with the largest number of six-rings are eliminated in sequence to obtain the target check matrix.

[0009] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned methods for constructing a high-rate QC-LDPC check matrix for NAND when executing the computer program.

[0010] The present application also provides a computer-readable storage medium, which stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-mentioned high-code-rate QC-LDPC check matrix construction methods for NAND.

[0011] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of any of the above-mentioned methods for constructing a high-code-rate QC-LDPC check matrix for NAND.

[0012] This application systematically optimizes the performance and hardware adaptability of high-rate QC-LDPC check matrices based on a progressive three-step construction method. First, an initial check matrix with uniform row weight distribution and no four-ring structure is generated. By balancing the number of non-zero items in each row, the parameter adaptation instability of the decoding algorithm is avoided. At the same time, the four-ring closed path is eliminated to block information transmission conflicts, thereby improving the decoding convergence speed and error correction reliability. Secondly, the non-zero item shift values of the initial check matrix are traversed and the configuration with the least six rings is selected to generate an intermediate check matrix. The six-ring density is significantly reduced by column-by-column local optimization, avoiding the high complexity of global search while maintaining the row weight uniformity of the initial matrix. Finally, based on the priority of the number of non-zero items participating in the six rings in the intermediate check matrix, high-frequency six-ring items are eliminated in sequence to generate the target check matrix. The remaining trap sets are directionally broken and the operation positions are dispersed to eliminate the operation positions. While reducing the number of global short rings, the row weight balance is maintained. Finally, the check matrix achieves the coordinated optimization between error correction performance, decoding stability and hardware complexity, meeting the core requirements of NAND flash memory for high reliability, low latency and low power consumption in high-rate scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 A schematic diagram of a method flow for constructing a high-rate QC-LDPC parity check matrix for NAND provided in an embodiment of the present application;

[0015] Figure 2 A schematic flow chart of a method for constructing a high-rate QC-LDPC code parity check matrix suitable for NAND flash memory provided in an embodiment of the present application;

[0016] Figure 3 A flow chart of a method for eliminating non-zero elements in an intermediate check matrix provided in an embodiment of the present application;

[0017] Figure 4 Schematic diagram of the total number of six rings of the three check matrices provided in the embodiments of the present application;

[0018] Figure 5 A schematic diagram of the decoding results of the bit error rates of the three check matrices provided in the embodiment of the present application;

[0019] Figure 6 Schematic diagram of the frame error rate decoding results of the three check matrices provided in the embodiment of the present application;

[0020] Figure 7 1 is a schematic structural diagram of a high-rate QC-LDPC parity check matrix construction device for NAND provided in an embodiment of the present application;

[0021] Figure 8 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0024] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the high-rate QC-LDPC check matrix construction method for NAND depends, the specific application environment architecture or specific hardware architecture is described herein.

[0026] With the rapid increase in NAND flash memory storage density, especially with the widespread adoption of 3D stacking technologies (such as TLC and QLC), the reduction in cell size and the increase in the number of stacked layers have significantly increased internal noise, leading to a corresponding increase in bit error rates. Quasi-cyclic low-density parity-check (QC-LDPC) codes have become a core solution for NAND flash error correction coding due to their excellent error correction performance and hardware-friendliness. However, at high code rates (>0.8), the construction of existing QC-LDPC check matrices faces significant challenges. Firstly, high code rates require a significant increase in the proportion of information bits in the check matrix, resulting in a sparse matrix structure. Short loops, such as four and six loops, are prone to forming "trap sets," hindering information transfer between variable and check nodes during decoding, extending the number of iterations and reducing error correction capability. Secondly, traditional construction methods (such as random generation and heuristic optimization) struggle to balance short loop elimination with uniform row weight distribution. Uneven row weight distribution can lead to an imbalance in the adaptation of the normalization factor in the decoding algorithm, further exacerbating decoding performance fluctuations.

[0027] In existing technologies, the Progressive Edge Growth (PEG) method can construct a basis matrix without short cycles, but it lacks systematic optimization of cyclic shift values and cannot effectively solve the problem of hidden short cycles generated by cyclic shifts in QC-LDPC codes. In addition, in high-code rate scenarios, the number of non-zero entries in the parity check matrix must be strictly controlled to reduce hardware complexity. However, existing methods often destroy row redistribution or introduce new short cycles when eliminating non-zero entries, making it difficult to achieve both performance and efficiency. For example, some schemes reduce short cycles by randomly eliminating non-zero entries, but this increases the standard deviation of row weights, affecting decoding stability. Other schemes use global search to optimize shift values. Although this can reduce the density of short cycles, the computational complexity is extremely high, making it difficult to adapt to the real-time requirements of NAND flash memory.

[0028] Therefore, there is an urgent need for a high-rate QC-LDPC check matrix construction method for NAND flash memory that can systematically eliminate short ring structures such as four-ring and six-ring structures, while strictly maintaining a uniform distribution of row weights and achieving an optimal balance between the number of non-zero entries and hardware complexity, thereby meeting the stringent requirements of 3D TLC / QLC NAND flash memory for high reliability, low latency and low power consumption.

[0029] Therefore, an embodiment of the present application provides a method for constructing a high-rate QC-LDPC check matrix for NAND, and the method is described in detail in conjunction with the execution flow of the method for constructing a high-rate QC-LDPC check matrix for NAND.

[0030] First, the terms involved in this application are introduced.

[0031] NAND: NAND flash memory, a non-volatile storage medium; LDPC (Low Density Parity Check Code); QC-LDPC (Quasi-cyclic LDPC); PEG (Progressive Edge-Growth); AWGN (Additive White Gaussian Noise); LLR (Log Likelihood Ratio); RLMS (Row Layered Normalized Min-Sum).

[0032] The embodiment of the present application provides a method for constructing a high code rate QC-LDPC check matrix for NAND. The specific process of the method is as follows: Figure 1 As shown, the specific steps include the following steps.

[0033] S101: Generate an initial check matrix.

[0034] Specifically, in step S101, the initial parity check matrix serves as the starting point for the entire construction process. Its structure must meet two key requirements: uniform row weight distribution and the absence of four-ring structures. As the foundation for subsequent optimization, the balance and absence of short cycles in the initial matrix provide a reliable starting point for improving the performance of intermediate and target matrices. If the initial matrix exhibits uneven row weights or a four-ring structure, subsequent optimization may struggle to achieve global optimization due to these fundamental deficiencies.

[0035] Row weight refers to the number of nonzero entries in a row of the parity check matrix. For example, if a row contains 5 nonzero entries, its row weight is 5. Uniform distribution is achieved by constraining the number of nonzero entries in each row to be as close as possible when constructing the initial matrix. For example, the row weight of all rows is controlled between 4 and 6 (the specific value is determined by the bit rate requirement), rather than having only 2 nonzero entries in some rows and 10 in others.

[0036] Row weight significantly impacts decoding. Decoding algorithms (such as the minimum sum algorithm) must process the checksum equation row by row. Uniform row weighting prevents certain rows from becoming computational bottlenecks due to excessive nonzero entries, improving hardware parallelization efficiency. Furthermore, decoding parameters such as the normalization factor are often correlated with row weight. Excessive differences in row weights can lead to difficulties in parameter adaptation and affect convergence stability.

[0037] A quadruple loop is a closed loop formed by four nonzero terms. Its path begins at a variable node, passes through two check nodes, and then two variable nodes, returning to the starting point, forming a rectangular closed path. During iterative decoding, a quadruple loop can cause repeated information conflicts between variable and check nodes, hindering the propagation of reliable information. The presence of a quadruple loop can prolong decoding iterations and even cause decoding failure.

[0038] During the initial matrix construction phase, all quad-rings can be actively broken by dynamically detecting quad-rings and adjusting the positions of non-zero entries or the cyclic shift values of the sub-matrices.

[0039] S102: For each non-zero item in the initial parity check matrix, traverse a preset shift value range, select a shift value that minimizes the number of six rings, and generate an intermediate parity check matrix.

[0040] Specifically, in step S102 above, in the QC-LDPC code, non-zero entries correspond to submatrix blocks, typically the identity matrix or a cyclically shifted version thereof. For example, if the submatrix dimension is 64, each non-zero entry represents a 64×64 cyclically shifted identity matrix block. The cyclic shift value determines the number of right shifts of the identity matrix block. For example, when the shift value is 3, each row of the identity matrix is cyclically shifted to the right by 3 bits. By adjusting the shift value, the position of the submatrix block is changed, thereby affecting the distribution of non-zero entries in the check matrix and indirectly controlling the generation of short cycles.

[0041] The shift value range of the preset shift value range generally covers all possible values of the sub-matrix dimension. For example, when the sub-matrix dimension is 128, the shift value range is 0 to 127.

[0042] For each submatrix corresponding to a nonzero entry, all possible shift values are traversed to generate multiple candidate matrices. For each candidate matrix, the total number of six-rings is counted, and the candidate with the fewest six-rings is selected as the final shift value. Traversing the shift values column by column (rather than adjusting them simultaneously) reduces computational complexity and significantly reduces the six-ring density through local optimization.

[0043] The generated intermediate parity check matrix maintains row weight uniformity while gradually reducing the number of six-rings. Specifically, during the shift value adjustment process, row redistribution is constrained to ensure that the number of nonzero entries in each row of the intermediate matrix is consistent with that of the initial matrix, maintaining decoding stability. The total number of six-rings in the intermediate matrix is significantly reduced compared to the initial matrix, providing a transitional structure for the final global optimization.

[0044] S103 , based on the number of six-rings in which each non-zero item in the intermediate check matrix participates, sequentially eliminate the non-zero items that participate in the largest number of six-rings to obtain a target check matrix.

[0045] Specifically, in step S103, all hexagonal closed paths in the intermediate parity check matrix are traversed, and the total number of six-rings in which each non-zero entry participates is recorded. The non-zero entries are sorted from highest to lowest by the number of six-rings they participate in, generating a priority queue for elimination. Frequent six-ring entries (i.e., those with the most non-zero entries participating in the six-rings) are considered to have the greatest impact on global performance and are eliminated first.

[0046] Starting from the head of the priority queue, the sub-matrices corresponding to the high-frequency six-ring items are replaced with all-zero matrices in sequence, gradually reducing the number of global six-rings.

[0047] During the elimination process, it is necessary to maintain uniform row weights. The standard deviation of row weights can be calculated in real time. If the number of non-zero items in a row deviates from the preset range, subsequent elimination of that row is skipped. This ensures that the number of non-zero items in each column does not decrease excessively, avoiding large differences in column weights that could affect bitrate stability.

[0048] The resulting target parity check matrix achieves a global minimization of the number of short cycles while maintaining uniform row weights. By eliminating high-frequency six-cycle terms, the number of six-cycles in the target matrix is further reduced, completely breaking the decoding trap. Elimination operations are distributed across rows and columns to avoid localized sparsity, and the standard deviation of row weights is maintained within a preset threshold.

[0049] The high-rate QC-LDPC parity check matrix construction method for NAND provided in the embodiment of the present application is based on a progressive three-step construction method to systematically optimize the performance and hardware adaptability of the high-rate QC-LDPC parity check matrix. First, an initial parity check matrix with uniform row weight distribution and no four-ring structure is generated. By balancing the number of non-zero items in each row, parameter adaptation instability of the decoding algorithm is avoided, and four-ring closed paths are eliminated to block information transmission conflicts, thereby improving the decoding convergence speed and error correction reliability. Secondly, the non-zero item shift values of the initial parity check matrix are traversed and the configuration with the least six-ring is selected to generate an intermediate parity check matrix. The six-ring density is significantly reduced through column-by-column local optimization, avoiding the high complexity of global search while maintaining the row weight uniformity of the initial matrix. Finally, based on the priority of the number of non-zero items participating in the six-ring in the intermediate parity check matrix, high-frequency six-ring items are eliminated in sequence to generate the target parity check matrix. The remaining trap sets are directionally broken and the operation positions are dispersed to eliminate the operation positions. The number of global short rings is reduced while maintaining row weight balance. Ultimately, the parity check matrix achieves coordinated optimization between error correction performance, decoding stability and hardware complexity, meeting the core requirements of NAND flash memory for high reliability, low latency and low power consumption in high bit rate scenarios.

[0050] In an optional embodiment, an initial check matrix is generated, including: constructing a base matrix based on a progressive edge growing method; the column weight of the base matrix is a first preset column weight, and the number of non-zero entries in each column is equal; connecting each variable node in the base matrix in turn to a check node that can maximize the current shortest path length; if there are multiple candidate check nodes that can maximize the shortest path length, then selecting the check node with the least number of short loops for connection; at each connection, detecting the four-loop structure through a four-loop detection formula and monitoring the uniformity of the row weight; if a four-loop structure is detected, reselecting the check node and adjusting the cyclic shift value of the submatrix in the base matrix until the four loops are eliminated; generating an initial check matrix with uniformly distributed row weights and no four-loop structure.

[0051] The Progressive Edge Growth (PEG) algorithm gradually expands the connections between variable nodes and check nodes, prioritizing check nodes that maximize the current shortest path length to avoid local overload caused by random connections, thereby reducing the probability of short loops. When multiple candidate check nodes exist, the node with the fewest short loops is selected to further suppress short loops beyond the four-loop structure, improving the quality of the initial matrix. Real-time verification using the four-loop detection formula during each connection ensures that four-loops are immediately detected and eliminated during the construction process, avoiding the costly backtracking corrections required in subsequent optimization phases. Combined with cyclic shift value adjustments, this algorithm directly destroys the four-loop closed path, laying the foundation for subsequent six-loop optimization. During the connection process, the row weight standard deviation is monitored simultaneously, and the distribution of non-zero entries is dynamically corrected to prevent decoding parameter mismatches caused by excessively high local row weights, ensuring the stability of the decoding algorithm.

[0052] In an optional embodiment, monitoring the uniformity of row weights includes: calculating the standard deviation of the current row weights at each connection; if the row weight standard deviation exceeds a preset threshold, reallocating the positions of non-zero items to make the row weights evenly distributed.

[0053] The standard deviation quantifies the degree of dispersion of row weight distribution, providing an objective uniformity evaluation metric and avoiding errors based on subjective experience. When the standard deviation exceeds a threshold, non-zero entries are redistributed, prioritizing rows with lower row weights for padding. This achieves load balancing between rows and prevents overloaded rows from becoming performance bottlenecks during decoding. Row weight deviations are corrected in real time during base matrix construction, eliminating global adjustments after construction is complete, reducing computational redundancy, and improving construction efficiency.

[0054] In an optional embodiment, an intermediate check matrix is generated, including: based on a preset shift value range, traversing the cyclic shift value for each column submatrix of the initial check matrix; for each candidate shift value, generating a temporary check matrix and counting the total number of six rings; selecting the candidate shift value with the least total number of six rings as the target shift value; using the target shift value to replace the shift value of the corresponding submatrix in the initial check matrix; when the shift values of all column submatrices in the initial check matrix are replaced, an intermediate check matrix is obtained; and the rows of the intermediate check matrix are evenly distributed.

[0055] For each column of submatrices, all possible shift values are independently traversed, and local optimization is performed on a column-by-column basis to ensure that the number of six-rings in each column is optimal. The shift value with the smallest total number of six-rings is selected to replace the original value, directly reducing the global six-ring density of the intermediate matrix and the number of decoding traps. During the shift value replacement process, the uniformity of row redistribution is constrained to prevent the imbalance of the initial matrix during the six-ring optimization, ensuring that the decoding stability of the intermediate matrix is consistent with that of the initial matrix.

[0056] In an optional implementation, the shift value ranges from 0 to an integer between the submatrix dimension of the initial check matrix minus 1; and counting the total number of six rings is achieved by traversing a hexagonal closed path algorithm.

[0057] Limiting the shift value range to all possible values of the submatrix dimensions (0 to L-1) prevents missing potential optimal solutions and ensures comprehensive six-ring optimization. Integer range traversal simplifies computational logic and reduces hardware implementation complexity. The hexagonal closed path algorithm precisely locates all six-ring closed paths by identifying the shift value relationships between adjacent submatrices, preventing missed or misjudgment. The algorithm traverses all possible paths to ensure absolute accuracy of the six-ring count results, providing reliable data support for subsequent optimization.

[0058] In an optional embodiment, the method further includes: in the process of generating the intermediate check matrix, after each shift value adjustment, re-detecting the four-ring structure using the four-ring detection formula to ensure that no new four-ring structure is added.

[0059] During the six-ring optimization process, shift value adjustments may accidentally introduce new four-ring structures. By detecting and eliminating four-rings in real time, the four-ring-free characteristics of the intermediate matrix are maintained, preventing the degradation of error correction performance. Combined with the four-ring elimination mechanism of the initial matrix, double protection is formed to ensure the short-ring controllability of the entire construction process.

[0060] In an optional embodiment, obtaining a target check matrix includes: for each non-zero item in the intermediate check matrix, counting the number of six-rings in which each non-zero item participates, and generating a six-ring distribution matrix; sorting the non-zero items from high to low according to the number of six-rings according to the six-ring distribution matrix, and generating an elimination priority queue; selecting non-zero items from the head of the queue for elimination in rounds according to the elimination priority queue, and updating the six-ring distribution matrix and the elimination priority queue after each round of elimination; and terminating the elimination process when the number of eliminated non-zero items reaches a preset target, and generating a target check matrix.

[0061] The six-ring distribution matrix quantifies the short-loop impact of each non-zero entry, identifying high-frequency six-ring entries as priority elimination targets to minimize the number of global short loops. Elimination is carried out round by round according to priority queues, specifically breaking down the remaining trap sets and avoiding performance fluctuations caused by blind elimination. The six-ring distribution matrix and queues are updated after each elimination round to reflect changes in the matrix structure in real time, ensuring that subsequent elimination decisions are based on the latest status and improving optimization efficiency.

[0062] In an optional embodiment, generating a six-ring distribution matrix includes: traversing all hexagonal closed paths of an intermediate check matrix using a depth-first search algorithm, marking the number of six-rings in which each non-zero item participates; the generation of the paths is determined by the relationship between the cyclic shift values of adjacent submatrices in the intermediate check matrix; and generating the six-ring distribution matrix based on the determined number of six-rings in which each non-zero item participates.

[0063] The depth-first search algorithm recursively traverses all potential hexagonal paths, avoiding repeated calculations and significantly reducing time complexity. The algorithm focuses solely on the shift value relationships between adjacent submatrices, filtering out invalid search paths and improving statistical efficiency. Each time a six-ring path is discovered, the corresponding non-zero entry's participation count is immediately updated, ensuring the real-time and accuracy of the six-ring distribution matrix and providing reliable input for priority queue generation.

[0064] In an optional embodiment, non-zero items are selected from the head of the queue for elimination in each round, including: setting a flag bit for each row and each column of the six-ring distribution matrix. If a row or column has a non-zero item eliminated in the previous round, then the operation of the row or column is prohibited in the current round.

[0065] Flags are used to restrict operations on the same row or column in consecutive rounds, preventing local over-sparseness and maintaining uniform row weights in the matrix. A balanced elimination strategy prevents remaining short loops from concentrating in specific areas, improving global optimization. Forced distributed elimination operations gradually disintegrate short loops in different regions, preventing residual, locally dense short loops from impacting decoding convergence.

[0066] In an optional implementation, the row and column positions of the six-ring distribution matrix correspond one-to-one to the non-zero entries of the intermediate check matrix, and the matrix element value is the total number of six rings in which the corresponding non-zero entry participates.

[0067] The matrix's row and column positions strictly correspond to nonzero entries, eliminating data redundancy and simplifying priority sorting logic. Element values directly reflect the nonzero entry's participation in the six rings, intuitively guiding elimination decisions and reducing algorithm implementation complexity. The matrix structure facilitates subsequent expansion (such as weighted statistics and multi-ring joint optimization), providing underlying data support for advanced optimization algorithms.

[0068] In addition, after generating the target check matrix, the cyclic shift values of the remaining non-zero items are further dynamically fine-tuned and optimized, including: generating a fine-tuning priority sequence based on the number of six rings participated by the remaining non-zero items in the six-ring distribution matrix, and giving priority to adjusting the non-zero items with the largest number of six rings; adjusting the cyclic shift value of each target non-zero item in a preset fine-tuning range in the forward and reverse directions, and statistically analyzing the changes in the number of six rings after adjustment, and selecting the adjustment direction that reduces the number of six rings the most as the final shift value; if the number of six rings does not decrease after multiple consecutive adjustments, terminating the fine-tuning process of the current non-zero item to avoid ineffective consumption of computing resources.

[0069] Specifically, the fine-tuning optimization includes: generating a fine-tuning priority sequence based on the number of six-rings involved in the remaining non-zero items in the six-ring distribution matrix, and sorting the sequence from high to low according to the number of six-rings; performing positive and negative adjustments on each non-zero item in the priority sequence within the preset fine-tuning range of its cyclic shift value; counting the number of six-rings with positive adjustment, negative adjustment, and no adjustment, and selecting the adjustment direction that reduces the number of six-rings the most as the final shift value of the current non-zero item; terminating the fine-tuning process of the current non-zero item if the number of six-rings does not decrease after a preset number of consecutive adjustments; and generating the final check matrix after traversing all remaining non-zero items.

[0070] In an optional embodiment, the column weight of the initial check matrix is a first preset column weight; the first preset column weight is determined by the target code rate and channel conditions; and in the construction process of the initial check matrix, the column weight of each column is equal to the first preset column weight; the column weight of the intermediate check matrix is a mixed structure of the first preset column weight and the second preset column weight; the second preset column weight is obtained by eliminating the non-zero items of the target column in the initial check matrix; the column weight of the target check matrix is a mixed structure of the first preset column weight, the second preset column weight and the third preset column weight; the third preset column weight is obtained by eliminating the non-zero items of the intermediate check matrix column by column; the distribution ratio of the mixed structure is determined based on the target code rate and channel noise conditions.

[0071] The initial matrix uses a single column weight (e.g., 5), the intermediate matrix introduces a second column weight (e.g., 4), and the target matrix further incorporates a third column weight (e.g., 3). This balance is achieved through progressive adjustment, balancing bit rate and error correction performance. The column weight distribution is dynamically adjusted based on the target bit rate and channel noise, adapting to the diverse needs of TLC / QLC flash memory. High-column-weight regions retain strong error correction capabilities, while low-column-weight regions reduce non-zero entries to lower complexity, achieving an optimal balance between decoding performance and hardware resource utilization.

[0072] In an optional embodiment, the four-ring detection formula is:

[0073] ;

[0074] Where i k 、j k 、i k+1 and j k+1 are the row and column positions of the non-zero entries in the matrix, and L is the submatrix dimension;

[0075] The six-ring test formula is:

[0076] ;

[0077] Where i k 、j k 、i k+1 、j k+1 、i k+2 and j k+2 are the row and column positions of the non-zero entries in the matrix, L is the submatrix dimension, and P is the shift value of the submatrix other than the all-zero submatrix.

[0078] In summary, the high-code-rate QC-LDPC check matrix construction method for NAND provided in the embodiment of the present application systematically solves the short-loop interference, uneven row weight and hardware adaptability problems of high-code-rate QC-LDPC codes in NAND flash memory through a progressive construction process and a multi-level optimization strategy: First, the initial check matrix is dynamically constructed based on the progressive edge growth method (PEG), and the generation of short loops is suppressed by preferentially connecting the check nodes that "maximize the shortest path length". The four-loop detection formula is combined to eliminate the four-loop structure in real time, and the standard deviation of the row weight is monitored to dynamically adjust the distribution of non-zero items, thereby generating an initial matrix with uniform row weight and no four-loops, laying a foundation for subsequent optimization. The algorithm is based on the principle of balance and stability. Secondly, the initial matrix is traversed column by column by submatrix shift values. The number of six-rings is accurately counted using a hexagonal closed path algorithm. The locally optimal shift value is selected to generate an intermediate matrix. The four-ring structure is simultaneously re-checked to prevent performance regression, significantly reducing the six-ring density while maintaining row weight uniformity. Finally, a priority queue is constructed based on the six-ring distribution matrix. High-frequency six-ring items are marked using a depth-first search algorithm. Row and column flags are used to control round-by-round targeted elimination, dispersing and breaking the remaining trap sets. The algorithm dynamically adapts to the code rate and channel conditions in a hybrid column weight structure, ultimately minimizing the number of global short rings, controlling the standard deviation of row weight distribution, and reducing non-zero items. These technical features are closely linked. Through the synergistic effect of "four-ring elimination → six-ring local optimization → global balanced elimination," they significantly improve error correction performance, decoding convergence speed, and hardware efficiency, fully adapting to the stringent requirements of 3D TLC / QLC NAND flash memory for high reliability, low complexity, and real-time performance.

[0079] Based on the high-rate QC-LDPC check matrix construction method for NAND provided in the above embodiment, a specific example will be used to provide a detailed description below.

[0080] The rapid development of emerging fields such as 5G, artificial intelligence, cloud computing, and the Internet of Things has led to an explosive growth in data. NAND flash memory, due to its large storage capacity, high read / write performance, and low power consumption, has become a core component of current data centers. With the advancement of NAND flash manufacturing processes, represented by 3D stacking technology, NAND flash storage capacity has further increased, while the cost per bit of data storage has gradually decreased. However, the high number of stacked layers also introduces greater noise into the NAND flash memory, increasing the bit error rate of the data stored in the NAND flash memory.

[0081] Low-density parity-check (LDPC) codes are widely used in deep space exploration, satellite communications, and digital watermarking due to their excellent error correction performance. They are also the preferred ECC scheme for NAND flash memory. LDPC codes are essentially linear block codes and can be defined by a parity check matrix with dimensions of n rows and m columns. The number of rows in the parity check matrix represents the number of check equations, and the number of columns represents the length of the encoded information in each codeword. QC-LDPC codes are commonly used in NAND flash memory. Their parity check matrix consists of a series of sub-matrices of the same dimension. These sub-matrices are either all-zero matrices, identity matrices, or shifted matrices obtained by cyclically shifting the identity matrix to the right. This unique structure reduces the complexity of the encoding process and facilitates hardware implementation.

[0082] The decoding process in NAND flash memory is typically an iterative decoding scheme. Errors may occur in the encoded information due to variations in the threshold voltage distribution. When data is read, the encoded information is decoded using the H matrix. If the iterative information c satisfies c·HT = 0, it is a valid codeword and the decoding is successful, and the final c is output. Otherwise, a new round of iterations begins until the final decoding result satisfies the parity check relationship (c multiplied by the transpose of the parity check matrix H) and the result is 0, or the maximum number of iterations is reached.

[0083] Unlike applications in other fields, the characteristics of NAND flash memory require that the parity check matrix of its corresponding QC-LDPC code have both a high code rate (typically above 0.8) and good error correction performance. Especially with the development of 3D TLC and 3D QLC, the quality requirements for the LDPC parity check matrix are becoming increasingly stringent.

[0084] Therefore, based on the high code rate QC-LDPC parity check matrix construction method for NAND in the above embodiment, this embodiment further provides a high code rate QC-LDPC code parity check matrix construction method applicable to NAND flash memory.

[0085] The main process includes determining the base matrix dimension, code rate, submatrix dimension and column weight of the initial QC-LDPC check matrix; using the PEG-based construction method to obtain an initial check matrix H1 without quad-loops (for a variable node, starting from the variable node, alternating from the check node to the variable node after several steps and then returning to the starting variable node to form a closed loop is called a "loop" in the LDPC code), with the same column weight (5) and uniform row weight; modifying the submatrix shift values in the H1 matrix column by column and row by row until the minimum number of six loops is reached, to obtain the check matrix H2; constructing the frequency matrix of the non-zero items corresponding to H2 in the six loops, setting row and column flags, and eliminating the shift value with the largest number of six loops in the selected range each time to obtain the final check matrix H3.

[0086] The method proposed in this embodiment can construct QC-LDPC codes at various code rates suitable for 3D TLC and QLC NAND flash media, and the constructed matrix has excellent error correction performance. Furthermore, because this method reduces the number of nonzero entries during the construction of matrix H3, it can reduce latency in hardware implementations of serial decoding.

[0087] The submatrix of a QC-LDPC code parity check matrix is an all-zero matrix, the identity matrix, or a shifted matrix formed by cyclically shifting the identity matrix to the right by a fixed value. The base matrix can generally be represented by the shift factor corresponding to the submatrix. Generally, when the submatrix is all zero, "-1" is used to represent it, and when the matrix is the identity matrix, "0" is used to represent it. Other numbers represent the corresponding shift value. The number ranges from 0 to q, where q is the dimension of the submatrix.

[0088] The method for constructing a high-rate QC-LDPC code check matrix applicable to NAND flash memory in this embodiment uses a three-step construction method to construct the final check matrix. The specific construction method is as follows: Figure 2 shown.

[0089] The construction of the initial check matrix H1 is based on the PEG method, which specifically includes the following steps:

[0090] First, the dimensions m and n of the initial check matrix base matrix, column weight (column_weight), girth (g), and submatrix dimension (p) are set. The check matrix dimensions are mp × np. According to the PEG method, for each variable node, the shortest path length from the variable node to an unconnected check node is calculated. The check node with the largest shortest path length is selected. If there are multiple check nodes with the largest shortest paths, the variable node is connected to the check node at the location with the fewest short cycles, ensuring that each variable node is connected to only five check nodes. This method ensures that the non-zero entries in each row of the constructed matrix are evenly distributed.

[0091] Each connected edge corresponds to a non-zero entry in the parity check matrix, either the identity matrix or a matrix with shift values. These positions with non-zero entries are initialized to the identity matrix, which is the number 0. Then, shift factors are randomly added to these positions column by column. First, the shift values for the five non-zero entries in the first column are randomly added, ranging from 0 to the submatrix dimension p-1.

[0092] Starting with the second column of shift values, each time a shift value is added, a four-ring check is performed on the previously shifted column. If the four-ring detection formula described in the above embodiment is met, a four-ring exists, and the shift value is randomly changed. This process is repeated until all non-zero shift factors have been added. A parity check matrix H1 is obtained that is completely free of four-rings, has a column weight of 5, and is evenly distributed across the rows.

[0093] Although the initial check matrix H1 obtained through the above steps does not contain four rings, since the six-ring constraint is not imposed when adding the shift factor, the generated check matrix H1 will contain a large number of six rings. Since the number of short rings is a major factor affecting the performance of the check matrix, the number of six rings in the H1 matrix is optimized according to the following method to obtain an intermediate check matrix H2 with the minimum number of six rings. Specifically, the following steps are included:

[0094] Starting from the first row of the first column, if the corresponding position in this row and column is not a non-zero item, the six-ring detection formula of the above embodiment is used to count the number of six-rings in the current check matrix H1, record the current total number of six-rings girth6_1, and initialize the flag of the non-zero item to 0.

[0095] Record the shift value m for the nonzero entry at that row and column position. Starting from k = 1, select integers such that k ≤ q (q is the submatrix dimension, and k increases by 1 each time). Set the shift value for that column to (m + k) % q to obtain the transition matrix H1' of the H1 matrix. Perform a four-ring detection on the H1' matrix using the four-ring detection formula. If there are no four-rings in the matrix, use the six-ring detection formula to count the total number of six-rings in the H1' matrix and record the total number of six-rings at that point, girth6_2. Compare girth6_1 with girth6_2. If girth6_2 is less than girth6_1, set the flag for that nonzero entry position to 1, record the value of k at that point, and replace girth6_1 with girth6_2. The shift change value for that position traverses the integers between k = 1 and k ≤ q. Repeat step 3 for each change in k. After the traversal is completed, if the flag of the position is 1 at this time, the latest (m+k)%q is replaced with the shift value of the position.

[0096] Select the next non-zero entry in that column. After updating the shift values of all non-zero entries, start a new round of updates starting from the first column. Continue until the number of six rings remains unchanged in the latest round of updates. At this point, the number of six rings in matrix H2 has reached its minimum, and further changes to the shift values will not reduce the number of six rings in the matrix.

[0097] Through the above steps, the intermediate check matrix H2 can be obtained.

[0098] Currently, 3D TLC and QLC NAND flash memory media have very high bit error rate requirements. The widely used QC-LDPC code decoding method is mostly based on the normalized minimum sum decoding algorithm, with a normalization factor typically ranging from 0.6 to 0.9. The size of the row weights for different rows in the matrix places a high demand on the normalization factor. This is because for each increase in the row weight, the check node information is multiplied by an additional tanh(Lq / 2) according to the original check node update formula. Since the tanh function has a range of (-1, 1), when approximating the normalized minimum sum, the more uniform the row weights, the less impact the selected normalization factor has on the check node information update of each row in the matrix.

[0099] Furthermore, due to the high code rate requirements of QC-LDPC in NAND flash memory, the constructed parity check matrix for NAND flash memory often contains a large number of six-rings. In fact, in the parity check matrix of a high-rate QC-LDPC code, each non-zero entry generates a six-ring with other non-zero entries. To further reduce the impact of rings on matrix performance, while also reducing the average number of decoding iterations and the latency consumed during the decoding process, the codeword convergence process is accelerated.

[0100] Therefore, it is necessary to eliminate some non-zero elements of the generated H2 matrix to obtain the final QL-LDPC check matrix H3 with uniform row weight suitable for 3D NAND flash memory. The specific process is as follows: Figure 3 As shown, the following steps are included:

[0101] Based on the dimensions of the check matrix H2, construct the six-ring distribution matrix H2' corresponding to H2 and the flags for each row and column of H2'. Initialize the flags for H2' and each row and column to 0. Determine the number of nonzero entries to be eliminated and the range of the nonzero entries in the matrix.

[0102] Starting with the first non-zero entry to be eliminated, the six-ring detection formula is used to count the number of six-rings corresponding to each non-zero entry in the H2 matrix, and the maximum number of six-rings is initialized to 0. Starting with each row of the matrix H2', if the flag for that row is 0, within the range of non-zero entries selected for elimination, in all columns where the column flag is 0, the number of six-rings corresponding to each non-zero entry is compared point by point with the initial maximum number of six-rings. The point with the largest number of six-rings within the elimination range is selected. If the number of six-rings at that point is not 0, the row and column flags corresponding to that point are set to 1, the shift value corresponding to that point in the H2 matrix is set to -1, and the next non-zero entry is eliminated. When the number of eliminated non-zero entries reaches an integer multiple of the number of rows in the check matrix H2, the flags for all rows are reset to 0, and this process is repeated until the number of eliminated non-zero entries reaches the target number, resulting in the final check matrix H3.

[0103] For example, a specific matrix example is used for illustration.

[0104] According to the method in this embodiment, a 29×287 matrix suitable for 3D TLC NAND flash memory is constructed.

[0105] First, the dimension of the submatrix is determined to be 128. A PEG-based method is used to construct a parity check matrix H1 with all column weights 5 and uniform row weights. The target range of the matrix is selected and further optimized according to the method in this embodiment to obtain H2. At the same time, H2 is further optimized for short loops to obtain H3. The number of short loops in H1, H2, and H3 is as follows: Figure 4 As shown, it can be seen that compared with the initial H1 matrix, the number of six rings in the H3 matrix is only one sixtieth of the initial matrix. The reduction in the number of short rings will further break the trap set composed of these short rings and accelerate the information transmission between variable nodes and check nodes during the decoding process.

[0106] The matrix constructed by the construction method of the present invention was further simulated for hard decoding performance. Under the same test conditions, the decoding performance of the initial structure H1 and the optimized H3 were tested. The BER (bit error rate) decoding results are shown in the figure. Figure 5 As shown, the decoding result of FER (frame error rate) is as follows Figure 6 As shown in the figure, it can be seen that the parity check matrix construction method constructed by the method described in the present invention can improve the performance of the parity check matrix. The final constructed matrix has an order of magnitude higher decoding performance than the initial matrix. When the initial error bit number is 270, the FER of the final H3 matrix can reach the order of 1E-4, which can meet the requirements of current 3D QLC NAND flash memory and has a good performance degradation advantage in the waterfall region.

[0107] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0108] The embodiment of the present application also provides a high code rate QC-LDPC check matrix construction device for NAND, the structure of the device is as follows Figure 7 Shown, including:

[0109] Initial generation module 701, used to generate an initial check matrix; the rows of the initial check matrix are evenly distributed and do not have a four-ring structure;

[0110] An intermediate generation module 702 is configured to traverse a preset shift value range for each non-zero item in the initial parity check matrix, select a shift value that minimizes the number of six rings, and generate an intermediate parity check matrix;

[0111] The target generation module 703 is configured to sequentially eliminate the non-zero items that participate in the largest number of six-rings based on the number of six-rings participated by each non-zero item in the intermediate check matrix, to obtain a target check matrix.

[0112] For the description of the features in the embodiment corresponding to the high-rate QC-LDPC check matrix construction device for NAND, please refer to the relevant description of the embodiment corresponding to the high-rate QC-LDPC check matrix construction method for NAND, and will not be repeated here.

[0113] The embodiment of the present application also provides an electronic device, such as Figure 8 As shown, it includes a memory 14 and a processor 20, the memory 10 stores a computer program, and the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the high code rate QC-LDPC check matrix construction method for NAND.

[0114] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned embodiments of the high-rate QC-LDPC check matrix construction method for NAND when running.

[0115] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0116] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the method for constructing a high-rate QC-LDPC check matrix for NAND.

[0117] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps in any of the above-mentioned embodiments of the high-code-rate QC-LDPC check matrix construction method for NAND.

[0118] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0119] The above is a detailed introduction to the high-rate QC-LDPC check matrix construction method, device, equipment, storage medium and program product for NAND provided by this application. This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

Claims

1. A method for constructing a high-rate QC-LDPC check matrix for NAND, characterized in that: The method comprises: Generating an initial check matrix; wherein the rows of the initial check matrix are uniformly distributed and do not have a four-ring structure; For each non-zero entry of the initial parity check matrix, traverse a preset shift value range, select a shift value that minimizes the number of six rings, and generate an intermediate parity check matrix; Based on the number of six-rings participated by each non-zero item in the intermediate check matrix, sequentially eliminating the non-zero items with the largest number of six-rings participated in, to obtain a target check matrix; The generating of the initial check matrix includes: Constructing a basis matrix based on a progressive edge growing method; the column weight of the basis matrix is a first preset column weight, and the number of non-zero entries in each column is equal; Connecting each variable node in the base matrix in sequence to a check node that can maximize the current shortest path length; if there are multiple candidate check nodes that can maximize the shortest path length, selecting the check node with the least number of short loops for connection; During each connection, the four-ring structure is detected by the four-ring detection formula and the uniformity of the row weight is monitored; If a four-ring structure is detected, the check nodes are reselected and the cyclic shift values of the submatrices in the base matrix are adjusted until the four-ring structure is eliminated; Generate an initial check matrix with uniform row weight distribution and no four-ring structure; The generating of the intermediate check matrix comprises: Based on a preset shift value range, traversing the cyclic shift value for each column submatrix of the initial check matrix; For each candidate shift value, generate a temporary check matrix and count the total number of six rings; Select the candidate shift value with the least total number of six rings as the target shift value; Using the target shift value to replace the shift value of the corresponding submatrix in the initial check matrix; When the shift values of all column submatrices in the initial check matrix are replaced, an intermediate check matrix is obtained; and the rows of the intermediate check matrix are uniformly distributed.

2. The method according to claim 1, characterized in that The monitoring of the uniformity of row weight includes: At each connection, calculate the standard deviation of the current row weight; If the standard deviation of row weights exceeds a preset threshold, the positions of non-zero items are redistributed to make the row weights evenly distributed.

3. The method according to claim 1, characterized in that The shift value range is an integer between 0 and the submatrix dimension of the initial check matrix minus 1; and the total number of statistical six rings is achieved by traversing the hexagonal closed path algorithm.

4. The method according to claim 3, characterized in that The method further comprises: In the process of generating the intermediate check matrix, after each shift value adjustment, the four-ring structure is re-detected using the four-ring detection formula to ensure that no new four-ring structure is added.

5. The method according to claim 4, characterized in that The obtaining of the target check matrix includes: For each non-zero item in the intermediate check matrix, count the number of six rings in which each non-zero item participates and generate a six-ring distribution matrix; According to the six-ring distribution matrix, non-zero items are sorted from high to low according to the number of six rings to generate an elimination priority queue; Eliminate the priority queue as described, selecting non-zero items from the head of the queue for elimination round by round, and updating the six-ring distribution matrix and the elimination priority queue after each elimination round; When the number of eliminated non-zero items reaches the preset target, the elimination process is terminated and the target check matrix is generated.

6. The method according to claim 5, characterized in that Generating a six-ring distribution matrix includes: All hexagonal closed paths in the intermediate parity check matrix are traversed using a depth-first search algorithm, marking the number of six-rings involved in each non-zero entry. The generation of the path is determined by the relationship between the cyclic shift values of adjacent sub-matrices in the intermediate parity check matrix. Based on the determined number of six-rings in which each non-zero entry participates, a six-ring distribution matrix is generated.

7. The method according to claim 6, characterized in that The process of selecting non-zero items from the head of the queue for elimination in rounds includes: A flag is set for each row and column of the six-ring distribution matrix. If a row or column has had non-zero entries eliminated in the previous round, operations on the row or column are prohibited in the current round.

8. The method according to claim 7, characterized in that The row and column positions of the six-ring distribution matrix correspond one-to-one to the non-zero entries of the intermediate check matrix, and the matrix element value is the total number of six rings in which the corresponding non-zero entry participates.

9. The method according to claim 8, characterized in that The column weight of the initial check matrix is a first preset column weight; the first preset column weight is determined by a target bit rate and a channel condition; and in the process of constructing the initial check matrix, the column weight of each column is equal to the first preset column weight; The column weight of the intermediate check matrix is a mixed structure of a first preset column weight and a second preset column weight; The second preset column weight is obtained by eliminating non-zero items of the target column in the initial check matrix; The column weight of the target check matrix is a mixed structure of the first preset column weight, the second preset column weight and the third preset column weight; The third preset column weight is obtained by eliminating non-zero items of the intermediate check matrix column by column; The distribution ratio of the hybrid structure is determined based on a target bit rate and a channel noise condition.

10. The method according to any one of claims 1 to 9, characterized in that The four-ring detection formula is: ； Where i k 、j k 、i k+1 and j k+1 are the row and column positions of the non-zero entries in the matrix, and L is the submatrix dimension; The six-ring detection formula is: ； Where i k 、j k 、i k+1 、j k+1 、i k+2 and j k+2 are the row and column positions of the non-zero entries in the matrix, L is the submatrix dimension, and P is the shift value of the submatrix other than the all-zero submatrix.

11. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for constructing a high-rate QC-LDPC check matrix for NAND according to any one of claims 1 to 10 when executing the computer program.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for constructing a high-rate QC-LDPC check matrix for NAND according to any one of claims 1 to 10 are implemented.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for constructing a high-rate QC-LDPC check matrix for NAND according to any one of claims 1 to 10 are implemented.

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