Open-closed loop self-adaptive parallel timing synchronization device for echo high-speed data transmission signals

Abstract

The invention discloses an open-closed loop adaptive parallel timing synchronization device for echo high-speed data transmission signals, and belongs to the field of echo high-speed data transmission. The device comprises a digital parallel down converter, a digital parallel resampler, a digital parallel resampler, a digital parallel matched filter, a digital parallel matched filter and an open-closed loop self-adaptive parallel timing synchronizer. According to the invention, a full-digital parallel signal processing flow is adopted, so that the signal processing rate is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of echo high-speed data transmission, and is particularly applicable to the reception demodulation and timing synchronization of high-speed data transmission signals in the data reception sub-system of a data ground receiving station such as an aircraft. Background Art

[0002] Traditional timing synchronization devices are mainly divided into closed-loop timing synchronization devices and open-loop timing synchronization devices. The core of the closed-loop timing synchronization device is to use a timing phase-locked loop to complete the acquisition of the ideal sampling points of the input signal. Its characteristics are excellent performance and relatively small demodulation loss generated by the timing module. However, during the locking process of the timing synchronization loop, the input data cannot be used by subsequent modules because the timing synchronization has not been completed. Closed-loop timing synchronization is usually used in continuous communication systems. The core of the open-loop timing synchronization device is to estimate the timing deviation of the current data group for a set of data, and then complete the timing synchronization of the current data through one-time digital resampling compensation. Its characteristics are fast response speed and can effectively utilize each independent set of data to be synchronized, so that more valid data can be obtained and provided to subsequent modules. However, its performance is average and its stability is poor. Open-loop timing synchronization algorithms are usually applied to burst communications. The echo high-speed data transmission system is a special continuous communication mode. Its echo signal is continuously transmitted. However, due to changes in the aircraft and the channel, the echo signal may have flash interruption at the receiving end, thus having certain burst communication characteristics. In order to effectively adapt to the signal transmission characteristics of the echo high-speed data transmission system, an open-closed loop adaptive parallel timing synchronization device is designed. This device has important application value in the data reception sub-system of the echo high-speed data transmission data ground receiving station. Summary of the Invention

[0003] The purpose of the present invention is to avoid the deficiencies in the above background art and provide an open-closed loop adaptive parallel timing synchronization device applicable to echo high-speed data transmission signals. The present invention also has the characteristics of high reliability, high stability, and low implementation complexity.

[0004] The purpose of the present invention is achieved as follows:

[0005] An open-closed loop adaptive parallel timing synchronization device applicable to echo high-speed data transmission signals includes a digital parallel down-converter 1, a first digital parallel resampler 2-1, a second digital parallel resampler 2-2, a first digital parallel matched filter 3-1, a second digital parallel matched filter 3-2, and an open-closed loop adaptive parallel timing synchronizer 4;

[0006] The digital parallel down-converter 1 performs digital parallel down-conversion processing on the input 8-channel parallel intermediate-frequency sampling signals, generates two groups of 8-channel parallel digital quadrature baseband signals of I / Q, and transmits them to the first digital parallel resampler 2-1. The first digital parallel resampler 2-1 sets parameters according to the input / output signal sampling multiple ratio, adjusts the internal resampling data rate, and performs digital parallel resampling processing on the input two groups of 8-channel parallel digital quadrature baseband signals according to the closed-loop timing synchronization error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4, so as to complete the closed-loop timing synchronization processing of the input data;

[0007] The second digital parallel resampler 2-1 generates two groups of 8-channel parallel digital baseband signals sampled at twice the symbol rate of I / Q and transmits them to the first digital parallel matched filter 3-1 and the second digital parallel matched filter 3-2 respectively. The first digital parallel matched filter 3-1 and the second digital parallel matched filter 3-2 perform matched filter processing on the input signals respectively, and transmit the processed signals to the second digital parallel resampler 2-2 for processing. The input / output signal sampling multiple ratio of the second digital parallel resampler 2-2 is fixedly set to 1. The second digital parallel resampler 2-2 performs digital parallel resampling processing on the input two groups of 8-channel parallel digital quadrature baseband signals according to the open-loop timing synchronization error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4, so as to complete the open-loop timing synchronization processing of the input data;

[0008] The second digital parallel resampler 2-2 generates and outputs two groups of 8-channel parallel digital baseband signals sampled at twice the symbol rate of I / Q to the subsequent signal processing module for processing. The open-loop and closed-loop adaptive parallel timing synchronizer 4 receives the two groups of 8-channel parallel digital baseband signals of I / Q output by the first digital parallel resampler 2-1, calculates and generates the closed-loop timing synchronization error signal and the open-loop timing synchronization error signal. The open-loop and closed-loop adaptive parallel timing synchronizer 4 transmits the generated closed-loop timing synchronization error signal to the first digital parallel resampler 2-1, and transmits the generated open-loop timing synchronization error signal to the second digital parallel resampler 2-2.

[0009] Preferably, both the first digital parallel resampler 2-1 and the second digital parallel resampler 2-2 include a first data delay unit 5-1 to a sixteenth data delay unit 5-16, a first data combining unit 6-1 and a second data combining unit 6-2, a first filter coefficient memory 7-1 to an eighth filter coefficient memory 7-8, a first data cyclic memory 8-1 to a sixteenth data cyclic memory 8-16, a rate matcher 9, a first weighted summing unit 10-1 to a sixteenth weighted summing unit 10-16, a step controller 11, a first fixed coefficient multiplier 12-1 to an eighth fixed coefficient multiplier 12-8, a first adder 13-1 to an eighth adder 13-8, a first accumulator 14-1 to an eighth accumulator 14-8, a first low-bit truncator 15-1 to an eighth low-bit truncator 15-8, and a first high-bit truncator 16-1 to a second high-bit truncator 16-2.

[0010] Among them, the first data delay unit 5-1 to the sixteenth data delay unit 5-16 respectively receive the I / Q two groups of 8-way parallel digital quadrature baseband signals output by the digital parallel downconverter 1, and respectively perform a one-clock-cycle delay process on the received data. The first data combining unit 6-1 respectively receives the 8-way I-channel parallel data output by the digital parallel downconverter 1, and at the same time receives the 8-way I-channel parallel data output by the first data delay unit 5-1 to the eighth data delay unit 5-8. The second data combining unit 6-2 respectively receives the 8-way Q-channel parallel data output by the digital parallel downconverter 1, and at the same time receives the 8-way Q-channel parallel data output by the first data delay unit 5-9 to the sixteenth data delay unit 5-16. The first data combining unit 6-1 sequentially combines the adjacent 4 input I-channel signals to generate a combined signal with 4 input I-channel signals as a group, and a total of 8 groups of signals are generated. Then, the 8 groups of signals generated are simultaneously transmitted to the first data cyclic memory 8-1 to the eighth data cyclic memory 8-8 in parallel. The second data combining unit 6-2 sequentially combines the adjacent 4 input Q-channel signals to generate a combined signal with 4 input Q-channel signals as a group, and a total of 8 groups of signals are generated. Then, the 8 groups of signals generated are simultaneously transmitted to the ninth data cyclic memory 8-9 to the sixteenth data cyclic memory 8-16 in parallel;

[0011] The storage space addresses in the first data cyclic memory 8-1 to the sixteenth data cyclic memory 8-16 are in a cyclic accumulation mode, so that the combined signals output by the first data combination unit 6-1 and the second data combination unit 6-2 complete cyclic storage respectively; the first data cyclic memory 8-1 and the ninth data cyclic memory 8-9, the second data cyclic memory 8-2 and the tenth data cyclic memory 8-10, the third data cyclic memory 8-3 and the eleventh data cyclic memory 8-11, the fourth data cyclic memory 8-4 and the twelfth data cyclic memory 8-12, the fifth data cyclic memory 8-5 and the thirteenth data cyclic memory 8-13, the sixth data cyclic memory 8-6 and the fourteenth data cyclic memory 8-14, the seventh data cyclic memory 8-7 and the fifteenth data cyclic memory 8-15, the eighth data cyclic memory 8-8 and the sixteenth data cyclic memory 8-16 respectively receive the data read addresses generated and output by the first data high-bit truncator 16-1 to the eighth data high-bit truncator 16-8, and output 1 combined signal stored corresponding to the currently received data read address; the combined signals output by the first data cyclic memory 8-1 to the sixteenth data cyclic memory 8-16 are respectively input into the first weighted summing unit 10-1 to the sixteenth weighted summing unit 10-16; the first filter coefficient memory 7-1 to the eighth filter coefficient memory 7-8 respectively receive the data read addresses output by the first data low-bit truncator 15-1 to the eighth data low-bit truncator 15-8, and output the filter combination coefficients corresponding to the currently received data read address, and each group of output filter combination coefficients includes 4 filter coefficients;

[0012] The first weighted summer 10-1 to the eighth weighted summer 10-8 respectively receive the combined signals output by the first data circular memory 8-1 to the eighth data circular memory 8-8 and the filter combined coefficients output by the first filter coefficient memory 7-1 to the eighth filter coefficient memory 7-8, and sequentially regard 4 filter coefficients in the filter combined coefficients as the weighting values of 4 data in the combined signal, complete the weighted summation operation of the filter combined coefficients and the combined signal, and output the result to the first matched filter 3-1; the ninth weighted summer 10-9 to the sixteenth weighted summer 10-16 respectively receive the combined signals output by the ninth data circular memory 8-9 to the sixteenth data circular memory 8-16 and the filter combined coefficients output by the first filter coefficient memory 7-1 to the eighth filter coefficient memory 7-8, and sequentially regard 4 filter coefficients in the filter combined coefficients as the weighting values of 4 data in the combined signal, complete the weighted summation operation of the filter combined coefficients and the combined signal, and output the result to the second matched filter 3-2; the step controller 11 receives the closed-loop timing error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4 and the ratio setting parameter of the input / output signal sampling multiple, combines them and transmits the result as the initial step value to the first fixed coefficient multiplier 12-1 to the eighth fixed coefficient multiplier 12-8 respectively. The first fixed coefficient multiplier 12-1 to the eighth fixed coefficient multiplier 12-8 respectively multiply the input initial step value by 1, 2, 3, 4, 5, 6, 7, 8, and transmit the signals after the multiplication operation to the first adder 13-1 to the eighth adder 13-8 respectively. The first adder 13-1 to the eighth adder 13-8 respectively perform an addition operation on the signals output by the first fixed coefficient multiplier 12-1 to the eighth fixed coefficient multiplier 12-8 and the signals output by the eighth accumulator 14-8, and transmit the signals obtained after the operation to the first accumulator 14-1 to the eighth accumulator 14-8 respectively. The first accumulator 14-1 to the eighth accumulator 14-8 respectively perform an accumulation calculation on the input signals, generate address information and output them to the first high-order data truncator 16-1 to the eighth high-order data truncator 16-8 and the first low-order data truncator 15-1 to the eighth low-order data truncator 15-8 respectively. The first accumulator 14-1 to the eighth accumulator 14-8 also receive the address information output control signal output by the rate matcher 9. When the address information output control signal is valid, the first accumulator 14-1 to the eighth accumulator 14-8 perform an accumulation operation internally, generate and output address information. When the address information output control signal is invalid, the first accumulator 14-1 to the eighth accumulator 14-8 stop the accumulation operation internally and stop outputting address information;The first high-order truncator 16-1 to the eighth high-order truncator 16-8 respectively receive the address information output by the first accumulator 14-1 to the eighth accumulator 14-8, and after intercepting and processing the high-order address information, output it to the first data cyclic memory 8-1 to the eighth data cyclic memory 8-8 and the ninth data cyclic memory 8-9 to the sixteenth data cyclic memory 8-16 respectively; the first low-order truncator 15-1 to the eighth low-order truncator 15-8 respectively receive the address information output by the first accumulator 14-1 to the eighth accumulator 14-8, and after intercepting and processing the low-order address information, output it to the first filter coefficient memory 7-1 to the eighth filter coefficient memory 7-8; the rate matcher 9 receives the data cumulative combination total data signal output by the second data combination unit 6-2 and the high-order address cumulative total data signal output by the eighth accumulator 14-8, and compares the two received data values, generates an address information output control signal and outputs it.

[0013] Preferably, the open-loop and closed-loop adaptive timing synchronizer 4 includes the first data delayers 17-1 to 17-16, the first squarers 18-1 to 18-16, the first multipliers 19-1 to 19-16, the first subtracters 20-1 to 20-16, the first adder 21-1 and the second adder 21-2, the loop filter 22, the first accumulative truncator 23-1 and the second accumulative truncator 23-2, the divider 24, the phase calculator 25 and the phase discrimination mapper 26;

[0014] Among them, the first data delay unit 17-1 to the eighth data delay unit 17-8 respectively receive 8 I-channel parallel digital baseband signals output by the first digital parallel matching filter 3-1, and respectively perform a one-clock-cycle delay process on the received data. The ninth data delay unit 17-9 to the sixteenth data delay unit 17-16 respectively receive 8 Q-channel parallel digital baseband signals output by the second digital parallel matching filter 3-2, and respectively perform a one-clock-cycle delay process on the received data. The first squarer 18-1 to the sixteenth squarer 18-16 respectively receive the signals output by the first data delay unit 17-1 to the sixteenth data delay unit 17-16, and respectively perform a squaring operation on the received signals. The first multiplier 19-1 receives the signals output by the first data delay unit 17-1 and the second data delay unit 17-2, performs a multiplication operation and outputs. The second multiplier 19-2 receives the signals output by the second data delay unit 17-2 and the third data delay unit 17-3, performs a multiplication operation and outputs. The third multiplier 19-3 receives the signals output by the third data delay unit 17-3 and the fourth data delay unit 17-4, performs a multiplication operation and outputs. The fourth multiplier 19-4 receives the signals output by the fourth data delay unit 17-4 and the fifth data delay unit 17-5, performs a multiplication operation and outputs. The fifth multiplier 19-5 receives the signals output by the fifth data delay unit 17-5 and the sixth data delay unit 17-6, performs a multiplication operation and outputs. The sixth multiplier 19-6 receives the signals output by the sixth data delay unit 17-6 and the seventh data delay unit 17-7, performs a multiplication operation and outputs. The seventh multiplier 19-7 receives the signals output by the seventh data delay unit 17-7 and the eighth data delay unit 17-8, performs a multiplication operation and outputs. The ninth multiplier 19-9 receives the signals output by the ninth data delay unit 17-9 and the tenth data delay unit 17-10, performs a multiplication operation and outputs. The tenth multiplier 19-10 receives the signals output by the tenth data delay unit 17-10 and the eleventh data delay unit 17-11, performs a multiplication operation and outputs. The eleventh multiplier 19-11 receives the signals output by the eleventh data delay unit 17-11 and the twelfth data delay unit 17-12, performs a multiplication operation and outputs. The twelfth multiplier 19-12 receives the signals output by the twelfth data delay unit 17-12 and the thirteenth data delay unit 17-13, performs a multiplication operation and outputs. The thirteenth multiplier 19-13 receives the signals output by the thirteenth data delay unit 17-13 and the fourteenth data delay unit 17-14, performs a multiplication operation and outputs. The fourteenth multiplier 19-14 receives the signals output by the fourteenth data delay unit 17-14 and the fifteenth data delay unit 17-15, performs a multiplication operation and outputs. The fifteenth multiplier 19-15 receives the signals output by the fifteenth data delay unit 17-15 and the sixteenth data delay unit 17-16, performs a multiplication operation and outputs.The sixteenth multiplier 19-16 receives the Q9-channel signals output by the sixteenth data delay unit 17-16 and the second digital parallel matching filter 3-2, performs a multiplication operation and outputs the result. The first subtractor 20-1 receives the signals output by the first squarer 18-1 and the second squarer 18-2 respectively, performs a subtraction operation and outputs the result. The second subtractor 20-2 receives the signals output by the third squarer 18-3 and the fourth squarer 18-4 respectively, performs a subtraction operation and outputs the result. The third subtractor 20-3 receives the signals output by the fifth squarer 18-5 and the sixth squarer 18-6 respectively, performs a subtraction operation and outputs the result. The fourth subtractor 20-4 receives the signals output by the seventh squarer 18-7 and the eighth squarer 18-8 respectively, performs a subtraction operation and outputs the result. The fifth subtractor 20-5 receives the signals output by the ninth squarer 18-9 and the tenth squarer 18-10 respectively, performs a subtraction operation and outputs the result. The sixth subtractor 20-6 receives the signals output by the eleventh squarer 18-11 and the twelfth squarer 18-12 respectively, performs a subtraction operation and outputs the result. The seventh subtractor 20-7 receives the signals output by the thirteenth squarer 18-13 and the fourteenth squarer 18-14 respectively, performs a subtraction operation and outputs the result. The eighth subtractor 20-8 receives the signals output by the fifteenth squarer 18-15 and the sixteenth squarer 18-16 respectively, performs a subtraction operation and outputs the result. The ninth subtractor 20-9 receives the signals output by the first multiplier 19-1 and the second multiplier 19-2 respectively, performs a subtraction operation and outputs the result. The tenth subtractor 20-10 receives the signals output by the third multiplier 19-3 and the fourth multiplier 19-4 respectively, performs a subtraction operation and outputs the result. The eleventh subtractor 20-11 receives the signals output by the fifth multiplier 19-5 and the sixth multiplier 19-6 respectively, performs a subtraction operation and outputs the result. The twelfth subtractor 20-12 receives the signals output by the seventh multiplier 19-7 and the eighth multiplier 19-8 respectively, performs a subtraction operation and outputs the result. The thirteenth subtractor 20-13 receives the signals output by the ninth multiplier 19-9 and the tenth multiplier 19-10 respectively, performs a subtraction operation and outputs the result. The fourteenth subtractor 20-14 receives the signals output by the eleventh multiplier 19-11 and the twelfth multiplier 19-12 respectively, performs a subtraction operation and outputs the result. The fifteenth subtractor 20-15 receives the signals output by the thirteenth multiplier 19-13 and the fourteenth multiplier 19-14 respectively, performs a subtraction operation and outputs the result. The sixteenth subtractor 20-16 receives the signals output by the fifteenth multiplier 19-15 and the sixteenth multiplier 19-16 respectively, performs a subtraction operation and outputs the result. The first adder 21-1 receives the signals output by the first subtractor 20-1 to the eighth subtractor 20-8 respectively, performs a multi-channel addition operation and outputs the result. The second adder 21-2 receives the signals output by the ninth subtractor 20-9 to the sixteenth subtractor 20-16 respectively, performs a multi-channel addition operation and outputs the result. The loop filter 22 receives the signal output by the first adder 21-2.After the loop filtering process is completed, it is transmitted to the first digital parallel resampler 2-1 as a closed-loop timing synchronization error signal. The first accumulator truncator 23-1 and the second accumulator truncator 23-2 respectively receive the signals output by the first adder 21-1 and the second adder 21-2, perform accumulative truncation processing on the received signals respectively and output them. The divider 24 respectively receives the signals transmitted by the first accumulator truncator 23-1 and the second accumulator truncator 23-2, completes the division operation, and transmits the operation signal to the phase calculator 25. The phase calculator 25 calculates the phase value corresponding to the current input signal according to the method of sine value phase calculation for the input data, and transmits it to the phase discrimination mapper 26. The phase discrimination mapper makes a decision on the input phase signal. When the phase signal is greater than the phase threshold, the phase signal is linearly mapped into an open-loop timing synchronization error signal. When the phase signal is less than or equal to the phase threshold, the open-loop timing synchronization error signal is mapped to 0. The phase discrimination mapper 26 transmits the mapped open-loop timing synchronization error signal to the second digital parallel resampler 2-2.

[0015] The present invention has the following advantages compared with the background technology:

[0016] 1. The present invention adopts a fully digital parallel signal processing flow, effectively improving the signal processing rate.

[0017] 2. The present invention uses two-stage digital parallel resamplers to perform closed-loop timing synchronization and open-loop timing synchronization processing respectively, improving the flexibility and stability of the timing synchronization device.

[0018] 3. The present invention uses an open-closed loop adaptive timing synchronizer to effectively combine the advantages of closed-loop timing synchronization performance and the response speed advantage of open-loop timing synchronization, improving the overall effectiveness of the timing synchronization device.

[0019] 4. The present invention is implemented in a fully digital manner, with a simple structure and strong portability. Since units such as ROM, look-up table, multiplier, and adder are integrated in current mainstream FPGAs, the present invention can be implemented through embedded software and has the value of popularization and application. Description of the Drawings

[0020] Figure 1 is the principle block diagram of the present invention.

[0021] Figure 2 is the circuit schematic diagram of the digital parallel resampler of the present invention.

[0022] Figure 3 is the circuit schematic diagram of the open-closed loop adaptive parallel timing synchronizer of the present invention. Detailed Embodiment

[0023] Refer to Figures 1 to 3, the present invention includes a digital parallel down-converter 1, digital parallel resamplers 2-1 and 2-2, digital parallel matched filters 3-1 and 3-2, and an open-loop and closed-loop adaptive parallel timing synchronizer 4. The digital parallel down-converter 1 performs digital parallel down-conversion processing on the input 8-channel parallel intermediate-frequency sampling signals, generates two groups of 8-channel parallel digital quadrature baseband signals of I / Q, and transmits them to the digital parallel resampler 2-1. The digital parallel resampler 2-1 sets parameters according to the input-output signal sampling multiple ratio, automatically adjusts its internal resampling data rate, and performs digital parallel resampling processing on the input two groups of 8-channel parallel digital quadrature baseband signals according to the closed-loop timing synchronization error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4, so as to complete the closed-loop timing synchronization processing of the input data. The digital parallel resampler 2-1 generates two groups of 8-channel parallel digital baseband signals sampled at twice the symbol rate of I / Q and transmits them to the digital parallel matched filter 3-1 and the digital parallel matched filter 3-2 respectively. The digital parallel matched filter 3-1 and the digital parallel matched filter 3-2 respectively perform matched filter processing on the input signals and transmit the processed signals to the digital parallel resampler 2-2 for processing. The input-output signal sampling multiple ratio setting parameter of the digital parallel resampler 2-2 is fixedly set to 1. The digital parallel resampler 2-2 performs digital parallel resampling processing on the input two groups of 8-channel parallel digital quadrature baseband signals according to the open-loop timing synchronization error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4, so as to complete the open-loop timing synchronization processing of the input data. The digital parallel resampler 2-2 generates and outputs two groups of 8-channel parallel digital baseband signals sampled at twice the symbol rate of I / Q to the subsequent signal processing module for processing. The open-loop and closed-loop adaptive parallel timing synchronizer 4 receives the two groups of 8-channel parallel digital baseband signals of I / Q output by the digital parallel resampler 2-1, calculates and generates a closed-loop timing synchronization error signal and an open-loop timing synchronization error signal. The open-loop and closed-loop adaptive parallel timing synchronizer 4 transmits the generated closed-loop timing synchronization error signal to the digital parallel resampler 2-1 and transmits the generated open-loop timing synchronization error signal to the digital parallel resampler 2-2. In the embodiment, the digital parallel down-converter 1, the digital parallel resamplers 2-1 and 2-2, the digital parallel matched filters 3-1 and 3-2, and the open-loop and closed-loop adaptive parallel timing synchronizer 4 are implemented by using a Virtex7 type FPGA.

[0024] Figure 2 is the principle block diagram of the digital parallel resampler. The example is according to Figure 2Connection line, digital parallel resampler 2-1 and digital parallel resampler 2-2 include data delayers 5-1 to 5-16, data combination units 6-1 and 6-2, filter coefficient memories 7-1 to 7-8, data cyclic memories 8-1 to 8-16, rate matcher 9, weighted summing units 10-1 to 10-16, step controller 11, fixed coefficient multipliers 12-1 to 12-8, adders 13-1 to 13-8, accumulators 14-1 to 14-8, data low truncators 15-1 to 15-8, and data high truncators 16-1 to 16-2. Among them, data delayers 5-1 to 5-16 respectively receive the I / Q two groups of 8-way parallel digital quadrature baseband signals output by digital parallel downconverter 1, and respectively perform a one-clock-cycle delay process on the received data. Data combination unit 6-1 respectively receives the 8-way I-channel parallel data output by digital parallel downconverter 1, and at the same time receives the 8-way I-channel parallel data output by data delayers 5-1 to 5-8. Data combination unit 6-2 respectively receives the 8-way Q-channel parallel data output by digital parallel downconverter 1, and at the same time receives the 8-way Q-channel parallel data output by data delayers 5-9 to 5-16. Data combination unit 6-1 sequentially combines the adjacent 4 I-channel input signals that have been input, generates a combined signal with 4 I-channel input signals as a group, and generates a total of 8 groups of signals. Then, the 8 groups of signals generated are simultaneously transmitted to data cyclic memories 8-1 to 8-8 in a parallel manner. The parallel signal output by data combination unit 6-1 can be expressed as: I1 I2 I3I4 I2 I3 I4 I5 I3 I4 I5 I6 I4 I5 I6 I7 I5I6 I7 I8 I6 I7 I8 I9 I7 I8 I9 I10 I8I9 I10 I11. Data combination unit 6-2 sequentially combines the adjacent 4 Q-channel input signals that have been input, generates a combined signal with 4 Q-channel input signals as a group, and generates a total of 8 groups of signals. Then, the 8 groups of signals generated are simultaneously transmitted to data cyclic memories 8-9 to 8-16 in a parallel manner. The parallel signal output by data combination unit 6-2 can be expressed as: Q1 Q2 Q3 Q4Q2 Q3 Q4 Q5 Q3 Q4 Q5 Q6 Q4 Q5 Q6 Q7 Q5 Q6 Q7 Q8 Q6 Q7 Q8 Q9Q7 Q8Q9 Q10 Q8 Q9 Q10 Q11. The storage space addresses in data cyclic memories 8-1 to 8-16 are in a cyclic accumulation mode, so that the combined signals output by data combination unit 6-1 and data combination unit 6-2 respectively complete cyclic storage;The data loop memories 8-1 and 8-9, data loop memories 8-2 and 8-10, data loop memories 8-3 and 8-11, data loop memories 8-4 and 8-12, data loop memories 8-5 and 8-13, data loop memories 8-6 and 8-14, data loop memories 8-7 and 8-15, and data loop memories 8-8 and 8-16 respectively receive the data read addresses generated and output by the high-bit truncators 16-1 to 16-8, and output 1 stored combined signal corresponding to the currently received data read address; the combined signals output by the data loop memories 8-1 to 8-16 are respectively input to the weighted summing units 10-1 to 10-6; the filter coefficient memories 7-1 to 7-8 respectively receive the data read addresses output by the low-bit truncators 15-1 to 15-8, and output the filter combined coefficients corresponding to the currently received data read address, and each group of output filter combined coefficients includes 4 filter coefficients; the weighted summing units 10-1 to 10-8 respectively receive the combined signals output by the data loop memories 8-1 to 8-8 and the filter combined coefficients output by the filter coefficient memories 7-1 to 7-8, and sequentially use the 4 filter coefficients in the filter combined coefficients as the weighting values of the 4 data in the combined signal, complete the weighted summation operation of the filter combined coefficients and the combined signal, and output the result to the matched filter 3-1; the weighted summing units 10-9 to 10-16 respectively receive the combined signals output by the data loop memories 8-9 to 8-16 and the filter combined coefficients output by the filter coefficient memories 7-1 to 7-8, and sequentially use the 4 filter coefficients in the filter combined coefficients as the weighting values of the 4 data in the combined signal, complete the weighted summation operation of the filter combined coefficients and the combined signal, and output the result to the matched filter 3-2;The step controller 11 receives the closed-loop timing error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4 and the setting parameter of the sampling multiple ratio of the input and output signals, combines them, and transmits the combined result as the initial step value to the fixed coefficient multipliers 12-1 to 12-8 respectively. The fixed coefficient multipliers 12-1 to 12-8 multiply the input initial step values by 1, 2, 3, 4, 5, 6, 7, and 8 respectively, and transmit the signals after the multiplication operation to the adders 13-1 to 13-8 respectively. The adders 13-1 to 13-8 perform addition operations on the signals output by the fixed coefficient multipliers 12-1 to 12-8 and the signals output by the accumulator 14-8 respectively, and transmit the signals obtained after the operation to the accumulators 14-1 to 14-8 respectively. The accumulators 14-1 to 14-8 perform accumulation calculations on the input signals respectively, generate address information, and output them to the high-order data truncators 16-1 to 16-8 and the low-order data truncators 15-1 to 15-8 respectively. The accumulators 14-1 to 14-8 also receive the address information output control signal output by the rate matcher 9. When the address information output control signal is valid, the accumulators 14-1 to 14-8 perform accumulation operations internally, generate and output address information. When the address information output control signal is invalid, the accumulators 14-1 to 14-8 stop the accumulation operation internally and stop outputting address information. The high-order data truncators 16-1 to 16-8 receive the address information output by the accumulators 14-1 to 14-8 respectively, and output the high-order address information after truncation processing to the data cyclic memories 8-1 to 8-8 and the data cyclic memories 8-9 to 8-16 respectively. The low-order data truncators 15-1 to 15-8 receive the address information output by the accumulators 14-1 to 14-8 respectively, and output the low-order address information after truncation processing to the filter coefficient memories 7-1 to 7-8. The rate matcher 9 receives the total data signal of the data accumulation combination output by the data combination unit 6-2 and the total data signal of the high-order address accumulation output by the accumulator 14-8, compares the two received data numerically, generates an address information output control signal and outputs it;

[0025] Figure 3 is the principle block diagram of the open-loop and closed-loop adaptive parallel timing synchronizer. The example is according to Figure 3Connection line. The open-loop and closed-loop adaptive timing synchronizer 4 includes data delayers 17-1 to 17-16, squarers 18-1 to 18-16, multipliers 19-1 to 19-16, subtracters 20-1 to 20-16, adders 21-1 and 21-2, loop filter 22, accumulative truncators 23-1 and 23-2, divider 24, phase calculator 25, and phase discrimination mapper 26. Among them, data delayers 17-1 to 17-8 respectively receive 8 I-channel parallel digital baseband signals output by the digital parallel matched filter 3-1, and respectively perform a one-clock-cycle delay process on the received data. Data delayers 17-9 to 17-16 respectively receive 8 Q-channel parallel digital baseband signals output by the digital parallel matched filter 3-2, and respectively perform a one-clock-cycle delay process on the received data. Squarers 18-1 to 18-16 respectively receive the signals output by data delayers 17-1 to 17-16, and respectively perform a squaring operation on the received signals. Multiplier 19-1 receives the signals output by data delayer 17-1 and data delayer 17-2, performs a multiplication operation and outputs. Multiplier 19-2 receives the signals output by data delayer 17-2 and data delayer 17-3, performs a multiplication operation and outputs. Multiplier 19-3 receives the signals output by data delayer 17-3 and data delayer 17-4, performs a multiplication operation and outputs. Multiplier 19-4 receives the signals output by data delayer 17-4 and data delayer 17-5, performs a multiplication operation and outputs. Multiplier 19-5 receives the signals output by data delayer 17-5 and data delayer 17-6, performs a multiplication operation and outputs. Multiplier 19-6 receives the signals output by data delayer 17-6 and data delayer 17-7, performs a multiplication operation and outputs. Multiplier 19-7 receives the signals output by data delayer 17-7 and data delayer 17-8, performs a multiplication operation and outputs. Multiplier 19-9 receives the signals output by data delayer 17-9 and data delayer 17-10, performs a multiplication operation and outputs. Multiplier 19-10 receives the signals output by data delayer 17-10 and data delayer 17-11, performs a multiplication operation and outputs. Multiplier 19-11 receives the signals output by data delayer 17-11 and data delayer 17-12, performs a multiplication operation and outputs. Multiplier 19-12 receives the signals output by data delayer 17-12 and data delayer 17-13, performs a multiplication operation and outputs. Multiplier 19-13 receives the signals output by data delayer 17-13 and data delayer 17-14, performs a multiplication operation and outputs. Multiplier 19-14 receives the signals output by data delayer 17-14 and data delayer 17-15, performs a multiplication operation and outputs. Multiplier 19-15 receives the signals output by data delayer 17-15 and data delayer 17-16,Perform multiplication and output. The multiplier 19-16 receives the Q9-channel signals output by the data delay unit 17-16 and the digital parallel matched filter 3-2, performs multiplication and outputs. The subtracter 20-1 receives the signals output by the squarer 18-1 and the squarer 18-2 respectively, completes the subtraction operation and outputs. The subtracter 20-2 receives the signals output by the squarer 18-3 and the squarer 18-4 respectively, completes the subtraction operation and outputs. The subtracter 20-3 receives the signals output by the squarer 18-5 and the squarer 18-6 respectively, completes the subtraction operation and outputs. The subtracter 20-4 receives the signals output by the squarer 18-7 and the squarer 18-8 respectively, completes the subtraction operation and outputs. The subtracter 20-5 receives the signals output by the squarer 18-9 and the squarer 18-10 respectively, completes the subtraction operation and outputs. The subtracter 20-6 receives the signals output by the squarer 18-11 and the squarer 18-12 respectively, completes the subtraction operation and outputs. The subtracter 20-7 receives the signals output by the squarer 18-13 and the squarer 18-14 respectively, completes the subtraction operation and outputs. The subtracter 20-8 receives the signals output by the squarer 18-15 and the squarer 18-16 respectively, completes the subtraction operation and outputs. The subtracter 20-9 receives the signals output by the multiplier 19-1 and the multiplier 19-2 respectively, completes the subtraction operation and outputs. The subtracter 20-10 receives the signals output by the multiplier 19-3 and the multiplier 19-4 respectively, completes the subtraction operation and outputs. The subtracter 20-11 receives the signals output by the multiplier 19-5 and the multiplier 19-6 respectively, completes the subtraction operation and outputs. The subtracter 20-12 receives the signals output by the multiplier 19-7 and the multiplier 19-8 respectively, completes the subtraction operation and outputs. The subtracter 20-13 receives the signals output by the multiplier 19-9 and the multiplier 19-10 respectively, completes the subtraction operation and outputs. The subtracter 20-14 receives the signals output by the multiplier 19-11 and the multiplier 19-12 respectively, completes the subtraction operation and outputs. The subtracter 20-15 receives the signals output by the multiplier 19-13 and the multiplier 19-14 respectively, completes the subtraction operation and outputs. The subtracter 20-16 receives the signals output by the multiplier 19-15 and the multiplier 19-16 respectively, completes the subtraction operation and outputs. The adder 21-1 receives the signals output by the subtracters 20-1 to 20-8 respectively, completes the multi-channel addition operation and outputs. The adder 21-2 receives the signals output by the subtracters 20-9 to 20-16 respectively, completes the multi-channel addition operation and outputs. The loop filter 22 receives the signal output by the adder 21-2, completes the loop filtering process, and transmits it to the digital parallel resampler 2-1 as the closed-loop timing synchronization error signal. The accumulative truncation unit 23-1 and the accumulative truncation unit 23-2 receive the signals output by the adder 21-1 and the adder 21-2 respectively, perform accumulative truncation processing on the received signals and output.The divider 24 receives the signals transmitted by the accumulative truncator 23-1 and the accumulative truncator 23-2 respectively, completes the division operation, and transmits the signal after the operation to the phase calculator 25. The phase calculator 25 calculates the phase value corresponding to the current input signal according to the method of sine value phase calculation for the input data, and transmits it to the phase discrimination mapper 26. The phase discrimination mapper makes a decision on the input phase signal. When the phase signal is greater than the phase threshold, the phase signal is linearly mapped into an open-loop timing synchronization error signal. When the phase signal is less than or equal to the phase threshold, the open-loop timing synchronization error signal is mapped to 0. The phase discrimination mapper 26 transmits the mapped open-loop timing synchronization error signal to the digital parallel resampler 2-2.

[0026] The brief working principle of the present invention is as follows:

[0027] When an open-loop and closed-loop adaptive parallel timing synchronization device applicable to echo high-speed data transmission signals is working, the digital parallel down-converter 1 performs digital parallel down-conversion processing on the input 8-channel parallel intermediate-frequency sampling signals, generates two groups of 8-channel parallel digital quadrature baseband signals of I / Q, and transmits them to the digital parallel resampler 2-1. The digital parallel resampler 2-1 sets parameters according to the input-output signal sampling multiple ratio, automatically adjusts the internal resampling data rate, and performs digital parallel resampling processing on the input two groups of 8-channel parallel digital quadrature baseband signals according to the closed-loop timing synchronization error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4, so as to complete the closed-loop timing synchronization processing of the input data. The digital parallel resampler 2-1 generates two groups of 8-channel parallel digital baseband signals sampled at twice the symbol rate of I / Q and transmits them to the digital parallel matched filter 3-1 and the digital parallel matched filter 3-2 respectively. The digital parallel matched filter 3-1 and the digital parallel matched filter 3-2 perform matched filter processing on the input signals respectively, and transmit the processed signals to the digital parallel resampler 2-2 for processing. The input-output signal sampling multiple ratio of the digital parallel resampler 2-2 is fixedly set to 1. The digital parallel resampler 2-2 performs digital parallel resampling processing on the input two groups of 8-channel parallel digital quadrature baseband signals according to the open-loop timing synchronization error signal output by the open-loop and closed-loop adaptive parallel timing synchronizer 4, so as to complete the open-loop timing synchronization processing of the input data. The digital parallel resampler 2-2 generates and outputs two groups of 8-channel parallel digital baseband signals sampled at twice the symbol rate of I / Q to the subsequent signal processing module for processing. The open-loop and closed-loop adaptive parallel timing synchronizer 4 receives the two groups of 8-channel parallel digital baseband signals of I / Q output by the digital parallel resampler 2-1, calculates and generates the closed-loop timing synchronization error signal and the open-loop timing synchronization error signal. The open-loop and closed-loop adaptive parallel timing synchronizer 4 transmits the generated closed-loop timing synchronization error signal to the digital parallel resampler 2-1, and transmits the generated open-loop timing synchronization error signal to the digital parallel resampler 2-2.

Claims

1. An open-closed loop adaptive parallel timing synchronization device for echo high-speed digital transmission signals, characterized in that: It comprises a digital parallel down-converter (1), a first digital parallel resampler (2-1), a second digital parallel resampler (2-2), a first digital parallel matching filter (3-1), a second digital parallel matching filter (3-2) and an open-closed loop adaptive parallel timing synchronizer (4); The digital parallel down-converter (1) performs digital parallel down-conversion processing on the input 8-channel parallel intermediate frequency sampling signals, generates two groups of 8-channel I / Q parallel digital orthogonal baseband signals and transmits them to the first digital parallel resampler (2-1). The first digital parallel resampler (2-1) sets parameters according to the input input and output signal sampling multiple ratio, adjusts its internal resampling data rate, and performs digital parallel resampling processing on the input I / Q two groups of 8-channel parallel digital orthogonal baseband signals according to the closed-loop timing synchronization error signal output by the open-closed-loop adaptive parallel timing synchronizer (4), thereby completing the closed-loop timing synchronization processing of the input data; The second digital parallel resampler (2-1) generates two groups of 8 parallel I / Q digital baseband signals sampled at a double symbol rate and transmits them to the first digital parallel matched filter (3-1) and the second digital parallel matched filter (3-2) respectively. The first digital parallel matched filter (3-1) and the second digital parallel matched filter (3-2) respectively perform matched filter processing on the input signals and transmit the processed signals to the second digital parallel resampler (2-2) for processing. The input and output signal sampling multiple ratio setting parameter of the second digital parallel resampler (2-2) is fixedly set to 1. The second digital parallel resampler (2-2) performs digital parallel resampling processing on the input two groups of 8 parallel I / Q digital orthogonal baseband signals according to the open-loop timing synchronization error signal output by the open-loop adaptive parallel timing synchronizer (4), thereby completing the open-loop timing synchronization processing of the input data; The second digital parallel resampler (2-2) generates and outputs two groups of 8 parallel I / Q digital baseband signals sampled at a double symbol rate to a subsequent signal processing module for processing. The open-closed-loop adaptive parallel timing synchronizer (4) receives the two groups of 8 parallel I / Q digital baseband signals output by the first digital parallel resampler (2-1), calculates and generates a closed-loop timing synchronization error signal and an open-loop timing synchronization error signal. The open-closed-loop adaptive parallel timing synchronizer (4) transmits the generated closed-loop timing synchronization error signal to the first digital parallel resampler (2-1), and transmits the generated open-loop timing synchronization error signal to the second digital parallel resampler (2-2).

2. The open-closed loop adaptive parallel timing synchronization device for echo high-speed digital transmission signals according to claim 1, characterized in that: The first digital parallel resampler (2-1) and the second digital parallel resampler (2-2) each include a first data delayer (5-1) to a sixteenth data delayer (5-16), a first data combination unit (6-1) and a second data combination unit (6-2), a first filter coefficient memory (7-1) to an eighth filter coefficient memory (7-8), a first data loop memory (8-1) to a sixteenth data loop memory (8-16), a rate matcher (9), a first weighted summer (10 -1) to the sixteenth weighted summer (10-16), a step controller (11), a first fixed coefficient multiplier (12-1) to an eighth fixed coefficient multiplier (12-8), a first adder (13-1) to an eighth adder (13-8), a first accumulator (14-1) to an eighth accumulator (14-8), a first data low-order truncation device (15-1) to an eighth data low-order truncation device (15-8), and a first data high-order truncation device (16-1) to a second data high-order truncation device (16-2). The first data delayer (5-1) to the sixteenth data delayer (5-16) respectively receive two groups of 8-channel I / Q parallel digital orthogonal baseband signals output by the digital parallel down converter (1), and respectively perform a clock cycle delay process on the received data; the first data combination unit (6-1) respectively receives the 8-channel I-channel parallel data output by the digital parallel down converter (1), and simultaneously receives the 8-channel I-channel parallel data output by the first data delayer (5-1) to the eighth data delayer (5-8); the second data combination unit (6-2) respectively receives the 8-channel Q-channel parallel data output by the digital parallel down converter (1), and simultaneously receives the 8-channel Q-channel parallel data output by the first data delayer (5-9) to the sixteenth data delayer (5-16); 16) output 8-channel Q-channel parallel data, the first data combination unit (6-1) sequentially combines the adjacent 4 I-channel input signals to generate a combination signal with 4 I-channel input signals as a group, generating 8 groups of signals in total, and then transmits the generated 8 groups of signals in parallel to the first data circulation memory (8-1) to the eighth data circulation memory (8-8), the second data combination unit (6-2) sequentially combines the adjacent 4 Q-channel input signals to generate a combination signal with 4 Q-channel input signals as a group, generating 8 groups of signals in total, and then transmits the generated 8 groups of signals in parallel to the ninth data circulation memory (8-9) to the sixteenth data circulation memory (8-16); The storage space addresses in the first data circulation memory (8-1) to the sixteenth data circulation memory (8-16) are in a cyclic accumulation mode, so that the combined signals output by the first data combination unit (6-1) and the second data combination unit (6-2) are respectively completed with cyclic storage; the first data circulation memory (8-1) and the ninth data circulation memory (8-9), the second data circulation memory (8-2) and the tenth data circulation memory (8-10), the third data circulation memory (8-3) and the eleventh data circulation memory (8-11), the fourth data circulation memory (8-4) and the twelfth data circulation memory (8-12), the fifth data circulation memory (8-5) and the thirteenth data circulation memory (8-13), the sixth data circulation memory (8-6) and the fourteenth data circulation memory (8-14), the seventh data circulation memory (8-7) and the fifteenth data circulation memory (8 -15), the eighth data loop memory (8-8) and the sixteenth data loop memory (8-16) respectively receive the data reading addresses generated and output by the first data high-order truncation device (16-1) to the eighth data high-order truncation device (16-8), and output a stored combination signal corresponding to the currently received data reading address; the combination signals output by the first data loop memory (8-1) to the sixteenth data loop memory (8-16) are respectively input into the first weighted summer (10-1) to the sixteenth weighted summer (10-16); the first filter coefficient memory (7-1) to the eighth filter coefficient memory (7-8) respectively receive the data reading addresses output by the first data low-order truncation device (15-1) to the eighth data low-order truncation device (15-8), and output the filter combination coefficients corresponding to the currently received data reading address, and each group of output filter combination coefficients includes 4 filter coefficients; The first weighted summer (10-1) to the eighth weighted summer (10-8) respectively receive the combined signal output by the first data loop memory (8-1) to the eighth data loop memory (8-8) and the filter combination coefficient output by the first filter coefficient memory (7-1) to the eighth filter coefficient memory (7-8), and sequentially use the four filter coefficients in the filter combination coefficient as the weighted values ​​of the four data in the combined signal to complete the weighted summation operation of the filter combination coefficient and the combined signal, and output the result to the first matched filter (3-1); the ninth weighted summer (10-9) to the sixteenth weighted summer (10-16) respectively receive the combined signal output by the ninth data loop memory (8-9) to the sixteenth data loop memory The combined signal output by the first filter coefficient memory (8-16) and the filter combination coefficient output by the first filter coefficient memory (7-1) to the eighth filter coefficient memory (7-8), and the four filter coefficients in the filter combination coefficient are sequentially used as the weighted values ​​of the four data in the combined signal to complete the weighted summation operation of the filter combination coefficient and the combined signal, and the result is output to the second matched filter (3-2); the step controller (11) receives the closed-loop timing error signal output by the open-closed-loop adaptive parallel timing synchronizer (4) and the input-output signal sampling multiple ratio setting parameter, merges them and transmits them as the initial step value to the first fixed coefficient multiplier (12-1) to the eighth fixed coefficient multiplier (12-8), and the first fixed coefficient multiplier The first adder (12-1) to the eighth fixed coefficient multiplier (12-8) respectively multiply the input initial step value by 1, 2, 3, 4, 5, 6, 7, 8, and transmit the multiplied signals to the first adder (13-1) to the eighth adder (13-8), respectively. The first adder (13-1) to the eighth adder (13-8) respectively perform addition operations on the signals output by the first fixed coefficient multiplier (12-1) to the eighth fixed coefficient multiplier (12-8) and the signal output by the eighth accumulator (14-8), and transmit the signals obtained after the operations to the first accumulator (14-1) to the eighth accumulator (14-8), respectively. The first accumulator (14-1) to the eighth accumulator (14-8) respectively perform addition operations on the input signals. The first accumulator (14-1) to the eighth accumulator (14-8) perform accumulation calculations to generate address information and output the information to the first data high-order truncation device (16-1) to the eighth data high-order truncation device (16-8) and the first data low-order truncation device (15-1) to the eighth data low-order truncation device (15-8), respectively. The first accumulator (14-1) to the eighth accumulator (14-8) simultaneously receive the address information output control signal output by the rate matcher (9). When the address information output control signal is valid, the first accumulator (14-1) to the eighth accumulator (14-8) perform accumulation calculations internally to generate and output address information. When the address information output control signal is invalid, the first accumulator (14-1) to the eighth accumulator (14-8) stop accumulating calculations internally and stop outputting address information.The first data high-order truncation device (16-1) to the eighth data high-order truncation device (16-8) respectively receive the address information output by the first accumulator (14-1) to the eighth accumulator (14-8), and intercept and process the high-order address information and output it to the first data circulation memory (8-1) to the eighth data circulation memory (8-8) and the ninth data circulation memory (8-9) to the sixteenth data circulation memory (8-16) respectively; the first data low-order truncation device (15-1) to the eighth data low-order truncation device (15-8) respectively receive the address information output by the first accumulator (14-1) to the eighth accumulator (14-8), and intercept and process the high-order address information and output it to the first data circulation memory (8-1) to the eighth data circulation memory (8-8) and the ninth data circulation memory (8-9) to the sixteenth data circulation memory (8-16) respectively; The first accumulator (14-1) to the eighth accumulator (14-8) receive the address information output by the first accumulator (14-1) to the eighth accumulator (14-8), and output the low-order address information to the first filter coefficient memory (7-1) to the eighth filter coefficient memory (7-8) after intercepting and processing; the rate matcher (9) receives the data cumulative combined total data signal output by the second data combination unit (6-2) and the address high-order cumulative total data signal output by the eighth accumulator (14-8), and compares the received two data, generates an address information output control signal and outputs it.

3. The open-closed loop adaptive parallel timing synchronization device for echo high-speed digital transmission signals according to claim 1, characterized in that: The open-closed loop adaptive timing synchronizer (4) comprises a first data delayer (17-1) to a sixteenth data delayer (17-16), a first squarer (18-1) to a sixteenth squarer (18-16), a first multiplier (19-1) to a sixteenth multiplier (19-16), a first subtractor (20-1) to a sixteenth subtractor (20-16), a first adder (21-1) and a second adder (21-2), a loop filter (22), a first accumulator truncation device (23-1) and a second accumulator truncation device (23-2), a divider (24), a phase calculator (25) and a phase discrimination mapper (26); The first data delayer (17-1) to the eighth data delayer (17-8) respectively receive the eight I-channel parallel digital baseband signals output by the first digital parallel matching filter (3-1), and respectively perform a clock cycle delay processing on the received data; the ninth data delayer (17-9) to the sixteenth data delayer (17-16) respectively receive the eight Q-channel parallel digital baseband signals output by the second digital parallel matching filter (3-2), and respectively perform a clock cycle delay processing on the received data; the first squarer (18-1) to the sixteenth squarer (18-16) respectively receive the signals output by the first data delayer (17-1) to the sixteenth data delayer (17-16), and respectively perform a clock cycle delay processing on the received signals. The first multiplier (19-1) receives the signals output by the first data delayer (17-1) and the second data delayer (17-2), performs multiplication operation and outputs the signals, the second multiplier (19-2) receives the signals output by the second data delayer (17-2) and the third data delayer (17-3), performs multiplication operation and outputs the signals, the third multiplier (19-3) receives the signals output by the third data delayer (17-3) and the fourth data delayer (17-4), performs multiplication operation and outputs the signals, the fourth multiplier (19-4) receives the signals output by the fourth data delayer (17-4) and the fifth data delayer (17-5), performs multiplication operation and outputs the signals, and the fifth multiplier (19-5) receives the signals output by the fifth data delayer (17-5). The sixth multiplier (19-6) receives the signal output by the sixth data delay (17-6) and the seventh data delay (17-7), performs multiplication operation and outputs the signal, the seventh multiplier (19-7) receives the signal output by the seventh data delay (17-7) and the eighth data delay (17-8), performs multiplication operation and outputs the signal, the ninth multiplier (19-9) receives the signal output by the ninth data delay (17-9) and the tenth data delay (17-10), performs multiplication operation and outputs the signal, the tenth multiplier (19-10) receives the signal output by the tenth data delay (17-10) and the eleventh data delay (17-11), performs multiplication operation and outputs the signal, The eleventh multiplier (19-11) receives the signal output by the eleventh data delayer (17-11) and the twelfth data delayer (17-12), performs multiplication operation and outputs the signal; the twelfth multiplier (19-12) receives the signal output by the twelfth data delayer (17-12) and the thirteenth data delayer (17-13), performs multiplication operation and outputs the signal; the third multiplier (19-13) receives the signal output by the third data delayer (17-13) and the fourteenth data delayer (17-14), performs multiplication operation and outputs the signal; the fourteenth multiplier (19-14) receives the signal output by the fourteenth data delayer (17-14) and the fifteenth data delayer (17-15);The first subtractor (20-1) receives the signals output by the first squarer (18-1) and the second squarer (18-2), performs a subtraction operation and outputs the signals; the second subtractor (20-2) receives the signals output by the third squarer (18-3) and the fourth squarer (18-4), performs a subtraction operation and outputs the signals; the fourth subtractor (20-2) receives the signals output by the third squarer (18-3) and the fourth squarer (18-4), performs a subtraction operation and outputs the signals; the fifth multiplier (19-15) receives the signals output by the fifteenth data delayer (17-15) and the sixteenth data delayer (17-16), performs a multiplication operation and outputs the signals; the sixteenth multiplier (19-16) receives the signals output by the sixteenth data delayer (17-16) and the Q9 channel signal output by the second digital parallel matching filter (3-2), performs a multiplication operation and outputs the signals; the first subtractor (20-1) receives the signals output by the first squarer (18-1) and the second squarer (18-2), performs a subtraction operation and outputs the signals; the second subtractor (20-2) receives the signals output by the third squarer (18-3) and the fourth squarer (18-4), performs a subtraction operation and outputs the signals; The third subtractor (20-3) receives the signals output by the fifth squarer (18-5) and the sixth squarer (18-6) respectively, performs a subtraction operation and outputs the signals, the fourth subtractor (20-4) receives the signals output by the seventh squarer (18-7) and the eighth squarer (18-8) respectively, performs a subtraction operation and outputs the signals, the fifth subtractor (20-5) receives the signals output by the ninth squarer (18-9) and the tenth squarer (18-10) respectively, performs a subtraction operation and outputs the signals, the sixth subtractor (20-6) receives the signals output by the eleventh squarer (18-11) and the twelfth squarer (18-12) respectively, performs a subtraction operation and outputs the signals, the seventh subtractor (20-7) receives the signals output by the thirteenth squarer (18-1 The eighth subtractor (20-8) receives the signals output by the fifteenth squarer (18-15) and the sixteenth squarer (18-16), respectively, and performs a subtraction operation and outputs the signals. The ninth subtractor (20-9) receives the signals output by the first multiplier (19-1) and the second multiplier (19-2), respectively, and performs a subtraction operation and outputs the signals. The tenth subtractor (20-10) receives the signals output by the third multiplier (19-3) and the fourth multiplier (19-4), respectively, and performs a subtraction operation and outputs the signals. The eleventh subtractor (20-11) receives the signals output by the fifth multiplier (19-5) and the sixth multiplier (19-6), respectively. The twelfth subtractor (20-12) receives the signals output by the seventh multiplier (19-7) and the eighth multiplier (19-8), performs a subtraction operation and outputs the signals. The thirteenth subtractor (20-13) receives the signals output by the ninth multiplier (19-9) and the tenth multiplier (19-10), performs a subtraction operation and outputs the signals. The fourteenth subtractor (20-14) receives the signals output by the eleventh multiplier (19-11) and the twelfth multiplier (19-12), performs a subtraction operation and outputs the signals. The fifteenth subtractor (20-15) receives the signals output by the thirteenth multiplier (19-13) and the fourteenth multiplier (19-14), performs a subtraction operation and outputs the signals.The sixteenth subtractor (20-16) receives the signals outputted by the fifteenth multiplier (19-15) and the sixteenth multiplier (19-16), performs subtraction operation and outputs the signals; the first adder (21-1) receives the signals outputted by the first subtractor (20-1) to the eighth subtractor (20-8), performs multi-channel addition operation and outputs the signals; the second adder (21-2) receives the signals outputted by the ninth subtractor (20-9) to the sixteenth subtractor (20-16), performs multi-channel addition operation and outputs the signals; the loop filter (22) receives the signal outputted by the first adder (21-2), performs loop filtering processing and transmits the signal as a closed-loop timing synchronization error signal to the first digital parallel resampler (2-1); the first accumulator truncation device (23-1) and the second accumulator truncation device (23-2) receive the signals outputted by the first adder (21-1) and the second adder (21-1) and the second adder (21-2) respectively; 21-2) output signal, respectively perform accumulation truncation processing on the received signal and output it, the divider (24) respectively receives the signal transmitted by the first accumulation truncation device (23-1) and the second accumulation truncation device (23-2), completes the division operation, and transmits the calculated signal to the phase calculator (25), the phase calculator (25) calculates the input data according to the sine value phase calculation method to obtain the phase value corresponding to the current input signal, and transmits it to the phase discrimination mapper (26), the phase discrimination mapper judges the input phase signal, when the phase signal is greater than the phase threshold, the phase signal is linearly mapped into an open-loop timing synchronization error signal, when the phase signal is less than or equal to the phase threshold, the open-loop timing synchronization error signal is mapped to 0, the phase discrimination mapper (26) transmits the mapped open-loop timing synchronization error signal to the second digital parallel resampler (2-2).

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