Array substrate and display panel

Abstract

The embodiment of the invention discloses an array substrate and a display panel, an active layer in the array substrate comprises a first lightly doped part, a channel part and a connecting part which are connected in sequence, the first lightly doped part at least covers and is connected with the side surface of an ohmic contact layer, the channel part is arranged on the side wall of an open hole, and the connecting part is arranged on the side wall of the open hole. The connecting part is connected with the second electrode; the active layer further comprises a second lightly-doped part, the second lightly-doped part is connected to one side, close to the ohmic contact layer, of the first lightly-doped part, and the second lightly-doped part is arranged on the hole wall of the open hole. According to the embodiment of the invention, the channel part is arranged on the side wall of the opening, so that a narrow channel is realized; secondly, the second lightly-doped part is added to be connected with the first lightly-doped part, so that the performance of the thin film transistor is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate and a display panel. Background Art

[0002] In recent years, the resolution of exposure machines in panel factories has been around 2 micrometers. The finest planar channels can only reach the micrometer level, making it difficult to fabricate nanoscale channel devices and achieve nanoscale narrow channels. Summary of the Invention

[0003] Embodiments of this application provide an array substrate and a display panel, which can achieve narrow channels while improving the performance of thin-film transistor devices.

[0004] Embodiments of this application provide an array substrate, which includes:

[0005] A substrate;

[0006] An ohmic contact layer disposed on the substrate;

[0007] A first insulating layer covering the ohmic contact layer and the substrate, the first insulating layer being provided with an opening that at least exposes the side surface of the ohmic contact layer;

[0008] A first electrode connected to the ohmic contact layer;

[0009] A second electrode disposed on a side of the first insulating layer away from the substrate;

[0010] An active layer covering the opening, the active layer including a first lightly doped portion, a channel portion, and a connecting portion that are connected in sequence, the first lightly doped portion at least covering the side surface connecting the ohmic contact layer, the channel portion being disposed on the sidewall of the opening, and the connecting portion connecting the second electrode; and

[0011] A gate disposed in a different layer from the active layer;

[0012] Wherein, the active layer further includes a second lightly doped portion, the second lightly doped portion being connected to a side of the first lightly doped portion close to the ohmic contact layer, and the second lightly doped portion being disposed on the pore wall of the opening.

[0013] Optionally, in some embodiments of this application, the active layer further includes an intrinsic semiconductor portion, at least a part of the intrinsic semiconductor portion being disposed on a side of the first insulating layer away from the substrate, and the intrinsic semiconductor portion connecting the second lightly doped portion.

[0014] Optionally, in some embodiments of the present application, the ohmic contact layer includes an extension portion disposed within the opening, and the first lightly doped portion covers the side surface of the extension portion and the surface of the extension portion away from the substrate.

[0015] Optionally, in some embodiments of the present application, the portion of the first lightly doped portion connecting to the channel portion at least contacts the pore wall of the opening.

[0016] Optionally, in some embodiments of the present application, both the first lightly doped portion and the second lightly doped portion have the same doping ions as the ohmic contact layer.

[0017] Optionally, in some embodiments of the present application, both the first lightly doped portion and the second lightly doped portion are configured to be formed by diffusion of the doping ions of the ohmic contact layer into partial regions of the active layer.

[0018] Optionally, in some embodiments of the present application, the active layer is a single-layer silicon-based semiconductor layer, and the semiconductor materials of the first lightly doped portion, the second lightly doped portion, the channel portion, and the connection portion are all polycrystalline silicon semiconductors.

[0019] Optionally, in some embodiments of the present application, the active layer includes a first semiconductor layer and a second semiconductor layer stacked, the second semiconductor layer is located on the side of the first semiconductor layer away from the ohmic contact layer, the thickness of the first semiconductor layer is less than the thickness of the second semiconductor layer, and the first semiconductor layer is configured to slow down the diffusion rate of the doping ions.

[0020] Optionally, in some embodiments of the present application, the doping ions are N-type ions, and the lattice constant of the first semiconductor layer is less than the lattice constant of the second semiconductor layer;

[0021] Or, the doping ions are P-type ions, and the lattice constant of the first semiconductor layer is greater than the lattice constant of the second semiconductor layer.

[0022] Optionally, in some embodiments of the present application, the doping ions are N-type ions, and the first semiconductor layer is a carbon-silicon semiconductor; the doping ions are P-type ions, and the first semiconductor layer is a silicon-germanium semiconductor. N-type ions include phosphorus, arsenic, and antimony; P-type ions include boron.

[0023] Optionally, in some embodiments of the present application, the array substrate further includes a second insulating layer, a third insulating layer, and a pixel electrode. The second insulating layer covers the side of the active layer away from the substrate. The gate is disposed on the side of the second insulating layer away from the substrate. The first electrode is disposed on the side of the first insulating layer away from the substrate and is disposed in the same layer as the second electrode. The connecting portion is connected to the side of the second electrode away from the substrate. The third insulating layer covers the gate, the first electrode, and the second electrode. The pixel electrode is disposed on the side of the third insulating layer away from the substrate. The pixel electrode is connected to the second electrode.

[0024] Correspondingly, an embodiment of the present application further provides a display panel, which includes the array substrate as described in any one of the above embodiments.

[0025] The active layer in the array substrate of the embodiment of the present application includes a first lightly doped portion, a channel portion, and a connecting portion that are connected in sequence. The first lightly doped portion at least covers the side surface connecting the ohmic contact layer. The channel portion is disposed on the sidewall of the opening. The connecting portion is connected to the second electrode. The active layer further includes a second lightly doped portion. The second lightly doped portion is connected to the side of the first lightly doped portion close to the ohmic contact layer. The second lightly doped portion is disposed on the pore wall of the opening.

[0026] It can be understood that in the embodiment of the present application, the channel portion is disposed on the sidewall of the opening to implement a narrow channel. Secondly, the second lightly doped portion is used to connect the first lightly doped portion, increasing the source of carriers injected into the channel, helping to improve the efficiency of the carrier injection channel, and accelerating the response speed of the thin film transistor. Also, based on the fact that the second lightly doped portion is disposed on the side close to the first electrode, it alleviates the phenomenon of high electric field concentration near the first electrode, reduces the hot carrier effect, and improves the reliability of the thin film transistor. In addition, the second lightly doped portion is disposed between the first electrode and the channel portion, which can shield the interference of the electric field of the first electrode on the channel portion and suppress the short channel effect. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of the array substrate provided by the embodiment of the present application;

[0028] Figure 2 is a schematic diagram of step B11 of the method for manufacturing the array substrate provided by the embodiment of the present application;

[0029] Figure 3 is a schematic diagram of step B12 of the method for manufacturing the array substrate provided by the embodiment of the present application;

[0030] Figure 4 is a schematic diagram of step B13 of the method for manufacturing the array substrate provided by the embodiment of the present application;

[0031] Figure 5 It is a schematic diagram of step B14 in the method for preparing an array substrate provided by an embodiment of the present application;

[0032] Figure 6 It is a schematic diagram of step B15 in the method for preparing an array substrate provided by an embodiment of the present application;

[0033] Figure 7 It is a schematic diagram of step B16 in the method for preparing an array substrate provided by an embodiment of the present application;

[0034] Figure 8 It is a schematic diagram of step B17 in the method for preparing an array substrate provided by an embodiment of the present application;

[0035] Figure 9 It is a schematic diagram of step B18 in the method for preparing an array substrate provided by an embodiment of the present application;

[0036] Figure 10 It is another schematic diagram of the structure of the array substrate provided by an embodiment of the present application;

[0037] Figure 11 It is a schematic diagram of the structure of the display panel provided by an embodiment of the present application. Detailed implementation manners

[0038] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the embodiments can be combined with each other without further elaboration, and in the case of no contrary description, the orientation terms such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the drawings; and "inner" and "outer" are relative to the contour of the device; the terms "first", "second", "third", etc. are only used as labels, and do not impose numerical requirements or establish an order.

[0039] An embodiment of the present application provides an array substrate and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0040] Please refer to Figure 1, an embodiment of the present application provides an array substrate 100, which includes a substrate 11, an ohmic contact layer 12, a first insulating layer 131, a first electrode 14, a second electrode 15, an active layer 16, and a gate electrode 17.

[0041] The ohmic contact layer 12 is disposed on the substrate 11. The first insulating layer 131 covers the ohmic contact layer 12 and the substrate 11. The first insulating layer 131 is provided with an opening 13a, and the opening 13a exposes at least the side surface of the ohmic contact layer 12. The first electrode 14 is connected to the ohmic contact layer 12. The second electrode 15 is disposed on a side of the first insulating layer 131 away from the substrate 11. The active layer 16 covers the opening 13a. The gate electrode 17 is disposed in a different layer from the active layer 16.

[0042] The active layer 16 includes a first lightly doped portion 161, a channel portion 163, and a connecting portion 164 that are connected in sequence. The first lightly doped portion 161 covers at least the side surface of the ohmic contact layer 12. The channel portion 163 is disposed on the sidewall of the opening 13a, and the connecting portion 164 is connected to the second electrode 15.

[0043] Wherein, the active layer 16 further includes a second lightly doped portion 162. The second lightly doped portion 162 is connected to a side of the first lightly doped portion 161 close to the ohmic contact layer 12, and the second lightly doped portion 162 is disposed on the pore wall of the opening 13a.

[0044] It can be understood that in the embodiment of the present application, the channel portion 163 is disposed on the sidewall of the opening 13a to implement a narrow channel. Secondly, the second lightly doped portion 162 is used to connect the first lightly doped portion 161, which increases the source of carriers injected into the channel, helps to improve the efficiency of the carrier injection channel, and speeds up the response speed of the thin film transistor. Also, based on the fact that the second lightly doped portion 162 is disposed on a side close to the first electrode 14, it alleviates the phenomenon of high electric field concentration near the first electrode 14, reduces the hot carrier effect, and improves the reliability of the thin film transistor. In addition, the second lightly doped portion 162 is disposed between the first electrode 14 and the channel portion 163, which can shield the interference of the electric field of the first electrode 14 on the channel portion and suppress the short channel effect.

[0045] It should be noted that in the embodiment of the present application, the ohmic contact layer 12, the first electrode 14, the second electrode 15, the active layer 16, and the gate electrode 17 form a thin film transistor. One of the first electrode 14 and the second electrode 15 is a source electrode, and the other of the first electrode 14 and the second electrode 15 is a drain electrode. According to different types of transistors, the source electrode and the drain electrode can be interchanged.

[0046] Optionally, in some embodiments of the present application, the array substrate 100 further includes a second insulating layer 132, a third insulating layer 133, and a pixel electrode 18. The second insulating layer 132 covers the side of the active layer 16 away from the substrate 11. The gate 17 is disposed on the side of the second insulating layer 132 away from the substrate 11. The first electrode 14 is disposed on the side of the first insulating layer 131 away from the substrate 11 and is disposed on the same layer as the second electrode 15. The connecting portion 164 is connected to the side of the second electrode 15 away from the substrate 11. The third insulating layer 133 covers the gate 17, the first electrode 14, and the second electrode 15. The pixel electrode 18 is disposed on the side of the third insulating layer 133 away from the substrate 11, and the pixel electrode 18 is connected to the second electrode 15.

[0047] It should be noted that the second insulating layer 132 covers the active layer 16 to form a recess, and the gate 17 covers the recess. In the plane direction parallel to the substrate 11, the gate 17 and the channel portion 163 are overlapped.

[0048] In some embodiments, the gate 17 may also be disposed between the substrate 11 and the first insulating layer 131. The gate 17 includes a first portion and a second portion disposed in a stacked manner, and the second portion is disposed on the side of the first portion away from the substrate. The first portion is disposed on the same layer as the ohmic contact layer 12 and has the same material, and the conductivity of the second portion is greater than that of the first portion. Optionally, the second portion is a metal and / or a metal alloy. It can be understood that, compared with Figure 1 the corresponding embodiment, disposing the gate 17 below and on the same layer as the ohmic contact layer 12 can save one photomask and save the second insulating layer 132.

[0049] Optionally, in some embodiments of the present application, the active layer 16 further includes an intrinsic semiconductor portion 165, and at least a part of the intrinsic semiconductor portion 165 is disposed on the side of the first insulating layer 131 away from the substrate 11. The intrinsic semiconductor portion 165 is connected to the second lightly doped portion 162.

[0050] It can be understood that, based on the fact that the conductivity of the intrinsic semiconductor portion 165 is less than that of the second lightly doped portion 162, and the intrinsic semiconductor portion 165 is disposed between the first electrode 14 and the channel portion 163, it can shield the interference of the electric field of the first electrode 14 on the channel portion 163 and suppress the short-channel effect. Secondly, the intrinsic semiconductor portion 165 can also be used as a source of carriers to increase the carrier concentration, thereby improving the efficiency of the thin-film transistor.

[0051] Optionally, in some embodiments of the present application, at least a part of the first lightly doped portion 161 connected to the channel portion 163 contacts the pore wall of the opening 13a.

[0052] It can be understood that one end of the first lightly doped portion 161 connecting the channel portion 163 is connected to the pore wall of the opening 13a, so that the channel portion 163 is only disposed on the pore wall of the opening 13a to further narrow the channel portion 163.

[0053] Optionally, in some embodiments of the present application, the first lightly doped portion 161 may further extend up the pore wall of the opening 13a to further narrow the channel portion 163.

[0054] Optionally, in some embodiments of the present application, both the first lightly doped portion 161 and the second lightly doped portion 162 have the same doping ions as the ohmic contact layer 12.

[0055] Wherein, both the first lightly doped portion 161 and the second lightly doped portion 162 are configured to be formed by diffusing the doping ions of the ohmic contact layer 12 into a partial region of the active layer 16.

[0056] It can be understood that forming the lightly doped portion by diffusing the doping ions in the ohmic contact layer 12 into the active layer 16 simplifies the process steps. Among them, the diffusion step of the doping ions and the annealing process of the active layer 16 can be combined, which can further save process steps. For example, the high temperature of the annealing process can be used to promote the diffusion of the doping ions into the active layer 16. In order to provide the accuracy of the doping ion diffusion, the blue laser annealing technology can be used for precise annealing.

[0057] Optionally, the doping ions of the ohmic contact layer 12 can be N-type doping ions or P-type doping ions. The N-type doping ions can include phosphorus, arsenic, antimony, etc., and the P-type doping ions can include boron, etc.

[0058] Optionally, in some embodiments of the present application, the ohmic contact layer 12 includes an extension portion 121 disposed in the opening 13a. The first lightly doped portion 161 covers the side surface of the extension portion 121 and the surface of the extension portion 121 away from the substrate 11.

[0059] It can be understood that compared with the first lightly doped portion 161 only covering the side surface of the ohmic contact layer 12, the embodiment of setting the extension portion 121 increases the contact area between the first lightly doped portion 161 and the ohmic contact layer 12. On the one hand, the length of the first lightly doped portion 161 can be reduced to improve the power-on efficiency; on the other hand, based on the fact that the first lightly doped portion 161 is formed by diffusing the doping ions in the ohmic contact layer 12 into a partial region of the active layer 16, the efficiency of the doping ion diffusion can be improved by setting the extension portion 121.

[0060] Optionally, in some embodiments, the semiconductor material of the active layer 16 is polysilicon semiconductor. When blue laser annealing is performed, amorphous silicon crystallizes to form polysilicon.

[0061] Optionally, in some embodiments of the present application, the active layer 16 is a single-layer silicon-based semiconductor layer. The semiconductor materials of the first lightly doped portion 161, the second lightly doped portion 162, the channel portion 163, and the connection portion 164 are all polycrystalline silicon semiconductors.

[0062] Please refer to Figures 2 to 9 , the method for manufacturing the array substrate 100 according to the embodiment of the present application includes steps B11 to B18.

[0063] Please refer to Figure 2 , in step B11, an ohmic contact layer 12 is formed on the substrate 11.

[0064] Optionally, the ohmic contact layer 12 is deposited by plasma-enhanced chemical vapor deposition. The ohmic contact layer 12 can be an N+ ohmic contact layer, that is, the ohmic contact layer 12 is an ohmic contact layer with heavily doped N-type ions.

[0065] Optionally, the thickness of the ohmic contact layer 12 is between 600 Å and 1500 Å, for example, it can be 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, 1100 Å, 1200 Å, 1300 Å, 1400 Å, or 1500 Å.

[0066] Subsequently, it proceeds to step B12.

[0067] Please refer to Figure 3 , in step B12, a first insulating layer 131 is formed on the substrate 11, and a first contact hole k1 is formed in the first insulating layer 131, and the first contact hole k1 exposes the ohmic contact layer 12.

[0068] Optionally, the first insulating layer 131 can be deposited by plasma-enhanced chemical vapor deposition. The first insulating layer 131 is an interlayer dielectric layer. The material of the first insulating layer 131 can be oxygen silicon or a composite layer of nitrogen silicon and oxygen silicon.

[0069] Optionally, the thickness of the first insulating layer 131 is between 1500 Å and 4000 Å. For example, the thickness of the first insulating layer 131 can be 1500 Å, 2000 Å, 2500 Å, 3000 Å, 3500 Å, or 4000 Å.

[0070] Subsequently, it proceeds to step B13.

[0071] Please refer to Figure 4 , in step B13, a first electrode 14 and a second electrode 15 are formed on the first insulating layer 131.

[0072] Optionally, the first electrode 14 and the second electrode 15 can be formed by physical vapor deposition in combination with yellow light technology and etching technology.

[0073] The thicknesses of the first electrode 14 and the second electrode 15 are between 2000 angstroms and 4500 angstroms. For example, the thicknesses of the first electrode 14 and the second electrode 15 can be 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, or 4500 angstroms.

[0074] Subsequently, proceed to step B14.

[0075] Please refer to Figure 5 , in step B14, pattern the first insulating layer 131 to form an opening 13a that penetrates the first insulating layer 131.

[0076] Optionally, the opening 13a can be formed using a yellow light process and an etching process. The opening 13a exposes at least the side surface of the ohmic contact layer 12.

[0077] Subsequently, proceed to step B15.

[0078] Please refer to Figure 6 , in step B15, form an a-si layer p1 on the substrate 11.

[0079] Optionally, the a-si layer p1 can be deposited using a plasma enhanced chemical vapor deposition process.

[0080] Subsequently, proceed to step B16.

[0081] Please refer to Figure 7 , in step B16, anneal the a-si layer p1 and the portion of the ohmic contact layer 12 near the opening 13a so that the a-si layer p1 is converted into a polysilicon layer p2.

[0082] At this time, the doped ions (such as phosphorus ions) in the ohmic contact layer 12 diffuse into the polysilicon layer p2 to form a first lightly doped portion 161 and a second lightly doped portion 162.

[0083] Optionally, a blue laser is used to anneal the ohmic contact layer 12 and the a-si layer p1.

[0084] Subsequently, proceed to step B17.

[0085] Please refer to Figure 8 , in step B17, form a second insulating layer 132 and a metal layer on the polysilicon layer p2, and then pattern the second insulating layer 132, the gate metal layer, and the polysilicon layer p2 to form an active layer 16 and a gate 17.

[0086] Optionally, the second insulating layer 132 may be deposited by a plasma enhanced chemical vapor deposition process. The thickness of the second insulating layer 132 ranges from 800 angstroms to 2000 angstroms, and may be, for example, 800 angstroms, 1000 angstroms, 1200 angstroms, 1400 angstroms, 1600 angstroms, 1800 angstroms, or 2000 angstroms. Optionally, the second insulating layer 132 is an inorganic material layer, which may be a composite layer of silicon oxide, silicon nitride, or silicon oxynitride.

[0087] Optionally, the metal layer may be formed by a physical vapor deposition process. The material of the metal layer may be a metal such as aluminum / copper, but is not limited thereto. That is, the thickness of the gate 17 ranges from 2000 angstroms to 4500 angstroms, and may be, for example, 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, 4000 angstroms, or 4500 angstroms.

[0088] Optionally, a patterned metal layer and the active layer 16 may be formed by a photolithography process and an etching process.

[0089] Subsequently, the process proceeds to step B18.

[0090] Please refer to Figure 9 , in step B18, a third insulating layer 133 and a pixel electrode 18 are formed on the substrate 11.

[0091] The above are the related steps of the manufacturing method of the array substrate 100 according to the embodiments of the present application.

[0092] It should be noted that the array substrate 100 according to the embodiments of the present application may be used as the array substrate of a liquid crystal display panel, may also be used as the driving substrate of an electroluminescent panel, or may be used as the array substrate of an electronic paper.

[0093] Figure 10 Shown is another structural schematic diagram of the array substrate 100 according to the embodiments of the present application. In Figure 10 the parts that are different from those of the above embodiments will be described to avoid redundancy.

[0094] Compared with the above embodiments, in Figure 10 the corresponding embodiment, optionally, the active layer 16 includes a first semiconductor layer 16a and a second semiconductor layer 16b which are stacked, and the second semiconductor layer 16b is located on the side of the first semiconductor layer 16a away from the ohmic contact layer 12.

[0095] The thickness of the first semiconductor layer 16a is less than the thickness of the second semiconductor layer 16b. The first semiconductor layer 16a is configured to slow down the diffusion rate of the doped ions.

[0096] It can be understood that the first semiconductor layer 16a is configured to slow down the diffusion rate of doping ions to more precisely control the sizes of the first lightly doped portion 161 and the second lightly doped portion 162. That is, the diffusion rate of the doping ions in the first semiconductor layer 16a is less than the diffusion rate of the doping ions in the second semiconductor layer 16b.

[0097] Optionally, in some embodiments, the doping ions are N-type ions, and the lattice constant of the first semiconductor layer 16a is less than the lattice constant of the second semiconductor layer 16b. It can be understood that the lattice constant of the first semiconductor layer 16a is less than the lattice constant of the second semiconductor layer 16b, thereby introducing compressive stress in the silicon layer. This compressive stress can inhibit the diffusion of phosphorus ions (N-type ions).

[0098] For example, the first semiconductor layer 16a is a silicon carbide layer. The atomic radius of carbon is less than that of silicon, and the lattice constant of the silicon carbide layer is less than that of pure silicon.

[0099] Optionally, in some embodiments, the doping ions are P-type ions, and the lattice constant of the first semiconductor layer 16a is greater than the lattice constant of the second semiconductor layer 16b. It can be understood that the lattice constant of the first semiconductor layer 16a is greater than the lattice constant of the second semiconductor layer 16b, thereby introducing tensile stress in the silicon layer. This tensile stress can inhibit the diffusion of boron ions (P-type ions). For example, the first semiconductor layer 16a is a silicon germanium layer. The atomic radius of germanium is greater than that of silicon, and the lattice constant of the silicon germanium layer is greater than that of pure silicon.

[0100] Optionally, based on the fact that the first semiconductor layer 16a is used to block the diffusion of doping ions, in some embodiments, the second electrode 15 can also be lapped on the side of the connecting portion 164 of the active layer 16 away from the substrate 11, that is, the second electrode 15 is connected to the second semiconductor layer 16b to improve the conductivity of the thin film transistor.

[0101] Please refer to Figure 11 , correspondingly, the embodiment of the present application also provides a display panel 1000, which includes the array substrate 100 as described in any one of the above embodiments.

[0102] It should be noted that the structure of the array substrate 100 of the display panel 1000 in the embodiment of the present application is similar to or the same as the structure of the array substrate 100 in any one of the above embodiments. For specific reference, please refer to Figures 1 to 10 the relevant description, which will not be repeated here.

[0103] Optionally, the display panel 1000 further includes a counter substrate 200 and a liquid crystal layer disposed between the counter substrate 200 and the array substrate 100.

[0104] Optionally, in some embodiments, the display panel 1000 can also be an electronic paper or an electroluminescent display panel, etc.

[0105] In the array substrate 100 of the display panel 1000 according to the embodiment of the present application, the active layer 16 includes a first lightly doped portion 161, a channel portion 163, and a connection portion 164 that are connected in sequence. The first lightly doped portion 161 covers at least the side surface of the connection ohmic contact layer 12. The channel portion 163 is disposed on the sidewall of the opening 13a. The connection portion 164 is connected to the second electrode 15. The active layer 16 further includes a second lightly doped portion 162. The second lightly doped portion 162 is connected to the side of the first lightly doped portion 161 close to the ohmic contact layer 12. The second lightly doped portion 162 is disposed on the pore wall of the opening 13a.

[0106] It can be understood that in the embodiment of the present application, the channel portion 163 is disposed on the sidewall of the opening 13a to implement a narrow channel. Secondly, the second lightly doped portion 162 is used to connect the first lightly doped portion 161, which increases the source of the carrier injection channel, helps to improve the efficiency of the carrier injection channel, and speeds up the response speed of the thin film transistor. Also, based on the fact that the second lightly doped portion 162 is disposed on the side close to the first electrode 14, it alleviates the high electric field concentration near the first electrode 14, reduces the hot carrier effect, and improves the reliability of the thin film transistor. In addition, the second lightly doped portion 162 is disposed between the first electrode 14 and the channel portion 163, which can shield the interference of the electric field of the first electrode 14 on the channel portion 163 and suppress the short channel effect.

[0107] The above has introduced in detail an array substrate and a display panel provided by the embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, characterized in that: include: substrate; An ohmic contact layer is disposed on the substrate; a first insulating layer, covering the ohmic contact layer and the substrate, wherein the first insulating layer is provided with an opening, and the opening at least exposes a side surface of the ohmic contact layer; A first electrode connected to the ohmic contact layer; A second electrode is disposed on a side of the first insulating layer away from the substrate; an active layer covering the opening, the active layer comprising a first lightly doped portion, a channel portion and a connecting portion connected in sequence, the first lightly doped portion at least covering a side connected to the ohmic contact layer, the channel portion being arranged on a sidewall of the opening, and the connecting portion being connected to the second electrode; as well as A gate is arranged in a different layer from the active layer; The active layer further includes a second lightly doped portion, the second lightly doped portion is connected to a side of the first lightly doped portion close to the ohmic contact layer, and the second lightly doped portion is arranged on a hole wall of the opening.

2. The array substrate according to claim 1, characterized in that: The active layer further includes an intrinsic semiconductor portion. At least a portion of the intrinsic semiconductor portion is disposed on a side of the first insulating layer away from the substrate, and the intrinsic semiconductor portion is connected to the second lightly doped portion.

3. The array substrate according to claim 1, characterized in that: The ohmic contact layer includes an extension portion disposed in the opening, and the first lightly doped portion covers a side surface of the extension portion and a surface of the extension portion away from the substrate.

4. The array substrate according to claim 1, characterized in that: A portion of the first lightly doped portion connected to the channel portion at least contacts a hole wall of the opening.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The first lightly doped portion and the second lightly doped portion both have the same doping ions as the ohmic contact layer.

6. The array substrate according to claim 5, characterized in that: The first lightly doped portion and the second lightly doped portion are both configured to be formed by diffusion of doping ions of the ohmic contact layer into a partial region of the active layer.

7. The array substrate according to claim 6, characterized in that: The active layer is a single-layer silicon-based semiconductor layer, and the semiconductor materials of the first lightly doped portion, the second lightly doped portion, the channel portion, and the connecting portion are all polycrystalline silicon semiconductors.

8. The array substrate according to claim 6, characterized in that: The active layer includes a first semiconductor layer and a second semiconductor layer which are stacked, the second semiconductor layer is located on a side of the first semiconductor layer away from the ohmic contact layer, the thickness of the first semiconductor layer is less than the thickness of the second semiconductor layer, and the first semiconductor layer is configured to slow down the diffusion rate of the doped ions.

9. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate also includes a second insulating layer, a third insulating layer and a pixel electrode, the second insulating layer covers the side of the active layer away from the substrate, the gate is arranged on the side of the second insulating layer away from the substrate, the first electrode is arranged on the side of the first insulating layer away from the substrate and is arranged in the same layer as the second electrode, the connecting portion is connected to the side of the second electrode away from the substrate, the third insulating layer covers the gate, the first electrode and the second electrode, the pixel electrode is arranged on the side of the third insulating layer away from the substrate, and the pixel electrode is connected to the second electrode.

10. A display panel, characterized in that: Comprising the array substrate as described in any one of claims 1-9.

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