Method for producing an optoelectronic component

Abstract

The description relates to a method of manufacturing an optoelectronic device, comprising the following consecutive steps: a) forming an active diode stack (101) by epitaxial growth on a growth substrate; b) transferring the active diode stack onto a first transfer substrate; c) removing the growth substrate; d) forming a plurality of dies (131) by dicing the first transfer substrate and the active diode stack; and e) transferring the dies onto a second transfer substrate (133), each die comprising a portion of the stack of active diodes.

Description

Technical Field

[0001] The present disclosure generally relates to the field of optoelectronic devices. Specifically, it aims at methods for manufacturing optoelectronic devices, each optoelectronic device including, for example, a plurality of semiconductor diodes based on gallium nitride (GaN) or indium gallium nitride (InGaN), and an electronic circuit for controlling these diodes. Background Art

[0002] Self-emitting display devices have been provided that include an array of gallium nitride-based light-emitting diodes (LEDs) and an electronic control circuit capable of individually controlling the LEDs to display an image. The use of gallium nitride-based LEDs in particular makes it possible to manufacture microdisplays with high brightness values and resolutions.

[0003] To form such a device, it is possible to provide for separately manufacturing the control circuit and the LED array and then connecting them to each other. The LED array of the device can in particular be manufactured by a method that includes the following steps: forming an active stack of LEDs on a substrate, defining the emission areas by photolithography, and then etching the active LED stack, and forming the anode and cathode contacts of each emission area and metal wires connected to pads enabling coupling of the cathode and anode of the emission areas to the control circuit. These methods are specifically described in international application number WO2017 / 068029 and French patent number FR3079350 (DD18591 / B16845) previously filed and obtained by the applicant.

[0004] Once the LED array is formed, it is then connected to the control circuit by a so-called wire bonding operation, by using solder bumps or metal pillars, or by hybrid bonding of the control circuit and the LED array, i.e., by stacking and connecting these two elements to each other. Examples of hybrid bonding are described in international application number WO2017 / 068029 and French patent number FR3079350 mentioned above.

[0005] However, a drawback of this method is that during the step of assembling these two elements, precise alignment of the control circuit and the LED array is required so that each LED is correctly positioned on its corresponding metal pad in the control circuit. This alignment is particularly difficult to achieve when the pixel pitch is reduced and is an obstacle to an increase in resolution and / or pixel integration density.

[0006] To overcome this drawback, in particular in international application number WO2017 / 194845 (DD16946 / B15015) previously filed by the applicant, a method for manufacturing an optoelectronic device is also provided, including the following successive steps:

[0007] a) fabricate the control circuit in the form of an integrated circuit that includes, on its surface, a plurality of metal pads intended to be connected to the LEDs to allow individual control of the current flowing through each LED;

[0008] b) transfer an active stack of LEDs that extends continuously over the entire surface of the control circuit onto the surface of the control circuit that includes the metal pads, so as to connect the semiconductor layers of the active LED stack to the metal pads of the control circuit; and

[0009] c) construct the active LED stack to define the different LEDs of the device and insulate them from each other.

[0010] The advantage of this method lies in the fact that, during the step of transferring the active LED stack onto the control circuit, the positions of the different LEDs of the device in the active LED stack have not yet been defined. Thus, the transfer step does not exhibit any major constraint in terms of alignment accuracy. Then, the definition of the different LEDs in the active stack can be achieved by methods of substrate structuring and deposition of insulating and conductive layers on the substrate, which provides a much higher alignment accuracy than can be achieved during the transfer of one substrate onto another.

[0011] In existing methods, the active LED stack is typically formed by epitaxial growth on a sapphire wafer. While this enables the formation of high-performance LEDs, the use of sapphire wafers has the drawback of generating high manufacturing costs. In addition, sapphire wafers have a diameter equal to approximately 100 mm or 150 mm, while the implementation of the method for forming the control circuit is better adapted to silicon wafers having a larger diameter (e.g., equal to approximately 300 mm). To attempt to solve these problems, an active stack of gallium nitride-based LEDs has been formed on a silicon substrate, e.g., on a silicon wafer having a diameter substantially equal to the diameter of the wafer used for forming the control circuit. However, for certain emission wavelengths, particularly green and red, the LEDs thus formed have a performance level lower than those obtained by using sapphire wafers.

[0012] European Patent Application No. EP 4016594 describes an alternative method which consists in reforming a large-diameter wafer by transferring chips obtained by cutting a second sapphire wafer having a diameter smaller than that of the first wafer (and on which an active stack of LEDs has been previously formed) onto a first silicon wafer typically having a diameter equal to about 200 mm or 300 mm. However, this method has the drawback of including the step of cutting the second wafer, which is carried out in a particularly complex and costly manner, sapphire being a very hard material whose cutting causes chipping of the edges of the chips. In addition, after the chips have been transferred onto the first wafer, the method implements a step of removing the debris of the second wafer resulting from the previous cutting step. This removal step by laser lift-off is difficult to control because the first wafer includes electronic circuits of the CMOS (Complementary Metal Oxide Semiconductor) type, for example, and there is a risk of irreversible damage by exposure to the laser beam.

[0013] Due to the difference in the coefficient of thermal expansion between sapphire and gallium nitride, the gallium nitride-based layers epitaxially grown on the second wafer are also subject to high stress. During the epitaxial growth carried out at a high temperature, one or more gallium nitride-based layers of the active LED stack are epitaxially grown on a thick gallium nitride buffer layer, allowing a lattice constant match between the sapphire of the growth substrate and the gallium nitride of the active stack. Thus, the stress is gradually released within the buffer layer, such that the layers of the active LED stack are under very little stress or no stress at the epitaxial growth temperature of these layers. During the cooling of the second wafer, the stress applied in the buffer layer becomes highly compressive. After removing the wafer of the highly rigid second wafer, the stress in the gallium nitride layer is transferred to the first wafer. This causes very large deformations of the first wafer, for example, of the order of several hundred micrometers, correspondingly making the processing of the reformed substrate incompatible with standard devices of microelectronics.

[0014] European Patent No. EP 3780123 (DD19602 / B18565) previously obtained by the applicant describes yet another method which consists in performing two full-panel transfers before cutting, thus avoiding cutting the sapphire, and then performing a chip-to-board transfer by non-aligned bonding of the type described in the above-mentioned International Application No. WO2017 / 194845. Summary of the Invention

[0015] There is a need to overcome all or part of the drawbacks of existing methods for manufacturing optoelectronic devices.

[0016] For this purpose, an embodiment provides a method for manufacturing an optoelectronic device, including the following successive steps:

[0017] a) forming an active diode stack by epitaxial growth on a growth substrate;

[0018] b) Transfer the active diode stack to a first transfer substrate;

[0019] c) Remove the growth substrate;

[0020] d) Form a plurality of dies by cutting the first transfer substrate and the active diode stack; and

[0021] e) Transfer the dies to a second transfer substrate, each die including a portion of the active diode stack.

[0022] According to an embodiment, the growth substrate or the transfer substrate is heated, preferably to a temperature higher than or equal to 40 °C, more preferably higher than or equal to 70 °C.

[0023] According to an embodiment, at step b), the growth substrate and the transfer substrate are heated, preferably to a temperature higher than or equal to 40 °C.

[0024] According to an embodiment, at step b), the active diode stack is bonded to the first transfer substrate by directly bonding a first bonding layer previously deposited on a surface of the active diode stack opposite to the growth substrate to a second bonding layer previously deposited on the first transfer substrate.

[0025] According to an embodiment, at step b), the surfaces of the first bonding layer and the second bonding layer to be contacted are activated before bonding.

[0026] According to an embodiment, the first bonding layer and the second bonding layer are made of amorphous silicon.

[0027] According to an embodiment, the first bonding layer and the second bonding layer are metal layers, preferably made of titanium.

[0028] According to an embodiment, at step e), the dies are bonded to the second transfer substrate by directly bonding a third bonding layer previously deposited on a surface of the active diode stack opposite to the first transfer substrate to a fourth bonding layer previously deposited on the second transfer substrate.

[0029] According to an embodiment, the third bonding layer and the fourth bonding layer are made of silicon oxide.

[0030] According to an embodiment, the method further includes, after step e), the following steps:

[0031] f) Transfer the component including the second transfer substrate and the portion of the active diode stack to an active substrate including an integrated control circuit.

[0032] According to an embodiment, at step f), the part of the active diode stack and the second transfer substrate are bonded to the active substrate by bonding a first insulating layer previously deposited on the surface of the active diode stack opposite to the second transfer substrate and a first contact element located in the first insulating layer to a second insulating layer previously deposited on the active substrate and a second contact element located in the second insulating layer, respectively.

[0033] According to an embodiment, the method further includes step g) of etching the grains after step e) so as to compensate for the misalignment of the grains with respect to the second transfer substrate.

[0034] According to an embodiment, the method further includes step h) of depositing an insulating layer filling the gaps extending laterally between the grains and then removing a part of the insulating layer vertically aligned with the grains after step g).

[0035] According to an embodiment, the growth substrate is made of sapphire.

[0036] According to an embodiment, the active diode stack includes gallium nitride.

[0037] According to an embodiment, the active diode stack is a stack of light-emitting diodes, including a first semiconductor layer and a second semiconductor layer of opposite conductivity types in sequence starting from the growth substrate. Description of the Drawings

[0038] The foregoing features and advantages, as well as the rest of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0039] Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D 、 Figure 1E 、 Figure 1F 、 Figure 1G 、 Figure 1H 、 Figure 1I 、 Figure 1J 、 Figure 1K 、 Figure 1L and Figure 1M are simplified and partial side and cross-sectional views showing the structure obtained at the end of an example of the steps of an embodiment of a method for manufacturing an optoelectronic device;

[0040] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D are simplified and partial side views and cross-sectional views showing the structure obtained at the end of the steps of an alternative embodiment of the method of Figures 1A to 1M ; and

[0041] Figure 3A 、Figure 3B , Figure 3C and Figure 3D are, respectively, a simplified and partial side view and cross-sectional view showing the structure obtained at the end of the steps of another alternative embodiment of the method of Figures 1A to 1M . DETAILED DESCRIPTION

[0042] In the respective figures, similar features have been designated by like reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numeral, and the same structure, dimensions, and material properties may be set.

[0043] For clarity, only those steps and elements useful for understanding the described embodiments have been shown and described in detail. In particular, applications that may benefit from the described optoelectronic devices have not been detailed, and the described embodiments are compatible with all or most applications of implementing at least one optoelectronic device and may be adjusted within the capabilities of those skilled in the art after reading this disclosure. In addition, the formation of integrated circuits for controlling semiconductor diodes has not been detailed, and the described embodiments are compatible with the usual structure and manufacturing methods of such control circuits. In addition, the composition and arrangement of the different layers of the active semiconductor diode stack have not been detailed, and the described embodiments are compatible with the usual active semiconductor diode stacks (particularly based on gallium nitride).

[0044] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements may be connected, or they may be coupled via one or more other elements.

[0045] In the following description, when referring to absolute position determiners (such as "front", "rear", "top", "bottom", "left", "right", etc.), or relative position determiners (such as "top", "bottom", "upper", "lower", etc.), or orientation determiners (such as "horizontal", "vertical", etc.), unless otherwise specified, the orientation of the drawing is referred to.

[0046] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "roughly" mean plus or minus 10%, preferably plus or minus 5%.

[0047] In the following description, unless otherwise specified, the determiners "insulating" and "conductive" mean electrically insulating and electrically conductive, respectively.

[0048] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E ,Figure 1F , Figure 1G , Figure 1H , Figure 1I , Figure 1J , Figure 1K , Figure 1L and Figure 1M are simplified and partial side and cross-sectional views showing the structure obtained at the end of an example of a step of a method of manufacturing an optoelectronic device.

[0049] Figures 1A to 1M More particularly, it shows the manufacture of an optoelectronic display device that includes an LED array and an electronic control circuit enabling individual control of the LEDs in order to display an image.

[0050] Figure 1A shows the structure obtained at the end of the step of forming the active LED stack 101 on the upper surface of the growth substrate 103 (in the Figure 1A orientation). The active LED stack 101 is, for example, based on gallium nitride (GaN).

[0051] The active LED stack 101 is formed by epitaxial growth from the upper surface of the growth substrate 103. The growth substrate 103 is, for example, a wafer or a piece of a wafer. Preferably, the growth substrate 103 is made of sapphire. Sapphire indeed has the advantage of allowing the growth of high-quality gallium nitride LED stacks.

[0052] In the example shown, the active LED stack 101 includes, in order from the upper surface of the growth substrate 103, an N-type doped gallium nitride layer 105, an emission layer 107, and a P-type doped gallium nitride layer 109. For example, the emission layer 107 or the active layer includes a stack of a plurality of emission layers forming quantum wells, for example layers based on gallium nitride, indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium gallium nitride (AlInGaN), gallium phosphide (GaP), aluminum gallium phosphide (AlGaP), aluminum indium gallium phosphide (AlInGaP), or any combination of one or more of these materials.

[0053] As a variant, the emission layer 107 can be intrinsic, i.e., an unintentionally doped gallium nitride layer, for example having a concentration of residual donor species in the range from 10 15 to 10 18 at / cm 3 , for example about 10 17 at / cm 3 .

[0054] In the example shown, the lower surface of the emission layer 107 contacts the upper surface of the layer 105, and the upper surface of the emission layer 107 contacts the lower surface of the layer 109. In practice, a stack of one or more buffer layers (not shown), such as an undoped gallium nitride layer, can form an interface between the growth substrate 103 and the gallium nitride layer 105.

[0055] As an example, the thickness of the layer 105 ranges from 0.2 μm to 2 μm, for example, about 1 μm. As an example, the thickness of the layer 107 ranges from 30 nm to 300 nm, for example, about 100 nm. As an example, the thickness of the layer 109 ranges from 5 nm to 300 nm, for example, about 100 nm. For example, the active LED stack 101 extends continuously and uniformly in thickness across the entire upper surface of the growth substrate 103.

[0056] Figure 1A The structure also includes a metal layer 111 on the upper surface of the active LED stack 101. In the example shown, the metal layer 111 is deposited on top of the gallium nitride layer 109 and contacts its upper surface. The metal layer 111 is deposited, for example, by the implementation of vacuum deposition techniques, such as by physical vapor deposition (PVD), by vacuum sputtering, by chemical vapor deposition (CVD), or by vacuum evaporation deposition. The metal layer 111 particularly ensures the function of electrical contact on the semiconductor layer 109 of the LED stack 101. The metal layer 111 can also ensure the function of an optical reflector or mirror and / or the function of a barrier for metal element diffusion.

[0057] As an example, the metal layer 111 is formed by a stack of multiple different metal layers (not shown in detail in the drawings), which in order from the upper surface of the semiconductor layer 109 include:

[0058] - A first metal layer, for example made of a transparent and conductive oxide such as indium tin oxide (ITO), contacts the upper surface of the semiconductor layer 109 and provides electrical contact on the semiconductor layer 109;

[0059] - A second metal layer, for example made of titanium nitride (TiN), contacts the upper surface of the first metal layer, and the second metal layer forms a barrier for metal element diffusion; and

[0060] - A third metal layer, for example made of aluminum, contacts the upper surface of the second metal layer, and the third metal layer has an optical reflector function.

[0061] For example, the thickness of the first metal layer is adjusted such that the distance between the quantum well of the emission layer 107 closest to layer 109 and the upper surface of the second metal layer enables constructive interference of light in the structure. This thus allows for optimal light extraction.

[0062] As an example, the first metal layer has a thickness in the range from 20 nm to 100 nm, for example equal to about 60 nm. As an example, the second metal layer has a thickness in the range from 1 nm to 10 nm, for example equal to about 5 nm. As an example, the third metal layer has a thickness in the range from 100 nm to 200 nm, for example equal to about 100 nm.

[0063] As a variant, the metal layer 111 can be formed by any stack of a layer made of a transparent and conductive oxide (such as ITO) and / or a layer based on a metal, a metal alloy, or a metal oxide (such as based on nickel, nickel oxide, nickel aluminide, aluminum, silver, platinum, etc.).

[0064] Figure 1B Shows the structure obtained at the end of the subsequent step of forming the bonding stack 113 on the upper surface of the metal layer 111 of the Figure 1A structure.

[0065] For example, the bonding stack 113 is selected to allow thermal bonding by using a surface activated bonding (SAB) process or an atomic diffusion bonding (ADB) technique, and subsequently removing the material used for bonding without damaging the semiconductor layer 109. As an example, the subsequent removal of the material used for bonding can be carried out by a wet etching process (such as by exposure to hydrofluoric acid and / or nitric acid), or by dry etching (such as by deep reactive ion etching (DRIE) (by using, for example, sulfur hexafluoride (SF6))).

[0066] As an example, the bonding stack 113 includes, in order from the upper surface of the metal layer 111, an insulating layer 115, an optional silicon nitride (SiN) layer 117, and a bonding layer 119. In the example shown, the lower surface of layer 117 is in contact with the upper surface of layer 115, and the upper surface of layer 117 is in contact with the lower surface of layer 119. Layer 115 includes, for example, at least one layer made of an oxide, a nitride, or a oxynitride. As an example, layer 115 is made of silicon oxide (SiO2), silicon nitride, or silicon oxynitride (SiON). As a variant, layer 115 can be an etch stop layer, for example formed by a titanium layer, for example having a thickness of about 10 nm, coated with a titanium nitride layer, for example having a thickness of about 50 nm.

[0067] The bonding layer 119 is made of amorphous silicon (a-Si), for example.

[0068] As an example, layer 115 has a thickness in the range from 300 nm to 600 nm. For example, layer 117 has a thickness of about 200 nm. For example, layer 119 has a thickness of about 20 nm.

[0069] Figure 1C Shown is the structure obtained at the end of the subsequent steps of transferring and bonding the active LED stack 101 to the upper surface of the temporary transfer substrate 121 or handle and then removing the growth substrate 103.

[0070] Prior to that, the bonding layer 123 is formed, for example, on the upper surface of the temporary transfer substrate 121 (in the Figure 1C orientation). The substrate 121 is, for example, a wafer or a piece of a wafer made of a semiconductor material (such as silicon). For example, the substrate 121 has substantially the same lateral dimensions as those of the growth substrate 103.

[0071] The bonding layer 123 is made of the same material as the bonding layer 119 (such as amorphous silicon), for example. The bonding layer 123 has, for example, a thickness substantially the same as that of the bonding layer 119, for example, about 20 nm. For example, the bonding layer 123 extends continuously over the entire upper surface of the substrate 121. Depending on the desired surface condition, the bonding layer 123 may be subjected to a planarization operation prior to the transfer step.

[0072] During the transfer step, the assembly including the growth substrate 103, the active LED stack 101, the metal layer 111, and the bonding stack 113 can be flipped and transferred onto the temporary transfer substrate 121 so as to place the upper surface of the bonding layer 119 (in the Figure 1B orientation) in contact with the upper surface of the bonding layer 123. In this example, the bonding of the active LED stack 101 to the temporary transfer substrate 121 is obtained by directly bonding the lower surface of the bonding layer 119 (in the Figure 1C orientation) to the upper surface of the bonding layer 123. The expression "direct bonding" here means that the bonding is a spontaneous bonding and there is no fluid layer (such as an adhesive layer) at the surface. Although this is a spontaneous bonding, pressure may be applied during bonding.

[0073] As an example, the bonding is more specifically a covalent bonding by controlling the temperature of the substrates 103 and 121 under ultra-high vacuum. For example, the surfaces to be contacted are activated in advance, for example, by bombarding with argon atoms having an energy of about 200 eV, up to about 10 15 at / cm 2The dose. For example, such activation is achieved by implementing the SAB technique mentioned above. As a variant, surface activation bonding (SAB) can be replaced by atomic diffusion bonding (ADB) of ultra-high vacuum deposition of amorphous silicon with a small thickness (for example, in the range from 1 nm to 10 nm). This layer can advantageously replace the previously deposited layer on the surface.

[0074] Before the two bonding surfaces are placed in contact, at least one of the substrates (among the growth substrate 103 and the temporary transfer substrate 121) is heated, for example. As an example, one of the substrates 103, 121 is heated to a temperature about 20 °C or about 50 °C higher than room temperature, for example, a temperature higher than or equal to 40 °C or higher than or equal to 70 °C. In the case where the growth substrate 103 has a thermal expansion coefficient greater than that of the layer 105 and the layer 105 has a thermal expansion coefficient greater than that of the temporary transfer substrate 121, the substrates 103 and 121 are advantageously heated to different temperatures, and the heating temperature of the growth substrate 103 is, for example, greater than the heating temperature of the substrate 121. The fact of heating the growth substrate 103 enables the relaxation of the stress in the layer 105 because this enables approaching the growth temperature. Once bonding occurs and the structure has cooled to room temperature, the difference in thermal expansion coefficients between the materials of the substrate 121 and the substrate 103 causes an increase in stress in the substrates 103 and 121. At the end of the step of removing the growth substrate 103, the layer 105 will be subject to less stress, and thus there will be less deformation of the transfer substrate 121 due to the difference in thermal expansion coefficients between the layer 105 and the temporary transfer substrate 121. Before bonding, the choice of the temperatures taken by the substrates 103 and 121 is, for example, subject to seeking a compromise between two objectives:

[0075] - When it returns to room temperature, maintaining the integrity of the structure because if excessive stress is applied between the substrate 121 and the substrate 103, it is possible to reach the breaking point of the material; and

[0076] - After removing the growth substrate 103, obtaining a slightly bent transfer substrate 121, for example, less than 100 μm or 120 μm, so as to be able to process the structure by standard microelectronic devices, especially dry etching devices of the RIE (reactive ion etching) or ICP (inductively coupled plasma) type.

[0077] As an example, in the case where the growth substrate 103 has a coefficient of thermal expansion greater than that of layer 105, and layer 105 has a coefficient of thermal expansion greater than that of the transfer substrate 121, the growth substrate 103 is heated to a temperature in the range from 95 °C to 150 °C, and the transfer substrate 121 is heated to a temperature of about 40 °C. As a variant, the transfer substrate 121 may not be heated and may be, for example, maintained at room temperature, for example, about 20 °C. Depending on the materials forming the substrates 103 and 121, as a variant, the transfer substrate 121 may be heated to a temperature higher than that of the growth substrate 103, in which case the growth substrate may or may not be heated. For example, this corresponds to the case where the substrate 103 has a lower coefficient of thermal expansion than the substrate 121.

[0078] As a variant, the growth substrate 103 and the temporary transfer substrate 121 are, for example, heated to a temperature about 20 °C or 25 °C higher than room temperature. As an example, the substrates 103 and 121 are each heated to a temperature equal to or higher than 40 °C or 45 °C.

[0079] For example, the removal of the growth substrate 103 is carried out by implementing a laser lift-off (LLO) technique, during which a laser beam is projected through the substrate 103 from its surface opposite to the active LED stack 101. In the case where the temporary transfer substrate 121 warps due to the transfer and bonding of the active LED stack 101, the laser beam is, for example, controlled to perform a spiral scan instead of a raster scan. The laser lift-off step is, for example, followed by a step of removing the gallium bumps formed on the upper surface of layer 105 under the action of the laser (for example, by wet treatment with hydrochloric acid or hot water).

[0080] In the example shown, layer 105 has been thinned, for example, by RIE or ICP on its upper surface side (in the Figure 1C orientation).

[0081] Figure 1D Shown is the structure obtained at the end of a subsequent step of forming another bonding stack 125 on the upper surface of the semiconductor layer 105 of the Figure 1C structure.

[0082] As an example, the bonding stack 125 includes, in order from the upper surface of the semiconductor layer 105, an etch stop layer 127 made of, for example, silicon nitride and a bonding layer 129 made of, for example, silicon oxide. In the example shown, the lower surface of layer 127 is in contact with the upper surface of layer 105, and the upper surface of layer 127 is in contact with the lower surface of layer 129. As an example, the etch stop layer 127 has a thickness equal to about 150 nm. As an example, the bonding layer 129 has a thickness of about 600 nm.

[0083] In addition, during this step, the upper surface of the bonding layer 129 is planarized, for example, by CMP (chemical and mechanical polishing).

[0084] Figure 1E The structure obtained after the subsequent step of cutting the structure of Figure 1D into a plurality of dies 131 is shown. More specifically, the components including the temporary transfer substrate 121, the bonding layer 123, the bonding stack 113, the metal layer 111, the active LED stack 101, and the bonding stack 125 are cut into a plurality of dies 131.

[0085] In the example shown, each die 131 includes portions of the temporary transfer substrate 121, the bonding layer 123, the bonding stack 113, the metal layer 111, the active LED stack 101, and the bonding stack 125. As an example, the cutting of the dies 131 is performed by sawing. For example, the dies 131 have the same size.

[0086] Advantageously, a preliminary step of inspecting the structure of Figure 1D can be provided to detect epitaxial defects. Then, the cutting can be performed in such a way as to concentrate the defects so as to subsequently select the dies 131 with a low defect rate.

[0087] Figure 1F The structure obtained at the end of the subsequent step of transferring and bonding the die 131 to the upper surface of the temporary transfer substrate 133 or the handle and then removing the temporary transfer substrate 121 and the bonding layers 119 and 123 is shown.

[0088] Prior to this, a bonding layer 135 is formed, for example, on the upper surface of the temporary transfer substrate 133 (in the orientation of Figure 1F ). The substrate 133 is, for example, a wafer or a piece of a wafer made of a semiconductor material (such as silicon). For example, the substrate 133 has a lateral dimension larger than those of the growth substrate 103.

[0089] The bonding layer 135 is made of, for example, the same material as the bonding layer 129 (such as silicon oxide). For example, the bonding layer 135 has a thickness substantially equal to or lower than that of the bonding layer 129, for example, about 200 nm. The bonding layer 135 extends continuously over the entire upper surface of the substrate 133.

[0090] During the transfer step, the die 131 can be flipped and transferred onto the temporary substrate 133 so that the lower surface of the bonding layer 129 (in the orientation of Figure 1F contacts the upper surface of the bonding layer 135. In this example, the bonding of the active LED stack 101 to the temporary transfer substrate 133 is achieved by bringing the lower surface of the bonding layer 129 (in the orientation of Figure 1Fobtained by directly bonding to the upper surface of the bonding layer 135 in the orientation of... The direct bonding of the crystal grains 131 to the temporary transfer substrate 133 is, for example, molecular bonding, thermocompression bonding, or eutectic bonding.

[0091] Then, for example, the portions of the transfer substrate 121 and the bonding layers 119 and 123 included in each crystal grain 131 are removed by grinding.

[0092] Figure 1G The structure obtained at the end of the subsequent steps of depositing the encapsulation layer 137, depositing the insulating passivation layer 139, and planarizing the structure is shown.

[0093] In the example shown, the encapsulation layer 137 is deposited on Figure 1F the upper surface side of the structure of... In this example, the layer 137 coats the lateral surface and the upper surface of the crystal grains 131. Then, after deposition, the layer 137 is, for example, more specifically located on top of and in contact with the upper surface of a portion of the layer 117 (or the layer 115 if the layer 117 is omitted), and on top of and in contact with the lateral surfaces of the bonding stack 125, the active LED stack 101, the metal layer 111, the layer 115, and the layer 117. The encapsulation layer 137 is, for example, intended to protect the lateral surfaces of the crystal grains 131 from the penetration of the liquid used during the subsequent wet etching step.

[0094] As an example, the encapsulation layer is made of silicon nitride.

[0095] In the example shown, the insulating passivation layer 139 is then deposited on the entire upper surface of the structure. For example, the layer 139 is deposited with a thickness greater than the cumulative thickness of the bonding stack 125, the active LED stack 101, the metal layer 111, the layer 115, and the layer 117. The layer 139 is, for example, made of an oxide (such as silicon oxide). As an example, the layer 139 has a thickness of about a few micrometers, for example, equal to approximately 3 μm or 4 μm. The layer 139 is then, for example, planarized by CMP to obtain a component with a substantially planar upper surface. This planarization is carried out, for example, by stopping on the layer 117. The layer 117 is then removed by etching. As an example, at the end of the planarization step, the upper surface of the insulating layer 115 is flush with the upper surface of the insulating passivation layer 139.

[0096] Figure 1H The structure obtained at the end of the subsequent steps of defining and individualizing the multiple basic LEDs in each crystal grain 131 is shown.

[0097] In the example shown, trenches 141 are formed in the LED stack 101. In this example, each trench extends vertically from the upper surface of the insulating layer 115, through the conductive layer 111, through the semiconductor layers 109 and 107, and stops at the thickness of the layer 105. As an example, the trenches 141 are formed by etching (by using the material of the layer 115 as a hard mask).

[0098] Figure 1I Shown is the structure obtained at the end of subsequent steps of depositing another insulating passivation layer 143 and forming trenches 145 and vias 147.

[0099] In the example shown, the insulating passivation layer 143 is deposited on the entire upper surface of the structure. The layer 143 is deposited conformally, for example, by a method of the ALD (Atomic Layer Deposition) or PECVD (Plasma-Enhanced Chemical Vapor Deposition) type, in the trenches 141. The layer 143 is made, for example, of an oxide (such as alumina), a nitride (such as silicon nitride or aluminum nitride), or a stack of layers made of these materials. Then, the layer 143 is anisotropically etched, for example, by dry etching of the RIE or ICP type, in order to expose the bottom of the trenches 141.

[0100] In the example shown, trenches 145 are formed in the extension of the previously formed trenches 141. The trenches 145 have a lateral dimension smaller than those of the trenches 141, and the sidewalls of each trench 145 are formed by parts of the insulating passivation layer 143. In the example shown, each trench 145 extends vertically from the upper surface of the insulating layer 115, through the conductive layer 111, through the semiconductor layers 109, 107, and 105, and stops at the thickness of the layer 127 of the bonding stack 125. Among other things, the trenches 145 can insulate a part of the semiconductor layer 105 of each elementary LED from parts of the layer 105 of other LEDs.

[0101] In the example shown, the vias 147 have a depth smaller than the depth of the trenches 145. The vias 147 extend vertically from the upper surface of the layer 115, across the entire thickness of the layer 115. In the example shown, the bottom of each via 147 is formed by a part of the upper surface of the conductive layer 111.

[0102] Figure 1J Shown is the structure obtained at the end of subsequent steps of forming conductive regions 149 in the trenches 145 and vias 147. In the example shown, the regions 149 fill the trenches 145 and vias 147.

[0103] As an example, on the upper surface side of the component, the regions 149 are formed by successive deposition of:

[0104] - at least one mirror layer extending over and in contact with the side surfaces and the tops of the bottoms of the trench 145 and the via 147; - at least one seed layer extending over the mirror layer and in contact with the mirror layer; and

[0105] - at least one filling layer.

[0106] By way of example, the mirror layer is an aluminum layer or a titanium layer coated with an aluminum layer. By way of example, the seed layer is formed by a stack of multiple layers, including a titanium layer, a titanium nitride layer, and a copper layer in that order starting from the mirror layer. By way of example, the filling layer is made of a metal (such as copper) or a metal alloy.

[0107] The region 149 is formed, for example, by a damascene process. The mirror layer is formed, for example, by ion beam deposition (IBD) or physical vapor deposition. The filling layer is formed, for example, by electrochemcial deposition.

[0108] The filling layer is deposited, for example, over the entire upper surface of the component, across a thickness sufficient to fill the trench 145 and the via 147. A step of planarizing the upper surface of the component by chemical mechanical polishing is then, for example, implemented such that the region 149 is flush with a part of the upper surface of the layer 115.

[0109] Figure 1K Shows a structure obtained at the end of subsequent steps of forming a stack 151 of insulating layers 153 and 155 on the upper surface of the structure of Figure 1J , forming a through-conductive via 157 in the stack 151, forming a stack 159 of insulating layers 161 and 163 on the stack 151, and forming contact elements 165 in the stack 159.

[0110] By way of example, the insulating layers 153 and 155 are made of silicon nitride and silicon oxide respectively. The conductive via 157 is made of a metal (such as copper) or a metal alloy, for example. The conductive via 157 is formed, for example, by implementing a damascene process. For example, the conductive via 157 can perform an adjustment of the proportion of conductive material on the upper surface of the component. In the example shown, each conductive via 157 extends vertically through the entire stack 151 and is located on top of and in contact with the upper surface of one of the regions 149.

[0111] By way of example, the insulating layers 161 and 163 are made of silicon nitride and silicon oxide respectively. The contact element 165 is formed, for example, by implementing a damascene process (such as the type described in the French patent number FR3079350 (DD18591 / B16845) previously obtained by the applicant). The contact element 165 is made of a metal (such as copper) or a metal alloy, for example. In the example shown, each contact element 165 extends vertically through the entire stack 159 and is located on top of and in contact with the upper surface of one of the conductive vias 157.

[0112] Figure 1L Shows the structure obtained at the end of the steps of forming a stack 171 of insulating layers 173 and 175 on the surface of a substrate 167 including an active region 169, forming a through-conductive via 177 in the stack 171, forming a stack 179 of insulating layers 181 and 183 on the stack 171, and forming a contact element 185 in the stack 179.

[0113] The substrate 167 is, for example, a wafer or a piece of a wafer made of a semiconductor material (such as silicon). The active region 169 of the substrate 167 includes, for example, a plurality of integrated control circuits. The control circuits (not detailed herein for readability) are formed, for example, in CMOS (complementary metal oxide semiconductor) technology. The control circuits formed in the active region 169 are, for example, of the ASIC (application specific integrated circuit) type. As an example, the substrate 167 has a lateral dimension greater than those of the growth substrate 103. Figure 1L For example, the stacks 171 and 179 are similar or identical to the stacks 151 and 159, respectively. In addition, the conductive via 177 and the contact element 185 are, for example, similar or identical to the conductive via 157 and the contact element 165, respectively.

[0114] For example, the stacks 171 and 179 are similar or identical to the stacks 151 and 159, respectively. In addition, the conductive via 177 and the contact element 185 are, for example, similar or identical to the conductive via 157 and the contact element 165, respectively.

[0115] Figure 1M Shows the structure obtained at the end of the subsequent step of transferring and bonding the Figure 1K components to the Figure 1L components. During this step, the components including the temporary transfer substrate 133, the layer 135, the stack 125, the stack 101, the layer 111, the layer 115, and the stacks 151 and 159 can be flipped with respect to the Figure 1K orientation so as to bond the surface of the LED stack 101 opposite to the substrate 133 to the upper surface of the substrate 167. The lower surface of the insulating layer 163 and the lower surface of the contact element 165 (in the Figure 1M orientation) can be bonded to the upper surface of the insulating layer 183 and the upper surface of the contact element 185, respectively. In this example, the bonding of the active LED stack 101 to the substrate 167 is obtained by direct bonding of the contacting surfaces, for example, more specifically, by hybrid metal-to-oxide bonding. As an example, an annealing operation (for example, at a temperature equal to about 400 °C and a duration of about 2 h) is then carried out in order to consolidate the bonding.

[0116] At the end of the transfer step, the individual LEDs previously defined in the active LED stack 101 are connected to the electronic control circuits formed in the active region 169 of the substrate 167.

[0117] Once the active LED stack 101 is bonded to the upper surface of the substrate 167, the temporary transfer substrate 133 is removed, for example by grinding and then wet etching (with a selective stop on the material of layer 135).

[0118] For example, a chemical-mechanical polishing step is then performed on the upper surface side of the component in order to remove layers 135 and 129. As an example, the chemical-mechanical polishing is stopped on layer 127.

[0119] For example, a passivation layer (not shown) made of silicon nitride is then deposited, for example, on the upper surface side of the component, and the microlenses 187 are vertically formed in correspondence with each elementary LED of the optoelectronic display device. As an example, the microlenses 187 are made of an insulating material such as silicon nitride or gallium nitride.

[0120] Regarding Figures 1A to 1M The advantage of the method described lies in the fact that it does not include the step of cutting the growth substrate 103 into grains or chips. This is particularly advantageous in the case where the growth substrate 103 is made of sapphire, whose material is very difficult to cut.

[0121] Regarding Figures 1A to 1M Another advantage of the method described lies in the fact that the step of removing the growth substrate 103 is carried out before transferring the active LED stack 101 onto the semiconductor substrate 167 (inside which and on top of which the control circuit is integrated). This makes it possible, in the case where such removal is carried out by projecting a laser beam through the substrate 103, for example during a laser lift-off step, not to risk damaging the control circuit.

[0122] Regarding Figures 1A to 1M Yet another advantage of the method described lies in the fact that it is capable of obtaining an optimal optical configuration in terms of light extraction, particularly due to the presence of LEDs with a resonator, the inclination in gallium nitride being favorable for extracting light into the external environment, and the fact that it is possible to fabricate microlenses from gallium nitride.

[0123] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D are simplified and partial side views and cross-sectional views showing the structure obtained at the end of the steps of an alternative embodiment of the method of Figures 1A to 1M . For example, Figures 2A to 2D a variant of

[0124] Figure 2A usually corresponds to the case where the first bond is a metal-to-metal bond. Figure 1A shows the structure obtained at the end of the step of forming the bond stack 201 on the upper surface of the metal layer 111 of the structure of

[0125] In the example shown, the bonding stack 201 includes, in order starting from the upper surface of the metal layer 111, a layer 203 made of a metal nitride (e.g., titanium nitride (TiN)) and a bonding layer 205 made of a metal (e.g., titanium). In the example shown, the lower surface of the layer 203 contacts the upper surface of the metal layer 111, and the upper surface of the layer 203 contacts the lower surface of the layer 205.

[0126] As an example, the layer 203 has a thickness of approximately 40 nm. As an example, the layer 205 has a thickness of approximately 600 nm.

[0127] Although this is not shown in Figure 2A to avoid overloading the drawing, during a subsequent step of removing the layer 205, another layer can be inserted between the layers 203 and 205 to form a stop layer.

[0128] During a subsequent step, for example, similar to the steps described previously above regarding Figures 1C to 1E described steps:

[0129] - For example, Figure 2A the structure of

[0130] - the growth substrate 103 is removed, and a bonding stack 125 is formed on the active LED stack 101; and - the assembly is diced to obtain die 131.

[0131] Figure 2B Shown is the structure obtained at the end of subsequent steps of transferring and bonding the die 131 to the upper surface of the temporary transfer substrate 133, removing a partial thickness of the temporary transfer substrate 121, and depositing the encapsulation layer 137.

[0132] For example, transferring the die 131 to the upper surface of the temporary transfer substrate 133 is performed similarly or identically to that described above regarding Figure 1F described. As an example, the partial removal of the temporary transfer substrate 121 is performed by grinding. For example, the encapsulation layer 137 is deposited on the entire upper surface of the structure, for example, as described previously regarding Figure 1G described.

[0133] Figure 2C Shown is the structure obtained at the end of subsequent steps of removing the entire temporary transfer substrate 133 and removing the bonding layers 123 and 207.

[0134] The temporary transfer substrate 133 is removed, for example, by grinding. As an example, the bonding layers 123 and 207 are removed by etching, for example, by wet etching (utilizing the stop on the metal nitride layer 203).

[0135] Figure 2D Shows the structure obtained at the end of the subsequent step of depositing the passivation layer 139.

[0136] For example, the formation of the passivation layer 139 is similar or identical to that previously described with respect to Figure 1G and will not be elaborated further below.

[0137] Then, for example, from Figure 2D the components are implemented with subsequent steps similar or identical to those previously described with respect to Figures 1H to 1M described.

[0138] For example, Figures 2A to 2D the variant of Figures 1A to 1M has advantages similar or identical to those of the method of

[0139] Figure 3A , Figure 3B , Figure 3C and Figure 3D are respectively a simplified and partial top view, side view, and cross-sectional view, showing the structure obtained at the end of the steps of an alternative implementation of the method of Figures 1A to 1M . For example, Figures 3A to 3D the variant of

[0140] Figure 3A shows the structure obtained at the end of the step of transferring and bonding the die 131 to the bonding layer 135 coating the temporary transfer substrate 133. As an example, the die 131 is obtained according to the steps of the method described above with respect to Figures 1A to 1E .

[0141] The transfer of the die 131 is performed, for example, by implementing a water film bonding technique, such as, for example, as described in European Patent Application No. EP 3593376 previously filed by the applicant.

[0142] In the example shown, the die 131 has a generally square overall shape in the top view. However, this example is not restrictive, and as a variant, the die 131 can have any overall shape, such as rectangular, oval, circular, etc.

[0143] At the end of the transfer and bonding steps, the die 131 is, for example, laterally and / or angularly misaligned with respect to the desired position of the die 131. To overcome this problem, the die 131 is, for example, etched in order to obtain a die 301 aligned with the desired position. To be able to implement such misalignment correction, for example, the die 131 is provided with lateral dimensions greater than those of the desired die 301 after being transferred to the temporary transfer substrate 133.

[0144] Figure 3B shows the structure obtained after subsequent steps of depositing encapsulation layer 137 and depositing insulating passivation layer 139, such as as previously described with respect to Figure 1G discussed.

[0145] Figure 3C shows the structure obtained after subsequent steps of structuring insulating passivation layer 139, for example by lithography followed by vertical etching conforming to each die 131.

[0146] In the example shown, layer 139 is vertically removed conforming to each die 131 in order to expose the upper surface of layer 137 located on each die 131 (in the Figure 3C orientation).

[0147] Figure 3D shows the structure obtained at the end of subsequent steps of planarization on the upper surface side of the temporary transfer substrate 133 (in the Figure 3D orientation). Figure 3C of the

[0148] In the example shown, at the end of this step, the upper surface of insulating passivation layer 139 is flush with the upper surface of die 131, and more specifically, the upper surface of the portion of layer 137 coating each die. As an example, the planarization step is carried out by chemical - mechanical polishing, for example by stopping on layer 137.

[0149] For example, Figures 3A to 3D a variant of Figures 1A to 1M has advantages similar or identical to those of the

[0150] method of Figures 3A to 3D Another advantage of the variant described above with respect to

[0151] is the fact that it can greatly improve the planarity of the component (which is a key element for subsequent implementation of hybrid bonding with substrate 167). Figures 1H to 1M Subsequent steps similar or identical to those previously described with respect to Figure 1G are then carried out, for example, on the

[0152] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants can be combined, and other variants will occur to those skilled in the art. In particular, Figures 2A to 2D a variant of Figures 3A to 3D and a variant of

[0153] In addition, the conductivity types of semiconductor layers 105 (N - type, in the example) and 109 (P - type, in the example) can be reversed.

[0154] In addition, although examples of embodiments of display devices including gallium nitride-based LEDs have been described in detail, the described embodiments can be applied by those skilled in the art to fabricate devices including a plurality of gallium nitride-based photodiodes (individually addressable for obtaining an image).

[0155] More generally, the described embodiments can be applied to fabricate any display device or photosensitive sensor based on semiconductor diodes, including those based on semiconductor materials other than gallium nitride, such as diodes based on other III-V semiconductor materials.

[0156] The embodiments can also be applied to fabricate any electronic device, including a plurality of semiconductor components based on gallium nitride or based on other semiconductor materials (such as III-V materials), and an integrated circuit suitable for individually controlling these components. As an example, the semiconductor components can be power components, such as transistors, diodes, etc.

[0157] Finally, based on the functional indications given above, the actual implementation of the embodiments and variations is within the capabilities of those skilled in the art. In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned in this disclosure.

Claims

1. A method for manufacturing an optoelectronic device, comprising the following consecutive steps: a) forming an active diode stack (101) by epitaxial growth on a growth substrate (103); b) transferring the active diode stack onto a first transfer substrate (121); c) removing the growth substrate; d) forming a plurality of dies (131) by cutting the first transfer substrate and the active diode stack; and e) transferring the dies onto a second transfer substrate (133), each die comprising a portion of the active diode stack.

2. The method according to claim 1, wherein: At step b), the growth substrate (103) or the transfer substrate (121) is heated, preferably to a temperature higher than or equal to 40°C, more preferably higher than or equal to 70°C.

3. The method according to claim 1, wherein: At step b), the growth substrate (103) and the transfer substrate (121) are heated, preferably to a temperature greater than or equal to 40°C.

4. The method according to claim 1, 2 or 3, wherein: At step b), the active diode stack (101) is bonded to the first transfer substrate (121) by directly bonding a first bonding layer (119) previously deposited on a surface of the active diode stack opposite to the growth substrate to a second bonding layer (123) previously deposited on the first transfer substrate.

5. The method according to claim 4, wherein: At step b), surfaces of the first bonding layer (119) and the second bonding layer (123) to be in contact are activated prior to bonding.

6. The method according to claim 4 or 5, wherein: The first bonding layer (119) and the second bonding layer (123) are made of amorphous silicon.

7. The method according to claim 4 or 5, wherein: The first bonding layer (119) and the second bonding layer (123) are metal layers, preferably made of titanium.

8. The method according to any one of claims 1 to 7, wherein: At step e), the die (131) is bonded to the second transfer substrate (133) by directly bonding a third bonding layer (129) previously deposited on the surface of the active diode stack (101) opposite to the first transfer substrate (121) to a fourth bonding layer (135) previously deposited on the second transfer substrate.

9. The method according to claim 8, wherein: The third bonding layer (129) and the fourth bonding layer (135) are made of silicon oxide.

10. The method according to any one of claims 1 to 9, further comprising, after step e), the following steps: f) transferring the assembly comprising the second transfer substrate (133) and parts of the active diode stack (101) onto an active substrate (167) comprising an integrated control circuit.

11. The method according to claim 10, wherein: At step f), a portion of the active diode stack (101) and the second transfer substrate (133) are bonded to the active substrate (167) by bonding a first insulating layer (163) previously deposited on a surface of the active diode stack opposite to the second transfer substrate and a first contact element (165) located in the first insulating layer to a second insulating layer (183) previously deposited on the active substrate and a second contact element (185) located in the second insulating layer, respectively.

12. The method according to any one of claims 1 to 11, further comprising, after step e), a step g) of etching the die (131) in order to compensate for misalignment of the die with respect to the second transfer substrate (133).

13. The method according to claim 12, further comprising, after step g), a step h) of depositing an insulating layer (139) filling the gaps extending laterally between the grains (131), and then removing portions of the insulating layer vertically aligned with the grains (131).

14. The method according to any one of claims 1 to 13, wherein: The growth substrate (103) is made of sapphire.

15. The method according to any one of claims 1 to 14, wherein: The active diode stack (101) comprises gallium nitride.

16. The method according to any one of claims 1 to 15, wherein: The active diode stack (101) is a light emitting diode stack which includes, in order from the growth substrate (103), a first semiconductor layer (105) and a second semiconductor layer (109) of opposite conductivity types.

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