MOS tube current sampling circuit and method

Abstract

The invention discloses an MOS tube current sampling circuit and method, and relates to the technical field of MOS tube current sampling, the circuit comprises a grid voltage adjusting circuit, a mirror image MOS tube and a first resistor; the first end of the grid voltage adjusting circuit is connected with the grid of the main MOS tube, and the second end of the grid voltage adjusting circuit is connected with the grid of the mirror image MOS tube; the source electrode of the mirror image MOS tube and the source electrode of the main MOS tube are connected with source electrode voltage, and the drain electrode of the mirror image MOS tube is connected with the first end of the first resistor; the second end of the first resistor and the drain electrode of the main MOS tube are connected with drain electrode voltage. Therefore, according to the application, the grid voltage of the main MOS transistor and the grid voltage of the mirror image MOS transistor are changed through the grid voltage adjusting circuit so as to adjust the mirror image proportion, high-precision and wide-range trimming on the mirror image proportion by using one mirror image MOS transistor is realized, and the economical efficiency is good.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS transistor current sampling, and particularly to a MOS transistor current sampling circuit and method. Background Art

[0002] MOS transistors are commonly used switching devices in power products. MOS is an abbreviation for MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Sampling the current flowing through the MOS transistor is a prerequisite for completing the closed-loop control and reliability design of power products. Traditional MOS transistor current sampling includes two methods: one is to connect a first resistor in series with the MOS transistor and calculate the current of the MOS transistor through the voltage of the first resistor. For the first MOS transistor current sampling circuit, please refer to Figure 1 as shown; the other is to connect the main MOS transistor in parallel with the mirror MOS transistor, connect the first resistor in series with the mirror MOS transistor, and infer the current of the main MOS transistor by detecting the current of the mirror MOS transistor. For the second MOS transistor current sampling circuit, please refer to Figure 2 as shown. However, for the first current sampling method, the first resistor will pass a large current, resulting in an increase in power loss; for the second current sampling method, the power loss is small, but the detection accuracy is affected by the current mirror ratio.

[0003] Due to process deviations in MOS transistors, the current mirror ratio needs to be trimmed. In the prior art, by setting multiple mirror MOS transistors, each of the multiple mirror MOS transistors is connected in series with a corresponding switch transistor respectively, and by turning on the switch transistors respectively, different current mirror ratios can be set. For the second MOS transistor current sampling circuit with a trimming circuit, please refer to Figure 3 as shown. However, using this trimming method for the current mirror ratio, the trimming accuracy is limited by the minimum channel width and minimum channel length of the MOS transistor, and the trimming range is limited by the layout area of the mirror MOS transistor. Among them, the larger the trimming range, the more mirror MOS transistors are required, and the larger the layout area of the mirror MOS transistors, resulting in poor economy. Summary of the Invention

[0004] The object of the present invention is to provide a MOS transistor current sampling circuit and method, which can adjust the gate voltage of the main MOS transistor and the gate voltage of the mirror MOS transistor through a gate voltage adjustment circuit to adjust the mirror ratio, and realize high-precision and wide-range trimming of the mirror ratio with one mirror MOS transistor, with good economy.

[0005] In a first aspect, the present invention discloses a MOS transistor current sampling circuit, including a gate voltage adjustment circuit, a mirror MOS transistor, and a first resistor;

[0006] The first end of the gate voltage adjustment circuit is connected to the gate of the main MOS transistor, and the second end of the gate voltage adjustment circuit is connected to the gate of the mirror MOS transistor. The gate voltage adjustment circuit is configured to output an adjustable gate voltage of the main MOS transistor and an adjustable gate voltage of the mirror MOS transistor;

[0007] The source of the mirror MOS transistor and the source of the main MOS transistor are both connected to a source voltage, and the drain of the mirror MOS transistor is connected to the first end of the first resistor;

[0008] The second end of the first resistor and the drain of the main MOS transistor are both connected to a drain voltage.

[0009] Optionally, the gate voltage adjustment circuit includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor;

[0010] The negative poles of the first current source and the third current source are both connected to a power supply voltage. The common terminal of the positive pole of the first current source, the negative pole of the second current source, and the first end of the second resistor serves as the first end of the gate voltage adjustment circuit and is connected to the gate of the main MOS transistor;

[0011] The common terminal of the positive pole of the third current source, the negative pole of the fourth current source, and the second end of the second resistor serves as the second end of the gate voltage adjustment circuit and is connected to the gate of the mirror MOS transistor;

[0012] The positive poles of the second current source and the fourth current source are both grounded.

[0013] Optionally, the second resistor is a resistor with adjustable resistance, and / or, the first current source, the second current source, the third current source, and the fourth current source are all adjustable current sources.

[0014] Optionally, the resistor with adjustable resistance includes N parallel resistor branches;

[0015] Each of the resistor branches includes a series-connected sub-resistor and a switch.

[0016] Optionally, the adjustable current source includes N parallel current source branches;

[0017] Each of the current source branches includes a series-connected sub-current source and a switch.

[0018] Optionally, it further includes an amplifier, an AD converter, and a processor;

[0019] The input end of the amplifier is connected to the first resistor and is configured to amplify the voltage across the first resistor to obtain an amplified voltage;

[0020] The input end of the AD converter is connected to the output end of the amplifier, and the output end of the AD converter is connected to the processor. The AD converter is configured to convert the amplified voltage from an analog quantity to a digital quantity;

[0021] The processor is configured to process the amplified digital voltage to obtain the current of the main MOS transistor.

[0022] Optionally, a filtering module is further included. The first end of the filtering module is connected to the output end of the amplifier, and the second end of the filtering module is connected to the input end of the AD converter, and is configured to filter the amplified voltage.

[0023] Optionally, a temperature sensor is further included. The temperature sensor is disposed around the mirror MOS transistor and is configured to collect the ambient temperature of the mirror MOS transistor, so that the processor corrects the current of the main MOS transistor obtained based on the voltage across the first resistor according to the ambient temperature.

[0024] In a second aspect, the present invention further discloses a method for sampling the current of a MOS transistor, which is applied to the MOS transistor current sampling circuit as described above. The method includes:

[0025] Determining a target mirror ratio of the gate voltage of the main MOS transistor and the gate voltage of the mirror MOS transistor in the MOS transistor current sampling circuit;

[0026] Adjusting the gate voltage of the main MOS transistor and the gate voltage of the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit so that the mirror ratio is the target mirror ratio;

[0027] Determining the current of the mirror MOS transistor based on the voltage across the first resistor in the MOS transistor current sampling circuit;

[0028] Determining the current of the main MOS transistor based on the target mirror ratio and the current of the mirror MOS transistor.

[0029] Optionally, the gate voltage adjustment circuit includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor;

[0030] The negative electrodes of the first current source and the third current source are both connected to the power supply voltage. The common terminal of the positive electrode of the first current source, the negative electrode of the second current source, and the first end of the second resistor serves as the first end of the gate voltage adjustment circuit and is connected to the gate of the main MOS transistor;

[0031] The common terminal of the positive electrode of the third current source, the negative electrode of the fourth current source, and the second terminal of the second resistor serves as the second terminal of the gate voltage adjustment circuit and is connected to the gate of the mirror MOS transistor;

[0032] The positive electrodes of the second current source and the fourth current source are both grounded;

[0033] Adjusting the gate voltages of the main MOS transistor and the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit includes:

[0034] Adjusting the currents of the first current source, the second current source, the third current source, and the fourth current source, and / or the resistance value of the second resistor, to adjust the gate voltages of the main MOS transistor and the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit.

[0035] The present application provides a MOS transistor current sampling circuit, which includes a gate voltage adjustment circuit, a mirror MOS transistor, and a first resistor; the first terminal of the gate voltage adjustment circuit is connected to the gate of the main MOS transistor, and the second terminal of the gate voltage adjustment circuit is connected to the gate of the mirror MOS transistor; the source electrodes of the mirror MOS transistor and the main MOS transistor are both connected to the source voltage, and the drain electrode of the mirror MOS transistor is connected to the first terminal of the first resistor; the second terminal of the first resistor and the drain electrode of the main MOS transistor are both connected to the drain voltage. It can be seen that the present application adjusts the mirror ratio by changing the gate voltages of the main MOS transistor and the mirror MOS transistor through the gate voltage adjustment circuit, realizes the high-precision and wide-range trimming of the mirror ratio with one mirror MOS transistor, and has good economy.

[0036] The present application also provides a MOS transistor current sampling method, which has the same beneficial effects as the above MOS transistor current sampling circuit. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is the first MOS transistor current sampling circuit diagram disclosed by the present invention;

[0039] Figure 2 It is the second MOS transistor current sampling circuit diagram disclosed by the present invention;

[0040] Figure 3The second MOS transistor current sampling circuit diagram with a trimming circuit disclosed by the present invention;

[0041] Figure 4 The structural schematic diagram of a MOS transistor current sampling circuit disclosed by the present invention;

[0042] Figure 5 The gate voltage adjustment circuit diagram disclosed by the present invention;

[0043] Figure 6 The flowchart of a MOS transistor current sampling method provided by the present invention;

[0044] The reference signs are as follows: 1 is the gate voltage adjustment circuit. Specific embodiments

[0045] The core of the present invention is to provide a MOS transistor current sampling circuit and method, which can change the gate voltage of the main MOS transistor and the gate voltage of the mirror MOS transistor through the gate voltage adjustment circuit to adjust the mirror ratio, and realize high-precision and wide-range trimming of the mirror ratio with one mirror MOS transistor, and has good economy.

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0047] Due to process deviations of MOS transistors, the mirror ratio needs to be trimmed. In the prior art, by setting multiple mirror MOS transistors, the multiple mirror MOS transistors are respectively connected in series with multiple switching transistors one by one, and by turning on the switching transistors respectively, different current mirror ratios can be set. For the second MOS transistor current sampling circuit with a trimming circuit, please refer to Figure 3 shown. However, using this trimming method for the current mirror ratio, the trimming accuracy is limited by the minimum channel width and minimum channel length of the MOS transistor, and the trimming range is limited by the layout area of the mirror MOS transistor. Among them, the larger the trimming range, the more mirror MOS transistors are required, and the larger the layout area of the mirror MOS transistor, resulting in poor economy. Therefore, the present invention provides a MOS transistor current sampling circuit.

[0048] Specifically, please refer to Figure 4 shown, Figure 4 The structural schematic diagram of a MOS transistor current sampling circuit disclosed by the present invention.

[0049] The MOS transistor current sampling circuit includes a gate voltage adjustment circuit 1, a mirror MOS transistor M2, and a first resistor R1;

[0050] The first end of the gate voltage adjustment circuit 1 is connected to the gate of the main MOS transistor M1, and the second end of the gate voltage adjustment circuit 1 is connected to the gate of the mirror MOS transistor M2;

[0051] The source of the mirror MOS transistor M2 and the source of the main MOS transistor M1 are both connected to the source voltage VS, and the drain of the mirror MOS transistor M2 is connected to the first end of the first resistor R1;

[0052] The second end of the first resistor R1 and the drain of the main MOS transistor M1 are both connected to the drain voltage VD.

[0053] Specifically, the MOS transistor saturation region current formula is as follows:

[0054] ;

[0055] Among them, is the drain current of the MOS transistor, is the electron mobility of the MOS transistor, which characterizes the moving speed of electrons in the semiconductor, is the capacitance of the gate oxide layer of the MOS transistor, W is the channel width of the MOS transistor, L is the channel length of the MOS transistor, is the voltage between the gate and the source of the MOS transistor, is the threshold voltage of the MOS transistor.

[0056] After the channel length and channel width of the main MOS transistor M1 and the channel length and channel width of the mirror MOS transistor M2 are determined, if the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 are equal, then the current ratio, i.e., the mirror ratio, between the main MOS transistor M1 and the mirror MOS transistor M2 is the ratio of the ratio of the channel length and channel width of the main MOS transistor M1 to the ratio of the channel length and channel width of the mirror MOS transistor M2; if the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 are equal, and the channel width of the main MOS transistor M1 and the channel width of the mirror MOS transistor M2 are also the same, then the mirror ratio depends on the ratio of the channel lengths of the main MOS transistor M1 and the mirror MOS transistor M2.

[0057] In this embodiment, the gate voltage adjustment circuit 1 is used to output the adjustable gate voltage VG1 of the main MOS transistor M1 and the adjustable gate voltage VG2 of the mirror MOS transistor M2. The gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 can be the same or different. When the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 are different, since the source terminal of the main MOS transistor M1 and the source electrode of the mirror MOS transistor M2 are connected together, changing the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 changes the gate-source voltage of the main MOS transistor M1 and the gate-source voltage of the mirror MOS transistor M2, thereby changing the mirror ratio. By changing the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 output by the gate voltage adjustment circuit 1 to adjust the mirror ratio, only one mirror MOS transistor M2 is required to complete the adjustment of the mirror ratio in a wide range, thereby reducing the layout area, and the trimming accuracy is not limited by the minimum channel width and the minimum channel length of the MOS transistor.

[0058] It can be seen that in this application, the gate voltage adjustment circuit 1 changes the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 to adjust the mirror ratio, so as to realize high-precision and wide-range trimming of the mirror ratio with one mirror MOS transistor M2, and the economy is good.

[0059] Based on the above embodiment:

[0060] Specifically, please refer to Figure 5 as shown in Figure 5 which is a circuit diagram of a gate voltage adjustment circuit disclosed by the present invention.

[0061] As an optional embodiment, the gate voltage adjustment circuit 1 includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor R2;

[0062] The negative electrodes of the first current source and the third current source are both connected to the power supply voltage VDD. The common terminal of the positive electrode of the first current source, the negative electrode of the second current source, and the first end of the second resistor R2 serves as the first end of the gate voltage adjustment circuit 1 and is connected to the gate of the main MOS transistor M1;

[0063] The common terminal of the positive electrode of the third current source, the negative electrode of the fourth current source, and the second end of the second resistor R2 serves as the second end of the gate voltage adjustment circuit 1 and is connected to the gate of the mirror MOS transistor M2;

[0064] The positive electrodes of the second current source and the fourth current source are both grounded.

[0065] In this embodiment, when the gate voltage adjustment circuit 1 is the first current source, the second current source, the third current source, the fourth current source, and the second resistor R2, by changing the current I1 of the first current source and the current I4 of the fourth current source, or changing the current I2 of the second current source and the current I3 of the third current source, and / or the magnitude of the second resistor R2, the voltage polarity and magnitude of the second resistor R2 can be changed, thereby changing the gate voltage VG2 of the mirror MOS transistor M2, achieving the adjustment of the mirror ratio with one mirror MOS transistor M2, and having good economy. The relationship between the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 is as follows:

[0066] ;

[0067] wherein, is the current of the second resistor R2.

[0068] Specifically, please refer to Figure 5 as shown Figure 5 is a diagram of a gate voltage adjustment circuit 1 disclosed in the present invention. Among them, the current flowing from the first end of the second resistor R2 to the second end of the second resistor R2 is in the reverse direction. When the current I1 of the first current source and the current I4 of the fourth current source are of the same magnitude, and the currents I2 of the second current source and I3 of the third current source are both 0, if the currents I1 of the first current source and I4 of the fourth current source are increased, the current at this time flows from the first current source through the second resistor R2 and then to the fourth current source, generating a reverse voltage difference across the second resistor R2, then the value of the gate voltage VG2 of the mirror MOS transistor M2 decreases; when the currents I2 of the second current source and I3 of the third current source are of the same magnitude, and the currents I1 of the first current source and I4 of the fourth current source are both 0, if the currents I2 of the second current source and I3 of the third current source are increased, the current at this time flows from the third current source through the second resistor R2 and then to the second current source, generating a forward voltage difference across the second resistor R2, then the value of the gate voltage VG2 of the mirror MOS transistor M2 increases; if the resistance value of the second resistor R2 is increased, then the value of the gate voltage VG2 of the mirror MOS transistor M2 decreases; if the resistance value of the second resistor R2 is decreased, then the value of the gate voltage VG2 of the mirror MOS transistor M2 increases.

[0069] It can be seen that by changing the current I1 of the first current source and the current I4 of the fourth current source, or changing the current I2 of the second current source and the current I3 of the third current source, and / or the magnitude of the second resistor R2 to change the gate voltage VG2 of the mirror MOS transistor M2 to adjust the mirror ratio, it is more convenient than changing the size of the mirror MOS transistor M2, greatly improving the adjustment range and accuracy, while saving the layout area and having good economy.

[0070] As an alternative embodiment, the second resistor R2 is a resistor with adjustable resistance value, and / or, the first current source, the second current source, the third current source, and the fourth current source are all adjustable current sources.

[0071] Specifically, from the relational expression of the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2, it can be seen that by changing the resistance value of the second resistor R2 and / or the current flowing through the second resistor R2, the relationship between the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 can be adjusted, and thus the mirror ratio can be adjusted. Based on this, in this embodiment, the second resistor R2 is a resistor with adjustable resistance value, and / or, the first current source, the second current source, the third current source, and the fourth current source are all current sources with adjustable output current, so as to realize the adjustment of the mirror ratio.

[0072] As an alternative embodiment, the resistor with adjustable resistance value includes N parallel resistor branches;

[0073] Each resistor branch includes a series-connected sub-resistor and a switch.

[0074] In this embodiment, the resistance value of the resistor with adjustable resistance value is adjusted by controlling the closing and opening of the switch in the resistor branch. Specifically, the number of parallel sub-resistors is determined by the number of closed switches in the resistor branch, and thus the resistance value of the resistor with adjustable resistance value is adjusted. Among them, the resistance values of the sub-resistors in each resistor branch can be the same or different, and the switch can be but is not limited to a MOS transistor.

[0075] As an alternative embodiment, the adjustable current source includes N parallel current source branches;

[0076] Each current source branch includes a series-connected sub-current source and a switch.

[0077] In this embodiment, the current output by the current source branch is adjusted by controlling the closing and opening of the switch in the current source branch. Specifically, the number of parallel sub-current sources is determined by the number of closed switches in the current source branch, and thus the current output by the current source branch is adjusted. Among them, the currents output by the sub-current sources in each current source branch can be the same or different, and the switch can be but is not limited to a MOS transistor.

[0078] As an alternative embodiment, both the main MOS transistor and the mirror MOS transistor are NMOS transistors.

[0079] In this application, both the main MOS transistor and the mirror MOS transistor can be NMOS transistors or PMOS transistors, so as to realize the adjustment of the mirror ratio of NMOS transistors or PMOS transistors, and the applicable range is wide.

[0080] As an alternative embodiment, it further includes a temperature sensor. The temperature sensor is disposed around the mirror MOS transistor M2 and is used to collect the ambient temperature of the mirror MOS transistor M2, so that the processor can correct the current of the main MOS transistor M1 obtained based on the voltage across the first resistor R1 through the ambient temperature.

[0081] Considering that the current in the saturation region of the MOS transistor is related to the threshold voltage of the MOS transistor, it decreases with the increase of the ambient temperature (about ), resulting in a change in the current in the saturation region of the MOS transistor. If not compensated, the mirror ratio will drift with temperature. For example, the error can reach in the range of -40°C to 125°C. Therefore, in this embodiment, a temperature sensor is provided to monitor the ambient temperature of the mirror MOS transistor M2 in real time, and the controller is used to correct the current of the main MOS transistor M1 obtained based on the voltage across the first resistor R1 through the ambient temperature, ensuring the consistency and reliability of the MOS transistor current sampling in a wide temperature range.

[0082] In addition, the resistance value of the first resistor R1 may also change with the ambient temperature (such as a metal film resistor ), further introducing errors. Therefore, the correction also needs to consider the error impact caused by the resistance value of the first resistor R1 at different ambient temperatures.

[0083] It can be seen that in this embodiment, temperature compensation is performed based on the temperature collected by the temperature sensor using the controller, ensuring the consistency and reliability of the MOS transistor current sampling in a wide temperature range.

[0084] As an alternative embodiment, it further includes an amplifier, an AD converter, and a processor;

[0085] The input end of the amplifier is connected to the first resistor R1 and is used to amplify the voltage across the first resistor R1 to obtain an amplified voltage;

[0086] The input end of the AD converter is connected to the output end of the amplifier, and the output end of the AD converter is connected to the processor. The AD converter is used to convert the amplified voltage from an analog quantity to a digital quantity;

[0087] The processor is used to process the amplified digital voltage to obtain the current of the main MOS transistor M1.

[0088] Considering that the voltage across the first resistor R1 is usually small (e.g., in the millivolt range), direct measurement is vulnerable to noise interference and difficult to be effectively quantified by the AD converter. Therefore, in this embodiment, an amplifier such as an instrumentation amplifier is provided, which can amplify the tiny voltage to the optimal input range of the AD converter (e.g., 0 to 3.3V), improve the SNR (Signal to Interference plus Noise Ratio), and ensure that the voltage across the first resistor R1 can be detected by the AD converter with high precision. Since the analog voltage signal cannot be directly processed by the digital processor, the AD converter is needed to convert the amplified voltage into a digital quantity (e.g., 12-bit resolution), which is convenient for the processor to perform mathematical operations and logical judgments, and at the same time avoid the attenuation and interference problems of long-distance transmission of analog signals. Finally, the processor can accurately calculate the current of the main MOS transistor M1 based on the digital quantity voltage output by the AD converter, combined with calibration data (such as temperature compensation, non-linear correction) and mirror ratio.

[0089] It can be seen that in this embodiment, the amplifier is used to amplify the voltage across the first resistor R1, ensure that the voltage across the first resistor R1 can be detected by the AD converter with high precision, convert the amplified voltage into a digital quantity for the processor to process, so as to obtain the current of the main MOS transistor M1, and improve the accuracy of the current sampling of the main MOS transistor M1.

[0090] As an alternative embodiment, it further includes a filtering module. The first end of the filtering module is connected to the output end of the amplifier, and the second end of the filtering module is connected to the input end of the AD converter.

[0091] Considering that the output of the amplifier may contain high-frequency noise such as environmental electromagnetic interference. If these high-frequency noises are not filtered out, they will be aliased into the low-frequency signal after being sampled by the AD converter, resulting in digital quantity voltage errors, and the useless high-frequency noises will occupy the quantization bits of the AD converter, reducing the resolution of the effective voltage signal. Therefore, in this embodiment, a filtering module is provided to filter the amplified voltage, so that the AD converter can more accurately quantify the voltage signal.

[0092] It can be seen that in this embodiment, the filtering module is used to suppress high-frequency noise and high frequency, ensure the accuracy of the input data of the AD converter, and make the calculation of the current of the main MOS transistor M1 more accurate.

[0093] Please refer to Figure 6 , Figure 6 , which is the flowchart of a method for sampling the current of a MOS transistor provided by the present invention. This method is applied to the MOS transistor current sampling circuit as described above, and this method may include:

[0094] S11: Determine the target mirror ratio of the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 in the MOS transistor current sampling circuit;

[0095] S12: Adjust the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 output by the gate voltage adjustment circuit 1 in the MOS transistor current sampling circuit so that the mirror ratio is the target mirror ratio;

[0096] S13: Determine the current of the mirror MOS transistor M2 based on the voltage across the first resistor R1 in the MOS transistor current sampling circuit;

[0097] S14: Determine the current of the main MOS transistor M1 based on the target mirror ratio and the current of the mirror MOS transistor M2.

[0098] Considering the process deviation of the MOS transistor, there is an error between the mirror ratio and the ratio of the channel length and channel width of the main MOS transistor M1 and the ratio of the channel length and channel width of the mirror MOS transistor M2. For this reason, in this embodiment, first determine the target mirror ratio of the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 in the MOS transistor current sampling circuit; then adjust the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 output by the gate voltage adjustment circuit 1 in the MOS transistor current sampling circuit so that the mirror ratio is the target mirror ratio, reducing the influence of the process deviation of the MOS transistor on the mirror ratio; take the ratio of the voltage across the first resistor R1 in the MOS transistor current sampling circuit to the resistance value of the first resistor R1 as the current of the mirror MOS transistor M2, and finally calculate the current of the main MOS transistor M1 according to the current of the mirror MOS transistor M2 and the target mirror ratio.

[0099] It can be seen that in this application, the gate voltage adjustment circuit 1 changes the gate voltage VG1 of the main MOS transistor M1 and the gate voltage VG2 of the mirror MOS transistor M2 to adjust the mirror ratio, realizing high-precision and wide-range trimming of the mirror ratio with a single mirror MOS transistor M2, and having good economy.

[0100] As an optional embodiment, the gate voltage adjustment circuit includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor;

[0101] The negative electrodes of the first current source and the third current source are both connected to the power supply voltage, and the common terminal of the positive electrode of the first current source, the negative electrode of the second current source, and the first end of the second resistor is used as the first end of the gate voltage adjustment circuit and is connected to the gate of the main MOS transistor;

[0102] The positive electrode of the third current source, the negative electrode of the fourth current source, and the second terminal of the second resistor are connected to the gate of the mirror MOS transistor as the second terminal of the gate voltage adjustment circuit;

[0103] The positive electrodes of the second current source and the fourth current source are both grounded;

[0104] Adjust the gate voltages of the main MOS transistor and the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit, including:

[0105] Adjust the currents of the first current source, the second current source, the third current source, and the fourth current source, and / or the resistance value of the second resistor to adjust the gate voltages of the main MOS transistor and the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit.

[0106] Specifically, please refer to Figure 5 , the current flowing from the first terminal of the second resistor R2 to the second terminal of the second resistor R2 is in the reverse direction. When the current I1 of the first current source is the same as the current I4 of the fourth current source, and the currents I2 of the second current source and I3 of the third current source are both 0, if the currents I1 of the first current source and I4 of the fourth current source are increased, the current at this time flows from the first current source through the second resistor R2 and then to the fourth current source, generating a reverse voltage difference across the second resistor R2, then the value of the gate voltage VG2 of the mirror MOS transistor M2 decreases; when the currents I2 of the second current source and I3 of the third current source are the same, and the currents I1 of the first current source and I4 of the fourth current source are both 0, if the currents I2 of the second current source and I3 of the third current source are increased, the current at this time flows from the third current source through the second resistor R2 and then to the second current source, generating a forward voltage difference across the second resistor R2, then the value of the gate voltage VG2 of the mirror MOS transistor M2 increases; if the resistance value of the second resistor R2 is increased, then the value of the gate voltage VG2 of the mirror MOS transistor M2 decreases; if the resistance value of the second resistor R2 is decreased, then the value of the gate voltage VG2 of the mirror MOS transistor M2 increases.

[0107] It can be seen that by changing the current I1 of the first current source and the current I4 of the fourth current source, or changing the current I2 of the second current source and the current I3 of the third current source, and / or the magnitude of the second resistor R2 to change the gate voltage VG2 of the mirror MOS transistor M2 to adjust the mirror ratio, it is more convenient than changing the size of the mirror MOS transistor M2, which greatly improves the adjustment range and accuracy, saves the layout area at the same time, and has good economy.

[0108] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0109] It should also be noted that in this specification, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0110] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A MOS transistor current sampling circuit, characterized in that It includes a gate voltage adjustment circuit, a mirror MOS transistor, and a first resistor; The first end of the gate voltage adjustment circuit is connected to the gate of the main MOS transistor, and the second end of the gate voltage adjustment circuit is connected to the gate of the mirror MOS transistor. The gate voltage adjustment circuit is used to output an adjustable gate voltage of the main MOS transistor and an adjustable gate voltage of the mirror MOS transistor; The source of the mirror MOS transistor and the source of the main MOS transistor are both connected to the source voltage, and the drain of the mirror MOS transistor is connected to the first end of the first resistor; The second end of the first resistor and the drain of the main MOS transistor are both connected to the drain voltage.

2. The MOS transistor current sampling circuit according to claim 1, wherein The gate voltage adjustment circuit includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor; The negative poles of the first current source and the third current source are both connected to the power supply voltage. The common terminal of the positive pole of the first current source, the negative pole of the second current source, and the first end of the second resistor serves as the first end of the gate voltage adjustment circuit and is connected to the gate of the main MOS transistor; The common terminal of the positive pole of the third current source, the negative pole of the fourth current source, and the second end of the second resistor serves as the second end of the gate voltage adjustment circuit and is connected to the gate of the mirror MOS transistor; The positive poles of the second current source and the fourth current source are both grounded.

3. The MOS transistor current sampling circuit according to claim 2, characterized in that The second resistor is a resistor with adjustable resistance value, and / or, the first current source, the second current source, the third current source, and the fourth current source are all adjustable current sources.

4. The MOS transistor current sampling circuit according to claim 3, wherein The resistor with adjustable resistance value includes N parallel resistor branches; Each of the resistor branches includes a series-connected sub-resistor and a switch.

5. The MOS transistor current sampling circuit according to claim 3, wherein, The adjustable current source includes N parallel current source branches; Each of the current source branches includes a series-connected sub-current source and a switch.

6. The MOS transistor current sampling circuit according to claim 1, characterized in that It further includes an amplifier, an AD converter, and a processor; The input end of the amplifier is connected to the first resistor and is used to amplify the voltage across the first resistor to obtain an amplified voltage; The input end of the AD converter is connected to the output end of the amplifier, and the output end of the AD converter is connected to the processor. The AD converter is used to convert the amplified voltage from an analog quantity to a digital quantity; The processor is used to process the amplified digital voltage to obtain the current of the main MOS transistor.

7. The MOS transistor current sampling circuit according to claim 6, wherein It further includes a filtering module. The first end of the filtering module is connected to the output end of the amplifier, and the second end of the filtering module is connected to the input end of the AD converter and is used to filter the amplified voltage.

8. The MOS transistor current sampling circuit according to any one of claims 1 to 7, characterized in that, It further includes a temperature sensor. The temperature sensor is arranged around the mirror MOS transistor and is used to collect the ambient temperature of the mirror MOS transistor so that the processor can correct the current of the main MOS transistor obtained based on the voltage across the first resistor through the ambient temperature.

9. A method for sampling MOS transistor current, characterized in that, Applied to the MOS transistor current sampling circuit according to any one of claims 1 to 8, the method includes: Determining the target mirror ratio of the gate voltage of the main MOS transistor and the gate voltage of the mirror MOS transistor in the MOS transistor current sampling circuit; Adjust the gate voltages of the main MOS transistor and the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit so that the mirror ratio is the target mirror ratio; Determine the current of the mirror MOS transistor based on the voltage across the first resistor in the MOS transistor current sampling circuit; Determine the current of the main MOS transistor based on the target mirror ratio and the current of the mirror MOS transistor.

10. The MOS transistor current sampling method according to claim 9, wherein The gate voltage adjustment circuit includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor; The negative poles of the first current source and the third current source are both connected to the power supply voltage, and the common terminal of the positive pole of the first current source, the negative pole of the second current source, and the first end of the second resistor is used as the first end of the gate voltage adjustment circuit and is connected to the gate of the main MOS transistor; The common terminal of the positive pole of the third current source, the negative pole of the fourth current source, and the second end of the second resistor is used as the second end of the gate voltage adjustment circuit and is connected to the gate of the mirror MOS transistor; The positive poles of the second current source and the fourth current source are both grounded; Adjusting the gate voltages of the main MOS transistor and the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit includes: Adjust the currents of the first current source, the second current source, the third current source, and the fourth current source, and / or the resistance value of the second resistor, to adjust the gate voltages of the main MOS transistor and the mirror MOS transistor output by the gate voltage adjustment circuit in the MOS transistor current sampling circuit.

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