Method for rapidly extracting trap parameters in GaN HEMT device at room temperature

Abstract

The invention provides a method for rapidly extracting trap parameters in a GaN HEMT (High Electron Mobility Transistor) device at room temperature. The method comprises the following steps: applying source-drain voltage, and observing channel current; applying a substrate bias voltage, and observing a substrate current; scanning and changing the bias voltage of the substrate, and evaluating trap types based on a channel current change trend; adjusting the scanning rate of the substrate bias to determine the trap type; applying a plurality of constant substrate bias voltages, observing the change trend of channel current along with time, calculating a time constant, and calculating a plurality of trap activation energies; the substrate current under different substrate bias voltages is observed, a current transmission mechanism is fitted, and the relation between multiple trap activation energy and an electric field is extracted; and calculating a zero field trap level. The method for rapidly and accurately extracting the trap parameters based on the room temperature is provided for the first time, the trap type, the trap time constant and the trap energy level information in the null field can be obtained at the room temperature, temperature change testing is not needed, the trap energy level in the null field can be accurately obtained, and data offset is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of reliability testing of semiconductor electronic devices, and particularly to a method for rapidly extracting trap parameters in GaN HEMT devices at room temperature. Background Art

[0002] GaN-based HEMT devices have the advantages of high voltage and high current, high switching frequency, low power loss, and high operating temperature, and can provide higher energy efficiency and higher power density in power electronics applications, and have more potential applications in fields such as motor control, power distribution systems, electric vehicles, and avionics. However, its industrialization process is still restricted by the breakthrough of several key scientific issues, especially challenges such as premature breakdown and reliability degradation of devices need to be solved urgently. During the device structure design, epitaxial growth, and preparation process, certain defect states will be deliberately or inadvertently introduced, forming deep-level traps in the semiconductor bandgap. Traps modulate the carrier transport behavior during the switching transient process, resulting in the degradation of the electrical performance of the device.

[0003] At present, the commonly used electrical testing method for characterizing traps is deep level transient spectroscopy (DLTS). This method can effectively obtain information such as the energy level parameters of GaN material traps, but there are still certain limitations in actual device applications. This method relies on the measurement of capacitance signals under variable temperature conditions, and this process requires multiple scans at different temperatures to cover a wide energy level range, resulting in a long test period. On the other hand, this method is based on an electric field-dependent energy level extraction mechanism, resulting in the obtained trap energy levels deviating from the true values under zero field, which restricts the physical accuracy of the test results. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a method for rapidly extracting trap parameters in GaN HEMT devices at room temperature.

[0005] To achieve the foregoing invention purpose, the technical solutions adopted by the present invention include:

[0006] The present invention provides a method for rapidly extracting trap parameters in GaN HEMT devices at room temperature, which includes:

[0007] Providing a GaN HEMT device, the GaN HEMT device includes a conductive substrate, a device structure layer, and a source electrode and a drain electrode, and the connection direction from the conductive substrate to the device structure layer is perpendicular to the connection direction of the source electrode and the drain electrode;

[0008] Applying a source-drain voltage between the source electrode and the drain electrode to make the GaN HEMT device operate in the linear region, and observing the channel current between the source electrode and the drain electrode;

[0009] Using the conductive substrate as an electrode, apply a substrate bias in the direction from the device structure layer to the conductive substrate, and observe the substrate current passing through the conductive substrate;

[0010] Vary the substrate bias in a scanning manner, and evaluate the trap type based on the variation trend of the channel current with the substrate bias;

[0011] Adjust the scanning rate of the substrate bias, and determine the trap type based on the variation trend of the channel current with the substrate bias at different scanning rates;

[0012] Apply multiple constant substrate biases, observe the variation trend of the channel current with time under different substrate biases, calculate the time constants under different substrate biases, and calculate the trap activation energy under different substrate biases according to the time constants;

[0013] Observe the stable substrate current under different substrate biases, and calculate the current transport mechanism;

[0014] According to the corresponding current transport mechanism formula, fit the relationship between multiple trap activation energies and the electric field formed by the substrate bias, and deduce the zero-field trap energy level when the substrate bias is 0.

[0015] Based on the above technical solutions, compared with the prior art, the beneficial effects of the present invention at least include:

[0016] The present invention firstly proposes a method for quickly and accurately extracting trap parameters of GaN HEMT devices at room temperature. This method can obtain trap type, trap time constant, and trap energy level information under zero field at room temperature (for example, in the range of 15 - 35 °C). Compared with the prior art, it does not require variable temperature testing, significantly improves the testing efficiency, and reduces the testing cost; in addition, it can accurately obtain the trap energy level under zero field and avoid data deviation.

[0017] The above description is only an overview of the technical solutions of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement it according to the content of the specification, the following takes a preferred embodiment of the present invention and combines it with detailed drawings for illustration as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of the test structure of a GaN HEMT device provided by a typical embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of the substrate bias scanning waveform in the test method of a GaN HEMT device provided by a typical embodiment of the present invention;

[0020] Figure 3It is a schematic waveform diagram of the constant substrate bias in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0021] Figure 4 It is a schematic diagram showing the variation law of the channel current and substrate current with time in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0022] Figure 5 It is a schematic diagram showing the ideal variation law of the channel current with the substrate bias in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0023] Figure 6 It is a measured graph of the actual variation law of the channel current with the substrate bias in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0024] Figure 7 It is a schematic diagram showing the energy band variation in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0025] Figure 8 It is a measured graph of the channel current-time variation law under different substrate biases in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0026] Figure 9 It is a time constant spectrogram of the channel current-time variation law under different substrate biases in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0027] Figure 10 It is a measured graph of the substrate current-time variation law under different substrate biases in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0028] Figure 11 It is a fitting line graph related to the electric field-current density in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0029] Figure 12 It is a schematic diagram showing the energy band tilting state in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0030] Figure 13 It is a linear fitting graph related to the electric field-defect energy level in the test method of the GaN HEMT device provided by a typical embodiment of the present invention;

[0031] Figure 14It is the measured graph of the actual variation law of the channel current with the substrate bias voltage in the test method of the GaN HEMT device provided by another typical embodiment of the present invention;

[0032] Figure 15 It is the measured graph of the variation law of the channel current - time under different substrate bias voltages in the test method of the GaN HEMT device provided by another typical embodiment of the present invention;

[0033] Figure 16 It is the linear fitting graph related to the electric field - defect energy level in the test method of the GaN HEMT device provided by another typical embodiment of the present invention. Detailed implementation manners

[0034] In view of the deficiencies in the prior art, the inventors of this case have proposed the technical solution of the present invention through long - term research and a large number of practices. The following will further explain the technical solution, its implementation process, principles, etc.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0036] Moreover, relational terms such as "first" and "second" are only used to distinguish one component or method step with the same name from another, and do not necessarily require or imply any actual relationship or order between these components or method steps.

[0037] The main object of the present invention is to propose a method for quickly extracting trap parameters of GaN HEMT devices at room temperature by the variation of transient current with voltage and time. This technology can be applied to the measurement of trap parameters of GaN HEMT devices to obtain information such as trap types, trap time constants, and trap energy levels under zero - field. This method is simple, convenient, and non - destructive, and is applicable to the field of reliability analysis of wide - bandgap semiconductor devices.

[0038] Based on the above object and inventive concept, an embodiment of the present invention provides a method for quickly extracting trap parameters in a GaN HEMT device at room temperature, which includes the following steps:

[0039] Provide a GaN HEMT device as Figure 1 shown, the GaN HEMT device includes a conductive substrate, a device structure layer, and a source electrode and a drain electrode. The connection direction from the conductive substrate to the device structure layer is perpendicular to the connection direction of the source electrode and the drain electrode;

[0040] Apply a source-drain voltage between the source and the drain to make the GaN HEMT device operate in the linear region, and observe the channel current between the source and the drain;

[0041] Using the conductive substrate as an electrode, apply a substrate bias voltage in the direction from the device structure layer to the conductive substrate, and observe the substrate current passing through the conductive substrate;

[0042] Vary the substrate bias voltage in a scanning manner, and evaluate the trap type based on the variation trend of the channel current with the substrate bias voltage;

[0043] Adjust the scanning rate of the substrate bias voltage, and determine the trap type based on the variation trend of the channel current with the substrate bias voltage at different scanning rates;

[0044] Apply multiple constant substrate bias voltages, observe the variation trend of the channel current with time under different substrate bias voltages, calculate the time constants under different substrate bias voltages, and calculate the trap activation energies under different substrate bias voltages according to the time constants;

[0045] Observe the stable substrate current under different substrate bias voltages, and calculate the current transport mechanism;

[0046] According to the corresponding current transport mechanism formula, combined with the relationship between multiple trap activation energies and the electric field formed by the substrate bias voltage, deduce the zero-field trap energy level when the substrate bias voltage is 0.

[0047] In the above technical solution, by applying a small voltage between the source and drain electrodes of the source-drain two-terminal test structure of the GaN HEMT, the device is made to operate in the linear region to avoid the self-heating effect. Using the conductive substrate as the back electrode to apply a negative bias voltage forms a vertically downward high electric field from the top metal to the substrate to simulate the off-state drain bias condition in the real application scenario. The drain-source current of the device will show a decreasing or increasing variation trend with the substrate bias voltage and time. This curve change is caused by the ionization of carriers by the buffer layer bulk traps under high electric fields to form fixed charges, which affects the two-dimensional electron gas (2DEG) in the channel. This process is the emission process of traps to carriers. By collecting, fitting, extracting, and analyzing the drain-source transient current during the process of traps releasing carriers, the characteristic parameters of the deep-level bulk traps can be obtained. The preparation process of the test structure required for this test is simple, and testing at room temperature can effectively save time costs and can obtain trap energy level information under zero field.

[0048] As some typical specific application examples of the above technical solution, the specific implementation method of the above technical solution includes the following steps:

[0049] 1. Place the device under test on a room-temperature probe station, apply a small bias voltage to the source and drain terminals of the device, and simultaneously apply a scanned substrate bias voltage at a constant speed to the substrate terminal to excite buffer layer traps. Monitor the variation of the drain-source current of the device under test with the scanned substrate voltage. The source-drain terminal voltage should be controlled within the range where self-heating effects occur (the source-drain voltage when the device operates in the linear region) to avoid measurement errors caused by changes in the device temperature. Plot the I d -V sub curve, and evaluate the trap type (donor or acceptor type trap) based on the rising or falling trend of the channel current with the substrate bias voltage.

[0050] 2. Place the device under test on a room-temperature probe station, apply a small bias voltage to the source and drain terminals of the device, and simultaneously apply a constant substrate bias voltage to the substrate terminal. Monitor the variation curve of the source-drain current of the device under test with time, as well as the variation curve of the substrate current I sub with time; the source-drain terminal voltage should be controlled within the range where self-heating effects occur (the source-drain voltage when the device operates in the linear region) to avoid measurement errors caused by changes in the device temperature. Plot the I d -t curve and the I sub -t curve.

[0051] 3. Repeat the measurement process of step 1 at different scanning frequencies. Based on the variation of the drain-source current I d with the substrate bias voltage V sub at different scanning frequencies, further evaluate and verify the trap type affecting carrier transport;

[0052] 4. Repeat the measurement process of step 2 at different substrate bias voltages. Take the derivative or fit the I d -t curve in logarithmic coordinates to obtain the time constant spectrum, perform the extraction process of transient current and trap time constant, and calculate the trap activation energy;

[0053] 5. Fit the substrate leakage current I sub values at different substrate bias voltages to its current transport mechanism. According to the current transport mechanism formula, plot the relationship diagram between the trap activation energy and the electric field formed by the substrate bias voltage, and extract the energy level parameters of the trap under zero field.

[0054] Regarding the specific steps, in some embodiments, the method may specifically include the following process:

[0055] When the slope of the relationship curve of the channel current with the substrate bias voltage is lower than the slope of the relationship curve of the ideal current with the substrate bias voltage, initially determine that the trap type is acceptor type;

[0056] When the slope of the relationship curve of the channel current with the substrate bias voltage is higher than the slope of the relationship curve of the ideal current with the substrate bias voltage, initially determine that the trap type is donor type.

[0057] In some embodiments, the ideal current refers to the channel current value when there are no defects in the material. At this time, an ideal capacitor exists between the substrate and the channel, and the ideal current value under the substrate bias can be calculated by the following formula:

[0058] ΔI = ΔV sub CWμV ds / L

[0059] where ΔI is the ideal current value, W is the device width, L is the source-drain spacing, μ is the channel electron mobility, V sub is the substrate bias, C is the capacitance of the buffer layer material in the device, and V ds is the source-drain voltage.

[0060] In some embodiments, the method may specifically further include the following process:

[0061] When, at different scan rates, both the current loss value and the current collapse value increase as the scan rate decreases, determine that the trap type is acceptor type;

[0062] When, at different scan rates, both the current loss value and the current collapse value decrease as the scan rate decreases, determine that the trap type is donor type;

[0063] where the current loss value represents the absolute value of the difference between the channel current and the ideal current under the selected substrate bias, and the current collapse value refers to the absolute value of the difference between the initial channel current at zero voltage and the terminal channel current after scanning back and forth to zero voltage.

[0064] In some embodiments, the time constant is obtained by exponential function fitting or by taking the derivative of the logarithm of time.

[0065] In some embodiments, the exponential function fitting is expressed as:

[0066]

[0067] where I d (·) represents the channel current, t represents time, I0 represents the initial current value, ΔI represents the current change value caused by the ionization of buffer layer traps, τ represents the time constant, and β represents the current decay exponent.

[0068] In some embodiments, the calculation method of the trap activation energy is expressed as:

[0069]

[0070] where h represents Planck's constant, k represents Boltzmann's constant, and mh represents the effective mass of the carriers corresponding to the defect, σ h represents the capture cross-section of the carriers corresponding to the defect, T represents the Kelvin temperature, ΔE trap represents the trap activation energy.

[0071] In some embodiments, the relationship between the trap activation energy and the electric field strength formed by the substrate bias is determined by the current transport mechanism and is expressed as:

[0072]

[0073] where q represents the electron charge, represents the trap energy level at zero field, ε0 represents the vacuum permittivity, ε s represents the relative permittivity of the device material, and E represents the electric field strength formed by the substrate bias.

[0074] In some embodiments, the method may specifically further include the following process:

[0075] For perform a linear fit, and obtain the intercept when E = 0 in the linear fit curve or formula as the zero-field trap activation energy.

[0076] In some embodiments, the scanning range of the substrate bias is -1000 to 0 volts.

[0077] In some embodiments, the scanning rate of the substrate bias is 0.01 - 100 V / s.

[0078] In some embodiments, the range of the source-drain voltage is 0.01 - 1 V.

[0079] The technical solution of the present invention will be further described in detail below through several embodiments in combination with the accompanying drawings. However, the selected embodiments are only used to illustrate the present invention and do not limit the scope of the present invention.

[0080] Embodiment 1

[0081] This embodiment is a method for rapidly extracting trap parameters in a GaN HEMT device at room temperature. The structure of the device to be measured is as Figure 1 shown. A transmission line (TLM) test structure is used, which is a source-drain two-terminal test structure. A small voltage is applied between the source and drain electrodes to make the device operate in the linear region to avoid surface states and self-heating effects. The conductive silicon substrate is used as the back electrode, and a negative ramp scanning bias (as Figure 2 shown) and a constant negative substrate bias (as Figure 3 shown) are applied, expecting to obtain I d -V sub , I d -t and Isub -t curve, such as Figure 4 shown, and further analyze the obtained curve to obtain relevant information on the trap characteristics, especially the variation rules of the substrate bias voltage and the channel current. Theoretically, it should be as Figure 5 shown.

[0082] In a specific implementation, an AlGaN / GaN HEMT is selected as the device under test. Using metalorganic chemical vapor deposition technology, Al 0.2 Ga 0.8 N / A1N / GaN / GaN HEMT structure is grown on a p-Si substrate. The carbon doping concentration of the GaN buffer layer is 2×10 19 cm- 3 . The source-drain ohmic contact is formed by stacking Ti / Al / Ni / Au metals and annealed in an N2 atmosphere at 890 °C for 30 s.

[0083] Place the sample under test on a room-temperature probe station to ensure good contact with the probe station. Apply a voltage of V ds = 0.1 V to the source-drain electrodes of the source-drain structure in the sample, and apply a voltage that scans from 0 V to -200 V and then back to 0 V to the substrate end. The scanning frequency is 20 V / s, and the measured I d -V sub curve is as Figure 6 shown. The measured current I d is smaller than the ideal current value, indicating that acceptor-type traps mainly participate in the carrier transport in the buffer layer. The traps emit holes to generate negative charges, resulting in a current hysteresis effect. Considering from the energy band perspective, as Figure 7 shown, due to the generation of negative charges, the interface energy band at the channel is increased, and there is a current difference after the voltage scanning ends.

[0084] Repeat the test on the sample under test at scanning rates of 5 V / s and 1 V / s respectively. The measurement results are as shown by the different lines in Figure 6 . The current loss under negative voltage and the current collapse under zero voltage both increase with the decrease of the scanning rate. This further verifies that acceptor-type traps mainly participate in the carrier transport process in the buffer layer.

[0085] Place the sample under test on a room-temperature probe station to ensure good contact with the probe station. Apply a voltage of V ds = 0.1 V to the source-drain electrodes of the source-drain structure in the sample, and apply a constant voltage of V sub = -50 V to the substrate end. Collect the curves of the drain current and the substrate current changing with time; change the substrate bias voltage in steps of -25 V and repeat the measurement. The measurement results and the corresponding analysis are as Figures 8 - 11 shown.

[0086] Figure 8Shows the current transient spectra I at different constant back-gate substrate biases d -t curves. After collecting the transient drain current response, the I d -t curves are further processed to obtain the time constant spectra, which can be obtained by either fitting with an exponential function or taking the derivative with respect to logarithmic time (d(I d )) / d[log(t)]). The exponential fitting function is shown in Equation (1),

[0087]

[0088] where I0 is the initial current value, ΔI is the current change value caused by the ionization of buffer layer traps, τ is the trap emission time constant, and β is the current decay exponent. The fitting and derivative results are as Figure 9 shown.

[0089] Using the extracted time constant τ, the activation energy (ΔE trap ) for trap emission of holes at different substrate biases is calculated according to the Arrhenius formula. The formula (2) is as follows,

[0090]

[0091] where T is the room temperature of 298K, σ h is the hole capture cross section, taken as 1×10 -16 cm -2 according to the literature, and m h is the effective mass of holes in GaN (0.8m0).

[0092] The monitored substrate current I sub versus time curve is as Figure 10 shown. The current value when I sub tends to be stable with time is taken as the vertical leakage current value. Figure 11 Shows the relationship between current density and electric field. When the electric field strength exceeds 0.8 MV / cm, ln(J / E)-√E shows a linear relationship. This indicates that at high electric fields, the Poole-Frenkel effect dominates and aids carrier transport. From the Poole-Frenkel conduction formula, the definition of the trap activation energy is given by the following formula (3)

[0093]

[0094] The trap activation energy essentially changes with the electric field. Under the action of an applied electric field, the energy band tilts, as Figure 12 shown. Therefore, the activation energy for trap emission of holes is smaller than that without an applied electric field. As the electric field further increases, the energy required to emit holes becomes lower and lower. Based on the data measured at room temperature, the activation energy is plotted against the square root of the electric field (ΔE trap-√E), as shown in Figure 13 . It can be seen from formula (3) that for the carbon-doped GaN buffer layer, the acceptor-type trap energy level depth under zero electric field is extracted as Ev + 0.9 eV.

[0095] Example 2

[0096] Select AlGaN / GaN HEMT as the device under test. Use metalorganic chemical vapor deposition technology to grow an 80-period AlN / GaN superlattice buffer layer with a thickness of 1.84 μm, a GaN buffer layer with a carbon doping concentration of 5×10 18 cm -3 , a 150-nm GaN channel layer, a 1-nm AlN spacer layer, and a 20-nm Al 0.2 Ga 0.8 N barrier layer HEMT structure. Source and drain ohmic contacts are formed by stacking Ti / Al / Ni / Au metals and annealed in N2 atmosphere at 890 °C for 30 s.

[0097] Place the sample under test on a room-temperature probe station to ensure good contact with the probe station. Apply a voltage of V ds = 0.1 V to the source and drain electrodes of the source-drain structure in the sample, and apply a voltage that scans from 0 V to -200 V and then back to 0 V to the substrate end. The scanning rates are 25 V / s and 7 V / s respectively, and the measured I d -V sub curve is as shown in Figure 14 . It can be seen from the test curve that as the electric field increases, I d first decreases rapidly and then turns into a slow decline, indicating that both acceptor-type traps and donor traps in the buffer layer participate in carrier transport. Acceptor traps emit holes to generate negative charges, resulting in current hysteresis; donor traps emit electrons to generate positive charges, offsetting part of the current hysteresis caused by negative charges. Therefore, both current loss and current collapse are alleviated. The current loss under negative voltage and the current collapse under zero voltage both decrease with the decrease of the scanning rate. This further verifies that both acceptor-type traps and donor-type traps in the buffer layer participate in the carrier transport process.

[0098] Place the sample under test on a room-temperature probe station to ensure good contact with the probe station. Apply a voltage of V ds = 0.1 V to the source and drain electrodes of the source-drain structure in the sample, and apply different constant bias voltages to the substrate end. Collect the curves of the drain current and substrate current changing with time, as shown in Figure 15 . The I d -t curves all show a trend of the current first decreasing and then increasing, and the two segments respectively correspond to the ionization processes of acceptor traps and donor traps. For the measured I d-t curves are segmented and fitted to extract the time constant. The activation energy for trap-emitted holes is calculated according to formula (2), and the trap energy level at zero electric field is extracted according to formula (3). The acceptor-type trap energy level depth is obtained as Ev + 0.83 eV, and the donor energy level depth is E c -0.71 eV, as Figure 16 shown.

[0099] Based on the above embodiments, it can be clearly seen that the embodiments of the present invention first propose a method for quickly and accurately extracting trap parameters of GaN HEMT devices at room temperature. This method can obtain trap type, trap time constant, and trap energy level information at zero field at room temperature (for example, in the range of 15 - 35 °C). Compared with the prior art, it does not require variable-temperature testing, significantly improves the testing efficiency, and reduces the testing cost; in addition, it can accurately obtain the trap energy level at zero field and avoid data deviation.

[0100] It should be understood that the above embodiments are only used to illustrate the technical concept and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for rapidly extracting trap parameters in a GaN HEMT device at room temperature, characterized in that, Including: Providing a GaN HEMT device, the GaN HEMT device includes a conductive substrate, a device structure layer, and a source electrode and a drain electrode, and the connection direction from the conductive substrate to the device structure layer is perpendicular to the connection direction of the source electrode and the drain electrode; Applying a source-drain voltage between the source electrode and the drain electrode to make the GaN HEMT device operate in the linear region, and observing the channel current between the source electrode and the drain electrode; Using the conductive substrate as an electrode, applying a substrate bias voltage in the direction from the device structure layer to the conductive substrate, and observing the substrate current passing through the conductive substrate; Making the substrate bias voltage scan and change, and evaluating the trap type based on the change trend of the channel current with the substrate bias voltage; Adjusting the scan rate of the substrate bias voltage, and determining the trap type based on the change trend of the channel current with the substrate bias voltage at different scan rates; Applying a variety of constant substrate bias voltages, observing the change trend of the channel current with time at different substrate bias voltages, calculating the time constant at different substrate bias voltages, and calculating the trap activation energy at different substrate bias voltages according to the time constant; Observing the stable substrate current at different substrate bias voltages, and calculating the current transport mechanism; According to the corresponding current transport mechanism formula, combining the relationship between multiple trap activation energies and the electric field formed by the substrate bias voltage, estimating the zero-field trap energy level when the substrate bias voltage is 0.

2. The method according to claim 1, characterized in that, Specifically including: When the slope of the relationship curve of the channel current with the substrate bias voltage is lower than the slope of the relationship curve of the ideal current with the substrate bias voltage, initially determining that the trap type is acceptor type; When the slope of the relationship curve of the channel current with the substrate bias voltage is higher than the slope of the relationship curve of the ideal current with the substrate bias voltage, initially determining that the trap type is donor type; Wherein, the ideal current refers to the channel current value when there are no defects in the device structure layer. At this time, the substrate and the channel are an ideal capacitor, and the calculation method of the ideal current value under the substrate bias voltage is expressed as: ΔI = ΔV sub CW μV ds / L where ΔI is the ideal current value, W is the width of the device structure layer, L is the distance between the source and the drain, μ is the channel electron mobility, V sub is the substrate bias voltage, C is the capacitance of the buffer layer material in the device structure layer, V ds is the source-drain voltage.

3. The method according to claim 2, wherein Specifically further including: When, at different scan rates, both the current loss value and the current collapse value increase with the decrease of the scan rate, determining that the trap type is acceptor type; When, at different scan rates, both the current loss value and the current collapse value decrease with the decrease of the scan rate, determining that the trap type is donor type; Wherein, the current loss value represents the absolute value of the difference between the channel current and the ideal current under the selected substrate bias voltage, and the current collapse value is the absolute value of the difference between the initial channel current at zero voltage and the terminal channel current when scanning back and forth to zero voltage.

4. The method according to claim 1, characterized in that, The time constant is obtained by exponential function fitting or by taking the derivative of the logarithm of time.

5. The method according to claim 5, wherein The exponential function fitting method is expressed as: Among them, I d (·) represents the channel current, t represents time, I0 represents the initial current value, ΔI represents the current change value caused by the ionization of buffer layer traps, τ represents the time constant, and β represents the current decay exponent.

6. The method according to claim 5 or 6, characterized in that, The calculation method of the trap activation energy is expressed as: where h represents Planck's constant, k represents Boltzmann's constant, m h represents the effective mass of the carrier corresponding to the defect, σ h represents the capture cross section of the carrier corresponding to the defect, T represents the Kelvin temperature, and ΔE trap represents the trap activation energy.

7. The method according to claim 1, characterized in that, The relationship between the trap activation energy and the electric field strength formed by the substrate bias voltage determined by the current transport mechanism is expressed as: where q represents the electronic charge, represents the trap energy level under zero field, ε0 represents the vacuum permittivity, and ε s represents the relative permittivity of the device material, and E represents the electric field strength formed by the substrate bias voltage.

8. The method according to claim 8, characterized in that Specifically including: For perform a linear fit and obtain the intercept when E = 0 in the linear fit curve or formula as the zero-field trap activation energy.

9. The method according to claim 1, characterized in that, The scan range of the substrate bias voltage is -1000 to 0 volts.

10. The method according to claim 1, characterized in that, The scan rate of the substrate bias voltage is 0.01 - 100 V / s; And / or, the source-drain voltage ranges from 0.01V to 1V.

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