Testing device compatible with chip for electrostatic discharge test and radio frequency test

Abstract

The invention provides a testing device compatible with a chip for electrostatic discharge testing and radio frequency testing, and the testing device comprises a first testing plate which comprises a chip placement region used for placing a chip to be tested; the plurality of first pin header holes are used for being electrically connected with pins of the chip to be tested, and the pins comprise radio frequency input pins and voltage input pins; the second test board comprises a peripheral circuit area used for placing a peripheral circuit of the chip to be tested; the plurality of second pin header holes are connected to the plurality of first pin header holes, the plurality of second pin header holes comprise voltage pin header holes and radio frequency pin header holes, and the voltage pin header holes are used for connecting the peripheral circuit and are connected with the voltage input pin through the first pin header holes; the radio frequency pin header is used for being connected with a radio frequency tester and is connected with the radio frequency input pin through the first pin header.

Description

Technical Field

[0001] The present application relates to the field of radio frequency, and particularly to a test device that is compatible with a chip for electrostatic discharge testing and radio frequency testing. Background Art

[0002] Electrostatic discharge (ESD) is an extremely important part in the reliability verification of chips. The purpose of device-level ESD testing is to determine whether a small amount of ESD discharges cause performance degradation or damage to the device under test (DUT) such as an integrated circuit (IC).

[0003] When a chip is undergoing ESD testing, it is usually necessary to apply an instantaneous high voltage to specific pins of the chip to examine the impact of this high voltage on the internal circuit of the chip. Since the chip size is small and its pins cannot directly contact the test equipment, it is necessary to embed the chip in a carrier (such as a test board), and connect the pins led out through the carrier to the test equipment.

[0004] ESD testing belongs to DC testing and does not involve radio frequency (RF) signals. Therefore, the end connectors of the carrier carrying the chip for leading out the chip pins are mainly for transmitting DC signals and cannot be directly connected to the RF interface. After ESD testing, in order to determine whether the chip is damaged, the most effective method is to test the key performance of the chip and compare the results before and after ESD testing to determine whether there are differences.

[0005] For radio frequency chips, ESD testing may affect the radio frequency parameters of the radio frequency chips before and after. Therefore, it is necessary to test the radio frequency parameters before and after ESD testing to evaluate the impact of ESD testing on radio frequency performance. The testing of radio frequency parameters requires the radio frequency chip to have a complete peripheral circuit, such as resistors, capacitors, and coaxial transmission lines for conducting radio frequency signals, etc.

[0006] However, in the current radio frequency chip testing, the peripheral circuit cannot participate in the ESD testing together because the peripheral circuit may be affected by the ESD testing, and the peripheral circuit will also affect the normal progress of the ESD testing. Therefore, currently it is impossible to accurately evaluate the impact of ESD testing on radio frequency parameters. Summary of the Invention

[0007] In order to implement the use of a set of test devices to perform electrostatic discharge testing and radio frequency testing on a chip, the present application proposes a test device that is compatible with a chip for electrostatic discharge testing and radio frequency testing to accurately evaluate the impact of ESD testing on radio frequency parameters.

[0008] The test device includes: A first test board for performing electrostatic discharge testing, including: A chip placement area for placing the chip to be tested; Multiple first row of pinholes for electrically connecting to the pins of the chip to be tested, the pins including a radio frequency input pin and a voltage input pin; A second test board for jointly performing radio frequency tests with the first test board, including: A peripheral circuit area for placing the peripheral circuit of the chip to be tested; Multiple second row of pinholes are detachably connected to the multiple first row of pinholes through first row of pins. Among the multiple second row of pinholes, there are voltage row of pinholes and radio frequency row of pinholes. The voltage row of pinholes are used to connect the peripheral circuit and connect to the voltage input pin through the first row of pinholes; the radio frequency row of pinholes are used to connect to a radio frequency tester and connect to the radio frequency input pin through the first row of pinholes.

[0009] The first row of pins is preferably integrally formed with the second row of pinholes to facilitate the disassembly and combination of the test device.

[0010] Optionally, the first test board includes a second row of pins, and the second test board includes a third row of pins; for the first row of pins of the radio frequency row of pinholes, it is surrounded by the second row of pins, the third row of pins, and at least part of the first row of pins of the voltage row of pinholes. Thus, a quasi-coaxial structure is formed, which can shield radio frequency signals and provide good impedance matching, thereby reducing the loss and interference of radio frequency signals and improving the transmission performance of radio frequency signals.

[0011] Optionally, the second row of pins is located outside the first row of pins, and the third row of pins is located inside the first row of pins; both the second row of pins and the third row of pins are grounded. Based on the structures of the first test board and the second test board, this setting facilitates the wiring design in the first test board and the second test board.

[0012] Optionally, there is a height difference between the second row of pins and the second test board, and between the third row of pins and the first test board.

[0013] Optionally, the first test board includes multiple second rows of pins, and the second test board includes multiple third rows of pins; the second row of pins is arranged outside the first row of pins of the voltage row of pinholes, and the third row of pins is arranged inside.

[0014] Optionally, the first test board includes multiple second rows of pins; for the first row of pins of the radio frequency row of pinholes, multiple second rows of pins surround it; or, the second test board includes multiple third rows of pins; for the first row of pins of the radio frequency row of pinholes, it is surrounded by multiple third rows of pins.

[0015] Optionally, the peripheral circuit area includes mounting positions for installing at least one of a resistor, a capacitor, and an inductor.

[0016] Optionally, the second test board further includes: A power supply pin hole for connecting a power supply and connecting to the mounting position; A radio frequency connector for connecting to the radio frequency tester and connecting to the radio frequency pin hole through a radio frequency connection line.

[0017] Optionally, the first test board includes at least two metal layers, and the metal layer on the side facing away from the second test board is a reference ground metal layer; The second test board includes at least two metal layers, and the metal layer on the side facing the first test board is a reference ground metal layer, or the metal layer on the side facing away from the first test board is a reference ground metal layer.

[0018] In summary, through the test device for electrostatic discharge test and radio frequency test using the compatible chip proposed in this application, especially through the first pin hole, the first row of pins and the second pin hole, the first test board (i.e., the ESD test board) and the second test board (i.e., the RF test board) can be conveniently combined and split. The first test board can independently perform the ESD test to ensure that there is no peripheral circuit interference around the chip during the ESD test, avoiding the influence of the peripheral circuit on the ESD test result, thereby improving the accuracy of the test result. At the same time, through the first pin hole and the second pin hole, the combination of the first test board and the second test board can be realized. The second test board can carry the peripheral circuit to ensure the accuracy of the radio frequency performance test.

[0019] Because of the integrated design of the test device, it is ensured that the radio frequency performance (such as radio frequency parameters) can be measured in the same test environment before and after the ESD test, so as to accurately compare and evaluate the influence of the ESD test on the radio frequency performance.

[0020] In addition, the first test board and the second test board can be put into production at the same time during board manufacturing, and multiple different second test boards can be manufactured at one time to adapt to the radio frequency pin positions of different chips, improving the versatility and flexibility of the device and meeting the test requirements of multiple chips.

[0021] The first pin hole and the second pin hole are connected by the first row of pins, which can conveniently realize the detachable connection between the first pin hole and the second pin hole and provide electrical conduction and mechanical support.

[0022] The first test board includes a second row of pins, and the second test board includes a third row of pins; for the first row of pins of the radio frequency pin hole, it is surrounded by the second row of pins, the third row of pins, and at least part of the first row of pins of the voltage pin hole. The first row of pins, the second row of pins, and the third row of pins form a quasi-coaxial structure to ensure good inter-board transmission performance of radio frequency signals, reducing signal loss and interference. Description of the Drawings

[0023] Figure 1 is a plan view of an ESD test board according to an embodiment of the present application Figure 1 。

[0024] Figure 2 is a cross-sectional view of an ESD test board according to an embodiment of the present application.

[0025] Figure 3 is a plan view of an RF test board according to an embodiment of the present application Figure 1 。

[0026] Figure 4 is a cross-sectional view of an RF test board according to an embodiment of the present application.

[0027] Figure 5 is a schematic diagram of a test device during ESD testing according to an embodiment of the present application.

[0028] Figure 6 is a plan stacking schematic diagram of a test device during RF testing according to an embodiment of the present application.

[0029] Figure 7 is a cross-sectional view of a test device during RF testing according to an embodiment of the present application.

[0030] Figure 8 is a plan view of an RF test board according to an embodiment of the present application Figure 2 。

[0031] Figure 9 is a plan view of an ESD test board according to an embodiment of the present application Figure 2 。

[0032] Figure 10 is a flowchart of a test method according to an embodiment of the present application. Specific Embodiments

[0033] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than limiting the disclosure. Additionally, it should be noted that for ease of description, only parts related to the relevant disclosure are shown in the drawings.

[0034] In the present application, by using an ESD test board (i.e., the first test board) and an RF test board (i.e., the second test board) that can be freely disassembled and combined, the accuracy of the test results is improved, and the impact of ESD testing on radio frequency performance can be accurately compared and evaluated. Next, reference will be made to Figures 1 to 4 to illustrate the structures of the ESD test board and the RF test board.

[0035] Figure 1 is a plan view of an ESD test board 100 for ESD testing proposed in this application. The ESD test board can be a printed circuit board (Printed Circuit Board), including a chip placement area 101 and a plurality of first row pinholes 102. Among them, the chip placement area 101 is used to place the chips to be tested that need to undergo ESD testing and RF testing. The chips to be tested can be RF chips, such as amplifier chips, attenuator chips, beamforming chips, and so on. The plurality of first row pinholes 102 are used to be electrically connected to a plurality of pins of the chips to be tested respectively, so as to perform electrical transmission with the pins of the chips to be tested. For example, they can be electrically connected through Figure 1 the plurality of electrical connection lines 103 shown in. When the chips to be tested are placed in the chip placement area 101, the electrical connection lines 103 conduct the pins of the chips to be tested and the corresponding first row pinholes 102. Since it is necessary to perform ESD testing using DC voltage and RF testing using RF signals on the chips to be tested, the pins of the chips to be tested include RF input pins and voltage input pins. The RF input pins are used to input RF signals into the chips to be tested, and the voltage input pins are used to input voltages into the chips to be tested.

[0036] In addition, the ESD test board further includes a plurality of first grounding holes 104 for grounding (as shown by the black circles in Figure 1 ) to shield test signals. Since electrical connection lines need to be arranged inside the first row pinholes 102, the plurality of first grounding holes 104 are preferably arranged close to the ground on the outside of the first row pinholes 102 to facilitate wiring. "Close to" means as close as possible, for example, the distance between the two is less than 3 millimeters, so as to achieve a better shielding effect.

[0037] Figure 2 shows Figure 1 a cross-sectional view of the ESD test board along the dashed line A-A' in, for reference to Figure 2 illustrate the hierarchical structure of the ESD test board. Figure 2 the ESD test board structure including two metal layers shown in. As shown in Figure 2As shown, when the ESD test board is combined with the RF test board, the metal layer facing the side of the RF test board is the first top metal layer 201, and the first bottom metal layer 202 facing the side of the RF test board is used as the reference ground metal layer of the ESD test board. In other embodiments, the metal layer facing away from the side of the RF test board may be the first top metal layer 201, and the first bottom metal layer 202 facing the side of the RF test board may be used as the reference ground metal layer of the ESD test board. Among them, the first top metal layer 201 is used to prepare and lay the electrical connection line 103. The structure of the two metal layers can facilitate the preparation of the electrical connection line and the grounding preparation of the first grounding hole 104, and can balance the signal quality and the complexity of the test board structure. It can be understood that based on different test requirements and test environments, the ESD test board can be a metal layer with different numbers of layers. For example, only one metal layer as a ground layer can be retained, and the electrical connection line 103 is connected by a flying wire method. For more complex test requirements, more layers of metal layers can also be used. For example, the ESD test board can also include three or more layers of metal layers.

[0038] Figure 3 It is a planar schematic diagram of an RF test board 300 for RF testing proposed in the present application. The RF test board can be a printed circuit board (Printed Circuit Board), including a plurality of second rows of pinholes 301 and a peripheral circuit area 302. Among them, the peripheral circuit area includes a plurality of mounting positions for setting a plurality of peripheral circuits of the chip to be tested (not shown in the figure to clearly show the peripheral circuit), wherein the mounting position is connected to the wiring 303 arranged on the metal layer, and can be any device such as a jack, a patch, a solder joint, etc. that can install electronic devices, and is used to install the peripheral circuit on the RF test board 300. At least one of a resistor, a capacitor, and an inductor can be installed in the mounting position as a peripheral circuit according to the needs of the RF test. In the RF test, the peripheral circuit is electrically connected to the chip to be tested, and the peripheral circuit is used for matching, filtering signal noise, filtering power supply noise, etc. The peripheral circuit can ensure the accuracy of the RF performance test, or realize the functions of matching different chips to be tested, so as to build a complete RF test circuit and realize RF testing, thereby the resistor, capacitor, and inductor can be set interchangeably, and when the chips to be tested are different, resistors, capacitors, and inductors with different parameters can be selected. Preferably, the peripheral circuit includes an RLC circuit consisting of a resistor, a capacitor and an inductor.

[0039] When combining the RF test board and the ESD test board for RF testing, it is necessary to supply the working voltage and the RF signal to the chip under test. Therefore, among the multiple second row of pinholes 301, there are a voltage pinhole 304 and an RF pinhole 305. The voltage pinhole 304 is used to transmit the working voltage, and the RF pinhole 305 is used to transmit the RF signal. In addition, a power supply pinhole 306 is provided on one side of the peripheral circuit, which is used to connect to an external power supply (not shown in the figure for clarity) and the peripheral circuit provided at the installation position of the trace 303. To improve the RF signal transmission performance, the RF test board can also be provided with an RF connector 307, one end of which is connected to an RF tester (not shown in the figure for clarity), and the other end is connected to the RF pinhole 305 through an RF connection line 308. The voltage pinhole 304 is used to connect to the peripheral circuit. The external power supply accessed passes through the power supply pinhole 306, the peripheral circuit provided on the trace 303, and the voltage pinhole 304 connected to the trace 303, and then is transmitted to the ESD test board through the first row of pinholes corresponding to the voltage pinhole 304, and is connected to the voltage input pin of the chip under test through an electrical connection line, such as Figure 3 all the second row of pinholes connected to the trace 303 in are voltage pinholes; the RF pinhole 305 is used to connect to an RF tester (which can be various devices for inputting RF signals). The external RF signal accessed passes through the RF connector 307, the RF connection line 308, and the RF pinhole 305, and then is transmitted to the ESD test board through the first row of pinholes corresponding to the RF pinhole 305, and is connected to the RF input pin of the chip under test through an electrical connection line, such as Figure 3 the second row of pinholes connected to the RF connection line 308 in is the RF pinhole.

[0040] In addition, the RF test board can also include multiple second ground holes 309 for grounding, which are used to form a shield. Since the peripheral circuit needs to be arranged outside the second row of pinholes 301, the multiple second ground holes 309 are preferably arranged close to the ground on the inner side of the second row of pinholes 301 to facilitate wiring.

[0041] Figure 4 shows Figure 3 a cross-sectional view of the RF test board along the dashed line B-B' in, refer to Figure 4 to illustrate the layered structure of the RF test board, where the power supply pinhole 306 located on the right side is not visible in the cross-sectional view, so it is shown as a dashed line. Figure 4 the structure of the RF test board including two metal layers shown in. As Figure 4As shown, the RF test board includes a second top metal layer 401 and a second bottom metal layer 402. In some embodiments, when the ESD test board is combined with the RF test board, the metal layer on the side facing away from the ESD test board is the second top metal layer 401, and the second bottom metal layer 402 facing the ESD test board serves as the reference ground metal layer; in other embodiments, when the ESD test board is combined with the RF test board, the metal layer on the side facing the ESD test board is the second top metal layer 401, and the second bottom metal layer 402 on the side facing away from the ESD test board serves as the reference ground metal layer. At this time, the signal traces on the two test boards are placed close to each other, which can reduce the mismatch effect when the signal passes through the test board. It can be understood that based on different test requirements and test environments, the RF test board can have metal layers of different numbers of layers.

[0042] Since the first test board and the second test board are detachable independent boards, the first test board and the second test board can be put into production simultaneously during plate making. And because RF testing may need to face different test environments and test conditions, multiple different RF test boards can also be made at one time for adaptation, improving the versatility and flexibility of the device and meeting the test requirements of multiple chips.

[0043] Next, refer to Figure 5 and Figure 6 to illustrate the structure when using this test device for ESD testing and RF testing.

[0044] Figure 5 is a schematic diagram of the test device during ESD testing. During ESD testing, only the ESD test board is used without combining it with the RF test board. In the Figure 5 shown embodiment, the ESD tester 501 is electrically connected to the ESD test board through the pin 502. Among them, the pin 502 is inserted into the first pin hole 102 to connect the ESD tester 501 and the ESD test board. Among them, the pin hole is a jack located on the test board. The pin hole can be inserted with a pin, and the side wall of the pin hole has metal for forming an electrical connection with the pin.

[0045] When performing ESD testing, such as performing Human Body Model (HBM) testing, the instantaneous high voltage generated by the ESD tester 501 is transmitted to the first pin hole 102 in the ESD test board through the pin 502, and is transmitted to the corresponding pin of the chip under test 506 via the electrical connection line 103. The transmission path of the voltage signal is as shown by the dotted line L1 in Figure 5 It can be understood that when performing different test items, the first pin hole 102 into which the pin 502 is inserted is the pin hole connected to the pin corresponding to the test item, and the ESD testing of each pin is completed in sequence accordingly.

[0046] Figure 6 Schematic diagram of the planar stack of the test device when performing RF testing Figure 7 When performing RF testing along Figure 7 The cross-sectional view of the test device shown along the dashed line C-C'. When performing RF testing, since an ESD test board is required to carry the chip under test, the RF test board and the ESD test board need to be combined. In Figure 7 In the illustrated embodiment, when the ESD test board and the RF test board are combined, the second bottom metal layer 402 of the RF test board serving as the reference ground faces the first top metal layer 201 for signal routing of the ESD test board; in other embodiments, the second top metal layer 401 for signal routing in the RF test board and the first top metal layer 201 for signal routing in the ESD test board are arranged face to face. In still other embodiments, it may also be that the second bottom metal layer 402 of the RF test board serving as the reference ground faces the first bottom metal layer 202 of the ESD test board serving as the reference ground; or the second top metal layer 401 for signal routing in the RF test board and the first bottom metal layer 202 of the ESD test board serving as the reference ground are arranged face to face.

[0047] The detachable connection between the first row of pin holes and the second row of pin holes is achieved through the first row of pins. One end of the first row of pins is used to connect to the first row of pin holes of the ESD test board 100, and the other end of the first row of pins is used to connect to the second row of pin holes of the RF test board 300. Since the number of both the first row of pin holes and the second row of pin holes is multiple, multiple first rows of pins can be used, and each first row of pins connects a corresponding set of the first row of pin holes and the second row of pin holes. For example Figure 6 as shown by the first row of pins 1, the first row of pins 2, and the first row of pins 4, and Figure 7 as shown by the first row of pins 1 in, among which, the first row of pins 1 is used to transmit radio frequency signals, the first row of pins 2 and the first row of pins 4 can be connected to the DC power supply, and the first row of pins 2 and the first row of pins 4 can also be grounded. In addition, in order to facilitate the construction or combination of the test device, the second row of pin holes can be integrally formed with the first row of pins.

[0048] Refer to Figure 6 and Figure 7 to illustrate the structure of the test device when performing RF testing.

[0049] When performing RF testing, the DC power supply 701 is connected to the power supply pin holes 306 on the RF test board through a connecting device (such as a pin 702). Thus, the DC voltage output by the DC power supply 701 is transmitted to the corresponding voltage input pins of the chip under test 707 after passing through the pin 702, the power supply pin holes 306, the peripheral circuit provided on the trace 303, the power supply pin holes 306, the voltage pin holes 304, the first row of pins 703, and the electrical connection line 103, so as to provide a working voltage for the chip under test, and the current path is as shown in Figure 7As shown by the dashed line L2 in the figure. In addition, the RF tester 708 is connected to the RF connector 307, so that the RF signal emitted by the RF tester 708 is transmitted to the RF input pin of the chip under test 707 via the RF connector 307, connected to the RF pin hole 305, the first row of pins 1, the first row of pin holes 102, and the electrical connection line 103, so as to provide an RF signal for RF testing for the chip under test 707. The current path is as Figure 7 shown by the dashed line L3 in the figure.

[0050] In addition, in order to improve the transmission performance of the RF signal, a row of pins is also arranged around the first row of pins 1 connected to the RF pin hole to form a quasi-coaxial structure, as Figure 6 shown. There are 4 rows of pins surrounding the side of the first row of pins 1 in the RF pin hole, including the first row of pins 2, the second row of pins 3, the first row of pins 4, and the third row of pins 5, so as to form a quasi-coaxial structure to ensure the integrity of RF signal transmission. Among them, the first row of pins 2 and the first row of pins 4 are connected to the voltage pin holes adjacent to the RF pin hole. The second row of pins 3 can be detachably arranged to be connected to the first grounding hole on the ESD test board. The third row of pins 5 can be detachably arranged to the second grounding hole on the RF test board. The second row of pins 3 and the third row of pins 5 constitute the metal ground in the quasi-coaxial structure, so that the quasi-coaxial structure shields the first row of pins 1. And there is a height difference between the second row of pins 3 and the RF test board, and between the third row of pins 5 and the ESD test board, that is, the second row of pins 3 is not connected to the RF test board, and the third row of pins 5 is not connected to the ESD test board to avoid short circuit.

[0051] In addition, the first row of pins, the second row of pins, and the third row of pins can also be spring pins. And although Figure 6 only four rows of pins are shown in the up, down, left, and right directions of the first row of pins 1 to form a quasi-coaxial structure, it can be understood that the more rows of pins arranged around the first row of pins 1, the better the effect. For example, rows of pins are arranged at the remaining eight positions in the nine-square grid centered on the first row of pins to form a quasi-coaxial structure with better effect.

[0052] In addition to the first row of pins in the RF pin hole, a quasi-coaxial structure can also be set for the first row of pins in the voltage pin hole. That is, the second row of pins can be arranged in multiple first grounding holes on the ESD test board, and the third row of pins can be arranged in multiple second grounding holes on the RF test board.

[0053] In some embodiments, the first row of pins 1 for transmitting RF signals can also be surrounded by multiple third rows of pins 5 to form a quasi-coaxial structure. For example, in Figure 8In the RF test board shown, the RF pin holes 305 can be surrounded by the grounded second grounding holes 309. When the first row of pins 1 is inserted into the RF pin holes 305 and the third row of pins 5 are respectively inserted into the multiple second grounding holes 309, the grounded third row of pins 5 surrounds the first row of pins 1, forming a quasi-coaxial structure.

[0054] In some embodiments, the first row of pins 1 for transmitting RF signals can also be surrounded by multiple second rows of pins 3 to form a quasi-coaxial structure. For example, in Figure 9 the ESD test board shown, the first pin hole 102 for transmitting RF signals can be surrounded by the grounded first grounding holes 104. When the first row of pins 1 is inserted into the first pin hole 102 for transmitting RF signals and the second rows of pins 3 are respectively inserted into the multiple first grounding holes 104, the grounded second rows of pins 3 surround the first row of pins 1, forming a quasi-coaxial structure.

[0055] Finally, refer to Figure 10 the flowchart to illustrate the test method for performing ESD tests and RF tests using this test device.

[0056] In step 901, install the chip under test onto the chip test socket and combine the ESD test board and the RF test board by connecting the first pin holes and the second pin holes. As Figure 6 、 Figure 7 shown, the ESD test board and the RF test board are electrically connected and combined through the first pin holes and the second pin holes with structures such as pin rows or spring pins.

[0057] In step 902, input an RF signal into the test device through the RF connector to perform the first RF test. This step is used to obtain the results of the RF test without being affected by the ESD test.

[0058] As Figure 7 shown, the DC power supply 701 supplies the operating voltage to the chip under test 707 through path L2, and the RF tester 708 supplies the RF signal required for the RF test to the chip under test 707 through the RF connector 709 and through path L3.

[0059] And the RF performance can be tested at the test pins of the chip under test 707, such as testing the RF power, voltage intensity, etc. output by the chip under test 707.

[0060] In step 903, disassemble the ESD test board and the RF test board, and connect the voltage output terminal of the electrostatic discharge tester to the corresponding first pin hole for the electrostatic discharge test. Since the peripheral circuit of the chip under test during the RF test will affect the test results of the ESD test, and the peripheral circuit may also be affected by the ESD test, the test device is disassembled to perform the ESD test using only the ESD test board. As Figure 5As shown, the DC power supply of the ESD tester 501 inputs a DC voltage to the ESD test board through path L1 to start the chip under test 506 and adjust the voltage for corresponding ESD test items.

[0061] In step 904, the ESD test board and the RF test board are combined again, and an RF signal is input to the test device through the RF connector for the second RF test.

[0062] As Figure 7 shown, the DC power supply 701 provides a working voltage to the chip under test 707 through path L2, and the RF tester 708 provides the RF signal required for RF testing to the chip under test 707 through the RF connector 709 and through path L3. The magnitudes of the working voltage and the RF signal provided to the chip under test 707 in step 904 are the same as those in step 902. To measure the RF performance under the same test environment.

[0063] And the RF performance can be tested at the test pins of the chip under test 707, such as testing the RF power, voltage intensity, etc. output by the chip under test 707.

[0064] Since the ESD test will affect the parameters of the chip under test, it is necessary to perform the RF test again after the ESD test to compare with the test results of the first RF test.

[0065] In step 905, compare the test results of the first RF test and the second RF test to obtain the impact of the electrostatic discharge test on the RF performance.

[0066] Through the above test method using the test device proposed in this application, the impact of the ESD test on the RF parameters of the chip can be detected without affecting the ESD test results.

[0067] The above uses specific specific embodiments to illustrate the implementation manners of this application, and those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Although the description of this application will be introduced in combination with preferred embodiments, this does not mean that the features of this invention are limited to this implementation manner. In addition, in order to avoid confusion or obscuring the key points of this application, some specific details will be omitted in the description. It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other.

[0068] In addition, various operations will be described as multiple discrete operations in the most helpful way for understanding the illustrative embodiments; however, the described order should not be construed as implying that these operations must depend on the order. In particular, these operations do not need to be performed in the presented order.

[0069] Unless the context otherwise requires, the terms "comprise", "include" and "have" are synonyms. The phrase "A / B" means "A or B". The phrase "A and / or B" means "(A and B) or (A or B)".

[0070] As used herein, the term "module" or "unit" may refer to, be, or include: an application specific integrated circuit (ASIC), an electronic circuit, a (shared, dedicated, or group) processor and / or memory that executes one or more software or firmware programs, combinational logic circuitry, and / or other suitable components that provide the described functionality.

[0071] In the drawings, some structural or method features are shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or ordering may not be required. In some embodiments, these features may be arranged in a different manner and / or order than shown in the illustrative drawings. Additionally, the inclusion of a structural or method feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0072] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements or data, these elements or data should not be limited by these terms. These terms are only used to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0073] It should be noted that in this specification, like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

[0074] Although the present invention has been illustrated and described with reference to certain preferred embodiments thereof, those of ordinary skill in the art should understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

1. A test device for a compatible chip to perform electrostatic discharge testing and radio frequency testing, characterized in that The test device includes: A first test board for performing electrostatic discharge tests, including: A chip placement area for placing the chip under test; A plurality of first row pin holes for electrically connecting to the pins of the chip under test, the pins including a radio frequency input pin and a voltage input pin; A second test board for jointly performing radio frequency tests with the first test board, including: A peripheral circuit area for placing the peripheral circuit of the chip under test; A plurality of second row pin holes detachably connected to the plurality of first row pin holes through first row pins. Among the plurality of second row pin holes, there are a voltage row pin hole and a radio frequency row pin hole. The voltage row pin hole is used to connect to the peripheral circuit and connect to the voltage input pin through the first row pin hole; the radio frequency row pin hole is used to connect to a radio frequency tester and connect to the radio frequency input pin through the first row pin hole.

2. The test device according to claim 1, characterized in that, The first test board includes second row pins, and the second test board includes third row pins; For the first row pins of the radio frequency row pin hole, they are surrounded by the second row pins, the third row pins, and at least part of the first row pins of the voltage row pin holes.

3. The testing device according to claim 2, characterized in that, The second row pins are located outside the first row pins, and the third row pins are located inside the first row pins; Both the second row pins and the third row pins are grounded.

4. The testing device according to claim 2, wherein There is a height difference between the second row pins and the second test board, and between the third row pins and the first test board.

5. The test device according to claim 2, characterized in that, The first test board includes a plurality of the second row pins, and the second test board includes a plurality of the third row pins; The second row pins are arranged outside the first row pins of the voltage row pin hole, and the third row pins are arranged inside.

6. The testing device according to claim 1, characterized in that, The first test board includes a plurality of second row pins; for the first row pins of the radio frequency row pin hole, they are surrounded by the plurality of second row pins; Or, the second test board includes a plurality of third row pins; for the first row pins of the radio frequency row pin hole, they are surrounded by the plurality of third row pins.

7. The test device according to any one of claims 1 to 6, characterized in that, The peripheral circuit area includes mounting positions for mounting at least one of a resistor, a capacitor, and an inductor.

8. The test device according to claim 7, wherein, The second test board further includes: A power supply row pin hole for connecting to a power supply and connecting to the mounting position; A radio frequency connector for connecting to the radio frequency tester and connecting to the radio frequency row pin hole through a radio frequency connection line.

9. The test device according to any one of claims 1 to 6, characterized in that, The first test board includes at least two metal layers, and the metal layer on the side facing away from the second test board is a reference ground metal layer; The second test board includes at least two metal layers, and the metal layer on the side facing the first test board is a reference ground metal layer, or the metal layer on the side facing away from the first test board is a reference ground metal layer.

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