Sampling circuit detection method, circuit, device, medium, equipment and system

Abstract

The embodiment of the invention provides a sampling circuit detection method, circuit, device, medium, equipment and system. The method comprises the following steps: controlling a channel switching module in a sampling circuit to be in a gating state corresponding to a known signal; the channel switching module is used for selecting and outputting a signal corresponding to a current gating state from a plurality of received signals; and determining the fault condition of the sampling circuit according to the size of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal. The method is used for carrying out fault detection on the sampling circuit, and the accuracy of the effectiveness detection result of the protection device is improved.

Description

Technical Field

[0001] This application relates to the technical field of voltage detection, and particularly to a detection method, circuit, device, medium, equipment and system for a sampling circuit. Background Art

[0002] In a battery system, by setting protection devices, rapid response can be achieved in case of overvoltage or overcurrent, thereby effectively protecting the battery system. Detecting whether the protection devices are effective plays an important role in the safe and stable operation of the battery management system.

[0003] Currently, a sampling circuit is used to monitor the voltage at a preset sampling point to detect the effectiveness of the protection devices. When it is detected that the protection devices fail, the battery system can switch to an emergency operation mode or a safe state to avoid potential safety problems such as thermal runaway that may occur after the protection function fails.

[0004] There is a problem that the sampling circuit itself cannot be fault-detected, which affects the accuracy of the detection result of the effectiveness of the protection devices. Summary of the Invention

[0005] Embodiments of this application provide a detection method, circuit, device, medium, equipment and system for a sampling circuit, which are used to perform fault detection on the sampling circuit itself and improve the accuracy of the detection result of the effectiveness of the protection devices.

[0006] In a first aspect, embodiments of this application provide a detection method for a sampling circuit, including: controlling a channel switching module in the sampling circuit to be in a gating state corresponding to a known signal; wherein, the channel switching module is used to select and output a signal corresponding to the current gating state from multiple received signals;

[0007] Determine the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal.

[0008] Optionally, the determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal specifically includes:

[0009] If, in the gating state corresponding to any known signal, the output result of the sampling circuit indicates that the signal actually output by the channel switching module is within the preset range, it is determined that the sampling circuit has a fault.

[0010] Optionally, the gating state corresponding to the known signal includes a first gating state and a second gating state;

[0011] The first gating state corresponds to a first known signal, and the second gating state corresponds to a second known signal.

[0012] Optionally, the first known signal is outside the preset range, and the second known signal is within the preset range;

[0013] Or, both the first known signal and the second known signal are outside the preset range, and are respectively outside the upper and lower limits of the preset range.

[0014] Optionally, determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal specifically includes:

[0015] When the channel switching module is in the first gating state, determining the output results of the first comparators of the analog detection module and the digital detection module;

[0016] And, when the channel switching module is in the second gating state, determining the output results of the second comparators of the analog detection module and the digital detection module;

[0017] Determining the fault condition of the sampling circuit according to the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal.

[0018] Optionally, the determining according to the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically includes:

[0019] If the output results of the first comparators of the analog detection module and the digital detection module in the first gating state all match the first known signal;

[0020] And, if the output results of the analog detection module and the second comparators in the second gating state all match the second known signal, it is determined that the sampling circuit has no fault.

[0021] Optionally, the determining according to the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically includes:

[0022] If the output results of the first comparators of the analog detection module and the digital detection module in the first gating state all match the first known signal;

[0023] And, if the output result of the analog detection module in the second gating state does not match the second known signal, it is determined that the channel switching module is faulty.

[0024] Optionally, the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically include:

[0025] If the output results of the analog detection module and the first comparator of the digital detection module in the first gating state both match the first known signal;

[0026] And, if the output result of the analog detection module in the second gating state matches the second known signal, and the output result of the second comparator does not match the second known signal, it is determined that the second comparator is faulty.

[0027] Optionally, the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically include:

[0028] If the output result of the first comparator in the first gating state does not match the first known signal;

[0029] And, if the output result of the analog detection module in the second gating state matches the second known signal, it is determined that the first comparator is faulty.

[0030] Optionally, the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically include:

[0031] If the output result of the first comparator in the first gating state does not match the first known signal;

[0032] And, if the output result of the analog detection module in the second gating state does not match the second known signal, it is determined that the analog detection module and / or the channel switching module is faulty.

[0033] Optionally, the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically include:

[0034] If the output result of the analog detection module in the first gating state does not match the first known signal, and the output result of the first comparator matches the first known signal;

[0035] And, if the output result of the analog detection module in the second gating state matches the second known signal, it is determined that the channel switching module is faulty.

[0036] Optionally, the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically include:

[0037] If the output result of the analog detection module in the first gating state does not match the first known signal, and the output result of the first comparator matches the first known signal;

[0038] And, if the output result of the analog detection module in the second gating state does not match the second known signal, it is determined that the analog detection module is faulty.

[0039] Optionally, after determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal, the method further includes:

[0040] If the sampling circuit is not faulty, control the channel switching module in the sampling circuit to be in the gating state corresponding to the sampling signal, so as to output the signal corresponding to the current gating state from multiple received signals; the sampling signal is obtained by monitoring a preset sampling point through the sampling conditioning module of the sampling circuit;

[0041] Determine the effectiveness of the sampling signal and the sampling conditioning module according to the magnitude of the sampling signal and the output results of the digital detection module and the analog detection module in the gating state corresponding to the sampling signal.

[0042] Optionally, the determining the effectiveness of the sampling signal and the sampling conditioning module according to the magnitude of the sampling signal and the output results of the digital detection module and the analog detection module in the gating state corresponding to the sampling signal specifically includes:

[0043] If the output result of the analog detection module is within the preset range of the signal corresponding to the gating state, and the output results of the first comparator and the second comparator of the digital detection module both indicate that the signal corresponding to the gating state is within the preset range, it is determined that the sampling signal and the sampling conditioning module are effective.

[0044] Optionally, the determining the effectiveness of the sampling signal and the sampling conditioning module according to the magnitude of the sampling signal and the output results of the digital detection module and the analog detection module in the gating state corresponding to the sampling signal specifically includes:

[0045] If the output result of the analog detection module is within the preset range of the signal corresponding to the gating state, and the output result of the first comparator or the second comparator of the digital detection module indicates that the signal corresponding to the gating state is outside the preset range, it is determined that the sampling conditioning module fails.

[0046] Optionally, determining the validity of the sampling signal and the sampling conditioning module according to the magnitude of the sampling signal and the output results of the digital detection module and the analog detection module in the gating state corresponding to the sampling signal specifically includes:

[0047] If the output result of the analog detection module is outside the preset range of the signal corresponding to the gating state, and the output result of the first comparator or the second comparator of the digital detection module indicates that the signal corresponding to the gating state is outside the preset range, it is determined that the sampling signal is valid.

[0048] Optionally, determining the validity of the sampling signal and the sampling conditioning module according to the magnitude of the sampling signal and the output results of the digital detection module and the analog detection module in the gating state corresponding to the sampling signal specifically includes:

[0049] If the output result of the analog detection module is outside the preset range of the signal corresponding to the gating state, and the output results of both the first comparator and the second comparator of the digital detection module indicate that the signal corresponding to the gating state is within the preset range, it is determined that the sampling circuit fails.

[0050] In a second aspect, an embodiment of the present application provides a sampling circuit, including:

[0051] A channel switching module, configured to select and output a signal corresponding to the current gating state from multiple received signals in the gating state corresponding to a known signal;

[0052] An analog detection module, connected to the channel switching module, for performing analog-to-digital conversion on the signal actually output by the channel switching module;

[0053] A digital detection module, connected to the channel switching module, for detecting whether the magnitude of the signal actually output by the channel switching module is within a preset range.

[0054] Optionally, the digital detection module includes: a first comparator and a second comparator;

[0055] The first input terminal of the first comparator and the first input terminal of the second comparator are connected to the channel switching module; the second input terminal of the first comparator is connected to a first reference signal; the second input terminal of the second comparator is connected to a second reference signal; the output terminals of the first comparator and the second comparator are connected as the output terminal of the digital detection module; wherein, the first reference signal and the second reference signal are used to determine the preset range.

[0056] Optionally, the first reference signal is higher than the second reference signal; the output terminal of the first comparator is connected to the output terminal of the second comparator through a NOT gate or connected as the output terminal of the digital detection module;

[0057] Alternatively, the first reference signal is lower than the second reference signal; the output terminal of the second comparator is connected to the output terminal of the first comparator through a NOT gate or connected as the output terminal of the digital detection module.

[0058] Optionally, the digital detection module further includes: a first isolation module disposed at the output terminal of the digital detection module;

[0059] The first isolation module is configured to conduct / break based on the output signal of the digital detection module, so as to output the output signal of the digital detection module after level conversion.

[0060] Optionally, the first isolation module includes: an optocoupler;

[0061] One end of the optocoupler receives the output signal of the digital detection module, the other end of the optocoupler is grounded, the third end of the optocoupler is connected to a power supply, and the output terminal of the optocoupler is configured to output a processed signal.

[0062] Optionally, the digital detection module further includes: an output setting module;

[0063] One end of the output setting module is connected to the output terminal of the optocoupler, the other end of the output setting module is grounded, and the third end of the output setting module outputs the output signal of the optocoupler.

[0064] The output setting module is configured to output a known level when the optocoupler is off, and invert the output level when the optocoupler is on.

[0065] Optionally, the output setting module includes: a first resistor and a second resistor;

[0066] One end of the first resistor is connected to the output end of the optocoupler; the other end of the first resistor and one end of the second resistor are connected to the ground; the other end of the second resistor outputs the output signal of the optocoupler.

[0067] Optionally, the channel switching module includes: a multi-channel selector;

[0068] The multi-channel selector is configured to be in a corresponding gated state according to the received gating signal.

[0069] Optionally, the sampling circuit further includes: a second isolation module connected to the multi-channel selector;

[0070] The second isolation module is configured to conduct / turn off based on the received gating signal, and output the received gating signal to the multi-channel selector after level conversion.

[0071] Optionally, the sampling circuit further includes: a sampling conditioning module;

[0072] The sampling conditioning module is connected to the channel switching module, and is configured to monitor a preset sampling point to obtain a plurality of sampling signals, and output the plurality of sampling signals to the channel switching module;

[0073] The channel switching module is further configured to select and output a signal corresponding to the current gated state from the plurality of sampling signals in the gated state corresponding to the sampling signal.

[0074] In a third aspect, an embodiment of the present application provides a detection device for a sampling circuit, including:

[0075] A control module, configured to control the channel switching module in the sampling circuit to be in a gated state corresponding to a known signal; wherein, the channel switching module is configured to output a signal corresponding to the current gated state from a plurality of received signals;

[0076] A determination module, configured to determine whether there is a fault in the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gated state corresponding to the known signal.

[0077] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the method according to any one of the first aspects.

[0078] In a fifth aspect, an embodiment of the present application provides a detection device, including: the sampling circuit according to any one of the second aspects, and the detection device according to the third aspect.

[0079] Sixth aspect, an embodiment of the present application provides a power supply system, including: the detection device as described in the fifth aspect, and a battery system.

[0080] Seventh aspect, an embodiment of the present application provides a transportation device, including the power supply system as described in the sixth aspect.

[0081] The detection method, circuit, device, medium, equipment and system of the sampling circuit provided by the embodiments of the present application can determine the fault condition of the sampling circuit by controlling the channel switching module of the sampling circuit to be in the gating state corresponding to the known signal and judging whether the output result of the sampling circuit matches the magnitude of the known signal under the gating state corresponding to the known signal; after determining that the sampling circuit is fault-free, the sampling circuit is used to monitor the voltage at the preset sampling points of the device under test, which can confirm the effectiveness of the sampling signal, thereby improving the accuracy of the result of the effectiveness of the protection device confirmed according to the sampling signal and improving the safety of the operation of the device under test. Description of the Drawings

[0082] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application and used together with the specification to explain the principles of the present application.

[0083] Figure 1 It is a schematic diagram of an application scenario related to an embodiment of the present application;

[0084] Figure 2 It is a schematic diagram of the structure of a sampling circuit provided by an embodiment of the present application;

[0085] Figure 3 It is a schematic diagram of the structure of another sampling circuit provided by an embodiment of the present application;

[0086] Figure 4 It is a schematic flowchart of a detection method for a sampling circuit provided by an embodiment of the present application;

[0087] Figure 5 It is a schematic flowchart of another detection method for a sampling circuit provided by an embodiment of the present application;

[0088] Figure 6 It is a schematic diagram of the structure of a third sampling circuit provided by an embodiment of the present application;

[0089] Figure 7 It is a schematic flowchart of a detection method for a third sampling circuit provided by an embodiment of the present application;

[0090] Figure 8 It is a schematic diagram of the structure of a fourth sampling circuit provided by an embodiment of the present application;

[0091] Figure 9Schematic flow chart of the fourth sampling circuit detection method provided by the embodiments of the present application;

[0092] Figure 10 Schematic flow chart of the fifth sampling circuit detection method provided by the embodiments of the present application;

[0093] Figure 11 Schematic flow chart of the sixth sampling circuit detection method provided by the embodiments of the present application;

[0094] Figure 12 Schematic structural diagram of a power supply system provided by the embodiments of the present application;

[0095] Figure 13 Schematic structural diagram of a sampling circuit detection device provided by the embodiments of the present application.

[0096] Description of reference numerals:

[0097] 1: Channel switching module; 11: Multichannel selector; 12: Second isolation module; 2: Digital detection module; 21: First comparator; 22: Second comparator; 23: First isolation module; 24: Optocoupler; 25: NOT gate; 26: Output setting module; 3: Analog detection module; 4: Calculation module; 5: Sampling conditioning module;

[0098] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed description of the specific implementation

[0099] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0100] Figure 1 Schematic diagram of an application scenario related to the embodiments of the present application. As Figure 1 shown, the specific application scenario of the present application is to perform fault detection on the sampling circuit.

[0101] In a battery system, by setting protection devices, such as fuses, contactors, etc., it is possible to quickly respond in case of overvoltage or overcurrent, thereby effectively protecting the battery system. Detecting whether the protection device is effective plays an important role in the safe and stable operation of the battery management system.

[0102] Currently, the voltage of preset sampling points in the battery system is monitored through a sampling circuit, and the detection device can perform calibration calculations based on the voltage values monitored by the sampling circuit to detect the effectiveness of the protection device. When it is detected that the protection device fails, the battery system can switch to an emergency operation mode or a safe state to avoid safety problems such as thermal runaway that may occur after the protection function fails.

[0103] There is a problem that the sampling circuit itself cannot be fault-detected. When the sampling circuit fails, the voltage monitoring results of the preset sampling points may be abnormal, which in turn affects the accuracy of the detection results of the effectiveness of the protection device.

[0104] In summary, how to perform fault detection on the sampling circuit to improve the accuracy of the detection results of the effectiveness of the protection device has become an urgent problem to be solved.

[0105] In view of this, the embodiments of the present application provide a detection method for a sampling circuit. The channel switching module is used to select a known signal from the received signal to detect the output result of the sampling circuit. According to whether the output result of the sampling circuit under the known signal matches the magnitude of the known signal, the fault condition of the sampling circuit can be determined. After determining that the sampling circuit is fault-free, the sampling circuit is used to monitor the voltage of the preset sampling points of the device under test, and the effectiveness of the sampling signal can be confirmed, thereby improving the accuracy of the effectiveness result of the protection device confirmed according to the sampling signal and improving the operation safety of the device under test.

[0106] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0107] Figure 2 It is a schematic structural diagram of a sampling circuit provided by an embodiment of the present application. As Figure 2 shown, the sampling circuit includes: a channel switching module 1, a digital detection module 2, and an analog detection module 3;

[0108] The channel switching module 1 can be, for example, any module that can switch the selected state to select one signal from multiple input signals for output. For example, it can include any one of an 8-to-1 multiplexer, a 16-to-1 multiplexer, etc. For example, the channel switching module 1 can receive a high-level or low-level selection signal and switch the selected state according to the selection signal. In one example, the channel switching module 1 can include a 16-to-1 multiplexer, receive 16 input signals, and select 1 corresponding signal from the 16 input signals for output according to the value of the 4-bit binary selection signal 0000 - 1111. For example, when the selection signal is 0000, the first input signal is selected for output; when the selection signal is 0001, the second input signal is selected for output, etc.

[0109] The digital detection module 2 can be, for example, any module that can compare the levels of the received signals to output a high-level or low-level signal. For example, it can include an analog comparator.

[0110] The analog detection module 3 can be, for example, any device that can convert an analog signal into a digital signal. For example, it can include an analog-to-digital converter (ADC).

[0111] The channel switching module 1 is used to select and output the signal corresponding to the current selected state from multiple known signals in the selected state corresponding to the known signal; among them, the multiple known signals can be, for example, voltage signals, such as 5V, 3.3V, 0V, etc. For example, the known signals input to the channel switching module 1 can include REF5V (voltage signal corresponding to 5V), REF3.3V (voltage signal corresponding to 3.3V), REF0V (voltage signal corresponding to 0V); the known signal REF5V corresponds to the selected state P8, and the known signal REF3.3V corresponds to the selected state P16. The channel switching module 1 can select and output the known signal REF5V in the selected state corresponding to REF5V, and the channel switching module 1 can select and output the known signal REF3.3V in the selected state corresponding to REF3.3V.

[0112] The analog detection module 3 is connected to the channel switching module 1 and is used to perform analog-to-digital conversion on the signal actually output by the channel switching module 1 and then output; the analog detection module 3 can, for example, convert the signal actually output by the channel switching module 1 into a binary value for output, and this binary value represents the magnitude of the signal actually output by the channel switching module 1.

[0113] The digital detection module 2, connected to the channel switching module 1, is used to detect whether the magnitude of the signal actually output by the channel switching module 1 is within a preset range and output a detection result. The preset range is determined based on the operating voltage of the sampling object. The sampling circuit can monitor the voltage of the sampling object. The sampling object can be, for example, a battery system or any power supply system other than the battery system. One function of the sampling circuit is to perform undervoltage / overvoltage detection on the sampling object, and this function is implemented by the digital detection module 2 in the sampling circuit. Therefore, the preset range here actually refers to the voltage range within which the digital detection module 2 can detect whether the sampling object is in an undervoltage / overvoltage state. The preset range can include, for example, an upper limit value and a lower limit value, where the upper limit value is greater than the lower limit value. The upper limit value can correspond to the maximum operating voltage value of the sampling object; the lower limit value can correspond to the minimum operating voltage value of the sampling object; if the signal magnitude is between the upper limit value and the lower limit value, it indicates that it is within the preset range; if the signal magnitude is higher than the upper limit value or lower than the lower limit value, it indicates that it is outside the preset range.

[0114] The sampling circuit can output results through, for example, the digital detection module 2 and / or the analog detection module 3; among them, the digital detection module 2 and the analog detection module 3 can be two independent modules or an integrated module. The embodiments of the present application do not limit this. Figure 2 Taking the digital detection module 2 and the analog detection module 3 as two independent modules as an example for illustration.

[0115] When the actual output results of the digital detection module 2 and the analog detection module 3 are consistent with the expected output results in the corresponding gating state of any known signal, it indicates that the output result of the sampling circuit matches the known signal; when the actual output results of the digital detection module 2 and / or the analog detection module 3 are inconsistent with the expected output results, it indicates that the output result of the sampling circuit does not match the known signal.

[0116] In one example, the digital detection module 2 can output a low-level signal when the magnitude of the signal actually output by the channel switching module 1 is within the preset range, and output a high-level signal when the magnitude of the signal actually output by the channel switching module 1 is outside the preset range; or, the digital detection module 2 can output a high-level signal when the magnitude of the signal actually output by the channel switching module 1 is within the preset range, and output a low-level signal when the magnitude of the signal actually output by the channel switching module 1 is outside the preset range; the embodiments of the present application do not limit this.

[0117] In one example, if the known signal is within the preset range, the digital detection module 2 should output a low-level signal; if the known signal is outside the preset range, the digital detection module 2 should output a high-level signal.

[0118] When the known signal is within the preset range, if the digital detection module 2 actually outputs a low-level signal and the voltage value actually output by the analog detection module 3 is the same as the magnitude of the known signal, it indicates that the output result of the sampling circuit matches the known signal, and it can be determined that the sampling circuit is free of faults. If the digital detection module 2 actually outputs a high-level signal, and / or the voltage value actually output by the analog detection module 3 is different from the magnitude of the known signal, it indicates that the output result of the sampling circuit does not match the known signal, and it can be determined that the sampling circuit has faults.

[0119] When the known signal is outside the preset range, if the digital detection module 2 actually outputs a high-level signal and the voltage value actually output by the analog detection module 3 is the same as the magnitude of the known signal, it indicates that the output result of the sampling circuit matches the known signal, and it can be determined that the sampling circuit is free of faults. If the digital detection module 2 actually outputs a low-level signal, and / or the voltage value actually output by the analog detection module 3 is different from the magnitude of the known signal, it indicates that the output result of the sampling circuit does not match the known signal, and it can be determined that the sampling circuit has faults.

[0120] In another example, when the known signal is within the preset range, the digital detection module 2 should output a high-level signal; when the known signal is outside the preset range, the digital detection module 2 should output a low-level signal.

[0121] When the known signal is within the preset range, if the digital detection module 2 actually outputs a high-level signal and the voltage value actually output by the analog detection module 3 is the same as the magnitude of the known signal, it indicates that the output result of the sampling circuit matches the known signal, and it can be determined that the sampling circuit is free of faults. If the digital detection module 2 actually outputs a low-level signal, and / or the voltage value actually output by the analog detection module 3 is different from the magnitude of the known signal, it indicates that the output result of the sampling circuit does not match the known signal, and it can be determined that the sampling circuit has faults.

[0122] When the known signal is outside the preset range, if the digital detection module 2 actually outputs a low-level signal and the voltage value actually output by the analog detection module 3 is the same as the magnitude of the known signal, it indicates that the output result of the sampling circuit matches the known signal, and it can be determined that the sampling circuit is free of faults. If the digital detection module 2 actually outputs a high-level signal, and / or the voltage value actually output by the analog detection module 3 is different from the magnitude of the known signal, it indicates that the output result of the sampling circuit does not match the known signal, and it can be determined that the sampling circuit has faults.

[0123] In the embodiment of the present application, it is illustrated by taking the digital detection module 2 as an example that when the magnitude of the signal actually output by the channel switching module 1 is within the preset range, a low-level signal is output, and when the magnitude of the signal actually output by the channel switching module 1 is outside the preset range, a high-level signal is output.

[0124] Taking the gating state corresponding to the known signal REF5V as P8 and the gating state corresponding to the known signal REF3.3V as P16 as an example for illustration. Among them, the known signal REF5V is outside the preset range, and the known signal REF3.3V is within the preset range.

[0125] In one example, when the channel switching module 1 is in the gating state P8, the input channel S8 is turned on, and the known signal REF5V located outside the preset range is selected and output to the analog detection module 3 and the digital detection module 2. If the output result of the analog-to-digital conversion of the signal actually output by the channel switching module 1 by the analog detection module 3 is not the same as the magnitude of the known signal, and / or the magnitude of the signal actually output by the channel switching module 1 detected by the digital detection module 2 is within the preset range, it indicates that the sampling circuit has a fault.

[0126] In one example, when the channel switching module 1 is in the gating state P16, the input channel S16 is turned on, and the known signal REF3.3V located within the preset range is selected and output to the analog detection module 3 and the digital detection module 2. If the output result of the analog-to-digital conversion of the signal actually output by the channel switching module 1 by the analog detection module 3 is not the same as the magnitude of the known signal, and / or the magnitude of the signal actually output by the channel switching module 1 detected by the digital detection module 2 is outside the preset range, it indicates that the sampling circuit has a fault.

[0127] In summary, in the embodiment of the present application, the channel switching module 1 selects and outputs the signal corresponding to the current gating state from multiple known signals in the gating state corresponding to the known signal. According to the matching relationship between the magnitude of the known signal and the output result of the sampling circuit, the fault condition of the sampling circuit can be determined.

[0128] Figure 3 FIG. is a schematic structural diagram of another sampling circuit provided by the embodiment of the present application. As Figure 3 shown, the sampling circuit includes: a channel switching module 1, a digital detection module 2, an analog detection module 3, and a sampling conditioning module 5.

[0129] The sampling conditioning module 5 can be, for example, any module that can adjust the signal amplitude. For example, it can include a voltage dividing module.

[0130] The channel switching module 1 is connected to the digital detection module 2 and the analog detection module 3; the sampling conditioning module 5 is connected to the channel switching module 1.

[0131] The sampling conditioning module 5 is used to monitor a preset sampling point to obtain multiple sampling signals and output the multiple sampling signals to the channel switching module 1.

[0132] The sampling point can be a sampling point in the battery system or a sampling point in any other power supply system.

[0133] For example, the sampling point can be a high voltage. The sampling conditioning module 5 can perform operations such as voltage division and filtering on the high voltage obtained by monitoring the sampling point according to a certain voltage division ratio, and convert it into a sampling signal with a low voltage and then input it to the channel switching module 1 to match the operating voltage supported by the channel switching module 1 and the preset range.

[0134] The channel switching module 1 selects and outputs a signal corresponding to the current selected state from multiple sampling signals in the selected state corresponding to the sampling signal. For example, the channel switching module 1 can output signals to the analog detection module 3 and the digital detection module 2 simultaneously.

[0135] Optionally, the sampling circuit may further include a calculation module 4. The calculation module 4 can be, for example, any module capable of outputting a control signal of high level or low level, such as a single-chip microcomputer, an embedded processor, a programmable logic device, or any other processing unit. Optionally, in addition to the processing unit, it may further include a peripheral circuit unit of the processing unit. The calculation module 4 is connected to the output ends of the analog detection module 3 and the digital detection module 2.

[0136] The calculation module 4 can be a module integrated in the sampling circuit or a module independent of the sampling circuit. The embodiments of the present application do not limit this.

[0137] The analog detection module 3 performs analog-to-digital conversion on the signal actually output by the channel switching module 1 and then outputs it.

[0138] The digital detection module 2 detects whether the magnitude of the signal actually output by the channel switching module 1 is within the preset range. Subsequently, the calculation module 4 can detect whether the sampling signal is valid according to whether the output results of the analog detection module 3 and the digital detection module 2 are within the preset range.

[0139] The calculation module 4 can multiply the output result of the analog detection module 3 by the voltage division ratio of the sampling conditioning module 5 relative to the sampling signal to obtain the monitored voltage of the sampling point.

[0140] It should be understood that the high voltage and low voltage mentioned in the embodiments of the present application are relative concepts, that is, the low voltage is a voltage relatively lower than the high voltage. For example, 5V is a low voltage and 220V is a high voltage.

[0141] In summary, for the sampling circuit provided by the embodiments of the present application, by the channel switching module 1 selecting and outputting a signal corresponding to the current selected state from multiple sampling signals in the selected state corresponding to the sampling signal, one analog detection module 3 and one digital detection module 2 can be used to detect multiple sampling signals, reducing the number of the analog detection module 3 and the digital detection module 2, as well as the number of interfaces required by the calculation module 4.

[0142] Figure 4 This is a schematic flowchart of a detection method for a sampling circuit provided by an embodiment of the present application. The execution subject of this method can be, for example, a processor or a device or electronic device equipped with a processor. In the embodiments of the present application, the processor is taken as an example for illustration. As Figure 4 shown, this method may, for example, include the following steps:

[0143] S401. The processor controls the channel switching module 1 in the sampling circuit to be in the gating state corresponding to a known signal; wherein, the channel switching module 1 is used to output a signal corresponding to the current gating state from multiple received signals;

[0144] Refer to Figure 2 the shown sampling circuit. The processor can, for example, send a gating signal to the channel switching module 1. After the channel switching module 1 decodes the gating signal, it is in the gating state corresponding to the known signal. The channel switching module 1 can select and output a signal corresponding to the current gating state from multiple known signals to transmit the known signal to the analog detection module 3 and the digital detection module 2.

[0145] S402. The processor determines the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal.

[0146] The sampling circuit can output results through the digital detection module 2 and / or the analog detection module 3; wherein, the digital detection module 2 and the analog detection module 3 can be two independent modules or an integrated module. The embodiments of the present application do not limit this.

[0147] In an example, if, in the gating state corresponding to any known signal, the output result of the sampling circuit indicates that the signal actually output by the channel switching module 1 does not match the known signal, it is determined that the sampling circuit has a fault.

[0148] For example, when the sampling circuit has no fault, it should output a signal that matches the magnitude of the known signal. For example, when the known signal is within a preset range, the sampling circuit should output a low-level signal or a voltage value equal to the magnitude of the known signal; when the known signal is outside the preset range, the sampling circuit should output a high-level signal or a voltage value equal to the magnitude of the known signal.

[0149] The processor can preset the correspondence between the gating state and the magnitude of the known signal in the internal storage module. When the processor controls the channel switching module 1 to be in the gating state corresponding to the known signal, the processor can obtain the magnitude of the known signal. The processor can also preset the correspondence between the output result of the sampling circuit and the known signal in the internal storage module.

[0150] The processor can obtain the output result of the sampling circuit. If the output result of the sampling circuit is the same as the known signal in terms of magnitude and signal level status under the selected state, it indicates that the output result of the sampling circuit matches the known signal in magnitude, and it can be determined that the sampling circuit is free of faults. If the output result of the sampling circuit is different from the known signal in terms of magnitude or signal level status under the selected state, it indicates that the output result of the sampling circuit does not match the known signal in magnitude, and it can be determined that the sampling circuit has faults.

[0151] In one example, the sampling circuit may include: a digital detection module 2 and an analog detection module 3; the analog detection module 3 can perform analog-to-digital conversion on the signal actually output by the channel switching module 1; the digital detection module 2 can detect whether the magnitude of the signal actually output by the channel switching module 1 is within a preset range.

[0152] In one example, there may be multiple selected states corresponding to the known signal, and the signals corresponding to the selected states of the known signal may all be within the preset range. If, under any selected state corresponding to the known signal, the output result of the analog detection module 3 and / or the digital detection module 2 indicates that the signal actually output by the channel switching module 1 is outside the preset range, it means that the output result of the analog detection module 3 and / or the digital detection module 2 does not match the known signal in magnitude. At this time, it may be that at least one of the analog detection module 3, the digital detection module 2, and the channel switching module 1 in the sampling circuit has a fault. This method has a unified detection standard and is easy to implement.

[0153] In another example, there may be multiple selected states corresponding to the known signal, and at least one of the selected states corresponds to a signal that is not within the preset range. If, under the selected state corresponding to the known signal outside the preset range, the output result of the analog detection module 3 and / or the digital detection module 2 indicates that the signal actually output by the channel switching module 1 is within the preset range, it means that the output result of the analog detection module 3 and / or the digital detection module 2 does not match the known signal in magnitude. At this time, it may be that at least one of the analog detection module 3, the digital detection module 2, and the channel switching module 1 in the sampling circuit has a fault. If, under the selected state corresponding to the known signal within the preset range, the output result of the analog detection module 3 and / or the digital detection module 2 indicates that the signal actually output by the channel switching module 1 is outside the preset range, it means that the output result of the analog detection module 3 and / or the digital detection module 2 does not match the known signal in magnitude. At this time, it may be that at least one of the analog detection module 3, the digital detection module 2, and the channel switching module 1 in the sampling circuit has a fault. This method is flexible to implement and has better compatibility.

[0154] In another example, the signals corresponding to the gating states of the known signals are all outside the preset range. If, under the gating state corresponding to any known signal, the output result of the analog detection module 3 and / or the digital detection module 2 indicates that the signal actually output by the channel switching module 1 is within the preset range, it means that the output result of the analog detection module 3 and / or the digital detection module 2 does not match the magnitude of the known signal. At this time, it may be that at least one of the analog detection module 3, the digital detection module 2, and the channel switching module 1 in the sampling circuit is faulty. This detection method has a unified standard and is easy to implement.

[0155] In summary, for the detection method of the sampling circuit provided by the embodiments of the present application, by controlling the channel switching module 1 of the sampling circuit to be in the gating state corresponding to the known signal, and according to whether the output result of the sampling circuit under the gating state corresponding to the known signal matches the magnitude of the known signal, the fault condition of the sampling circuit can be determined; after determining that the sampling circuit is fault-free, the sampling circuit is used to monitor the voltage at the preset sampling points of the device under test, and the validity of the sampling signal can be confirmed, thereby improving the accuracy of the protection device validity result confirmed according to the sampling signal and improving the operation safety of the device under test.

[0156] Figure 5 It is a schematic flowchart of another detection method for the sampling circuit provided by the embodiments of the present application. As Figure 5 shown, the method may include the following steps:

[0157] S501. The processor controls the channel switching module 1 in the sampling circuit to be in the gating state corresponding to the known signal; wherein, the channel switching module 1 is used to select and output the signal corresponding to the current gating state from multiple received signals;

[0158] S502. The processor determines the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit under the gating state corresponding to the known signal.

[0159] If after detecting the fault of the sampling circuit, it is confirmed that the sampling circuit is normal, then the validity of the sampling signal can be detected. The sampling signal is obtained by the sampling circuit monitoring the voltage of the sampling object.

[0160] S503. The processor controls the channel switching module 1 in the sampling circuit to be in the gating state corresponding to the sampling signal, so as to output the signal corresponding to the current gating state from multiple received signals; the sampling signal is obtained by the sampling conditioning module 5 of the sampling circuit monitoring the preset sampling points.

[0161] Continue to refer to Figure 2For the sampling circuit shown, the processor can send a strobe signal to channel switching module 1. After decoding the strobe signal, channel switching module 1 is in the strobe state corresponding to the sampling signal. Channel switching module 1 can select and output the signal corresponding to the current strobe state from multiple sampling signals to transmit the sampling signal to analog detection module 3 and digital detection module 2.

[0162] In one example, the processor can periodically control channel switching module 1 to switch the strobe state to periodically select the output of each sampling signal. And in each strobe state, obtain the voltage output by analog detection module 3 and the output result of digital detection module 2.

[0163] S504. Determine the validity of the sampling signal and sampling conditioning module 5 according to the magnitude of the sampling signal and the output results of digital detection module 2 and analog detection module 3 in the strobe state corresponding to the sampling signal.

[0164] Analog detection module 3 can perform analog-to-digital conversion on the signal actually output by channel switching module 1 and then output it; digital detection module 2 can detect whether the magnitude of the signal actually output by the channel switching module is within a preset range and output the detection result.

[0165] For example, the processor can preset the correspondence between the sampling signal and the strobe state in the internal storage module. When the processor controls channel switching module 1 to be in the strobe state corresponding to the sampling signal, the processor can obtain the preset value of the sampling signal. The processor can also preset the correspondence between digital detection module 2 and the known signal in the internal storage module. For example, when the sampling signal is within the working range, digital detection module 2 should output a low-level signal; when the sampling signal is outside the preset range, digital detection module 2 should output a high-level signal.

[0166] The processor can obtain the output results of digital detection module 2 and analog detection module 3 in this strobe state. If the output results of both analog detection module 3 and digital detection module 2 indicate that the sampling signal is within the preset range, or if the output results of both analog detection module 3 and digital detection module 2 indicate that the sampling signal is outside the preset range, it means that the output results of digital detection module 2 and analog detection module 3 match; if one of the output results of analog detection module 3 and digital detection module 2 indicates that the sampling signal is outside the preset range and the other indicates that the sampling signal is within the preset range, it means that the output results of digital detection module 2 and analog detection module 3 do not match.

[0167] If the output results of digital detection module 2 and analog detection module 3 match, determine that the sampling signal and sampling conditioning module 5 are valid; if the output results of digital detection module 2 and analog detection module 3 do not match, determine that sampling conditioning module 5 is faulty.

[0168] In summary, for the detection method of the sampling circuit provided in the embodiments of the present application, by controlling the channel switching module 1 in the sampling circuit to be in the gating state corresponding to the sampling signal, so as to output the signal corresponding to the current gating state from multiple received signals, it is possible to verify the effectiveness of the sampling signal and the sampling conditioning module 5 according to whether the output results of the digital detection module 2 and the analog detection module 3 match; after determining that the sampling signal is effective, the effectiveness of the protection device can be confirmed according to the sampling signal, thereby improving the operation safety of the device under test.

[0169] Figure 6 FIG. is a schematic structural diagram of the third sampling circuit provided in the embodiments of the present application. As Figure 6 shown, on the basis of the Figure 2 embodiment, the sampling circuit will be described in detail. The sampling circuit includes: a channel switching module 1, an analog detection module 3, and a digital detection module 2;

[0170] The digital detection module 2 includes a first comparator 21 and a second comparator 22; the first comparator 21 and the second comparator 22 can both be, for example, any module capable of comparing the signal levels received to output a high-level or low-level signal, and can include, for example, an analog comparator.

[0171] The first input terminal of the first comparator 21 and the first input terminal of the second comparator 22 are connected to the channel switching module 1; the second input terminal of the first comparator 21 is connected to the first reference signal; the second input terminal of the second comparator 22 is connected to the second reference signal; the output terminals of the first comparator 21 and the second comparator 22 are connected as the output terminal of the digital detection module 2; wherein, the first reference signal and the second reference signal are determined based on a preset range.

[0172] For example, the first reference signal corresponds to the upper limit of the preset range, and the second reference signal corresponds to the lower limit of the preset range; or, the first reference signal corresponds to the lower limit of the preset range, and the second reference signal corresponds to the upper limit of the preset range.

[0173] For example, the first input terminal of the first comparator 21 can be the negative input terminal, and the second input terminal of the first comparator 21 can be the positive input terminal; or, the first input terminal of the first comparator 21 can be the positive input terminal, and the second input terminal of the second comparator 22 can be the negative input terminal. The first input terminal of the second comparator 22 can be the negative input terminal, and the second input terminal of the second comparator 22 can be the positive input terminal; or, the first input terminal of the second comparator 22 can be the positive input terminal, and the second input terminal of the second comparator 22 can be the negative input terminal. The embodiments of the present application do not limit this, and can be specifically set according to the actual situation.

[0174] Figure 6 Taking the example that the first input terminal of the first comparator 21 can be the negative input terminal, and the second input terminal of the first comparator 21 can be the positive input terminal; the first input terminal of the second comparator 22 can be the negative input terminal, and the second input terminal of the second comparator 22 can be the positive input terminal for illustration. In this connection mode, when the magnitude of the signal actually output by the channel switching module 1 is higher than the first reference signal, the first comparator 21 outputs a low-level signal; when the magnitude of the signal actually output by the channel switching module 1 is lower than the first reference signal, the first comparator 21 outputs a high-level signal. When the magnitude of the signal actually output by the channel switching module 1 is higher than the first reference signal, the second comparator 22 outputs a low-level signal; when the magnitude of the signal actually output by the channel switching module 1 is lower than the first reference signal, the second comparator 22 outputs a high-level signal.

[0175] The output terminals of the first comparator 21 and the second comparator 22 can respectively serve as the output terminals of the digital detection module 2. The digital detection module 2 can respectively output the output results of the first comparator 21 and the second comparator 22. This method is flexible.

[0176] Furthermore, the first reference signal can be higher than the second reference signal; the output terminal of the first comparator 21 is OR-connected to the output terminal of the second comparator 22 through a NOT gate 25 as the output terminal of the digital detection module 2; at this time, the output signal of the output terminal of the first comparator 21 through the NOT gate 25 is called the output result of the first comparator 21, and the output signal of the output terminal of the second comparator 22 is called the output result of the second comparator 22.

[0177] Alternatively, the first reference signal can be lower than the second reference signal; the output terminal of the second comparator 22 is OR-connected to the output terminal of the first comparator 21 through a NOT gate 25 as the output terminal of the digital detection module 2; at this time, the output signal of the output terminal of the second comparator 22 through the NOT gate 25 is called the output result of the second comparator 22, and the output signal of the output terminal of the first comparator 21 is called the output result of the first comparator 21. In this way, the digital detection module 2 can use one output terminal to output the output results of the first comparator 21 and the second comparator 22 externally, simplifying the detection method and reducing the circuit components connected to the output terminal.

[0178] Through the above connection mode, when the signal actually output by the channel switching module 1 is outside the preset range, the output result of the first comparator 21 or the second comparator 22 is high level, and the output terminal of the digital detection module 2 outputs high level; when the signal actually output by the channel switching module 1 is within the preset range, the output results of both the first comparator 21 and the second comparator 22 are low level, and the output terminal of the digital detection module 2 outputs low level.

[0179] Figure 6Taking the case where the first reference signal is higher than the second reference signal, that is, the first reference signal corresponds to the upper limit of the preset range and the second reference signal corresponds to the lower limit of the preset range; the output end of the first comparator 21 is connected to the output end of the second comparator 22 through a NOT gate 25 by OR connection as an example for illustration.

[0180] Further, the digital detection module 2 further includes: a first isolation module 23 disposed at the output end of the digital detection module 2;

[0181] The first isolation module 23 can be, for example, any module that can implement signal isolation between the input side and the output side, and can include, for example, any one of: an optocoupler, a relay, etc.

[0182] The first isolation module 23 is configured to conduct / turn off based on the output signal of the digital detection module 2, so as to output the output signal of the digital detection module 2 after level conversion. By setting the first isolation module 23, when the sampling circuit is used to monitor the sampling point of high voltage, isolation between the high voltage side and the low voltage side can be achieved, and the influence of the power supply ripple on the low voltage side circuit can be avoided.

[0183] Further, the first isolation module 23 includes: an optocoupler 24;

[0184] One end of the optocoupler 24 receives the output signal of the digital detection module 2, the other end of the optocoupler 24 is grounded, the third end of the optocoupler 24 is connected to the power supply, and the output end of the optocoupler 24 is used to output the processed signal. The optocoupler 24 is small in size and easy to integrate.

[0185] Further, the digital detection module 2 further includes: an output setting module 26;

[0186] The output setting module 26 can be, for example, any module that can set the initial level. For example, it can include a resistor network.

[0187] One end of the output setting module 26 is connected to the output end of the optocoupler 24, the other end of the output setting module 26 is grounded, and the third end of the output setting module 26 outputs the output signal of the optocoupler 24.

[0188] The output setting module 26 is configured to output a known level when the optocoupler 24 is turned off, and to flip the output level when the optocoupler 24 is turned on. For example, when the output setting module 26 outputs a high-level signal when the optocoupler 24 is turned on, it can set the output known level to a low level; or, when the output setting module 26 outputs a low-level signal when the optocoupler 24 is turned on, it can set the output known level to a high level, thereby avoiding being in a certain level when the optocoupler 24 is turned off and improving the stability of the system.

[0189] Further, the output setting module 26 may include, for example, a first resistor R1 and a second resistor R2.

[0190] One end of the first resistor R1 is connected to the output end of the optocoupler 24; the other end of the first resistor R1 and one end of the second resistor R2 are connected to the ground; the other end of the second resistor R2 outputs the output signal of the optocoupler 24.

[0191] Further, the channel switching module 1 may include: a multi-channel selector 11. The multi-channel selector 11 may be, for example, any device that selects one signal from multiple input signals for output. The multi-channel selector 11 includes a plurality of input terminals, one output terminal, and several selection lines. The gating signals received by the several selection lines are used to control which input signal is connected to the output.

[0192] The multi-channel selector 11 is configured to be in a corresponding gating state according to the received gating signal.

[0193] Further, the sampling circuit further includes: a second isolation module 12 connected to the multi-channel selector 11;

[0194] The second isolation module 12 may be, for example, any module that can implement signal isolation between the input side and the output side, and may include, for example: a digital isolation conversion chip.

[0195] The second isolation module 12 is configured to conduct / turn off based on the received gating signal, and output the received gating signal to the multi-channel selector 11 after level conversion.

[0196] By setting the second isolation module 12, when the sampling circuit is used to monitor the sampling point of high voltage, isolation between the high voltage side and the low voltage side can be achieved, and the influence of the power supply ripple on the high voltage side on the low voltage side circuit can be avoided.

[0197] Figure 6 The shown sampling circuit takes the first input terminal of the first comparator 21 and the first input terminal of the second comparator 22 as an example to be connected to the output end of the channel switching module 1; the second input terminal of the first comparator 21 is connected to the first reference signal REF1; the second input terminal of the second comparator 22 is connected to the second reference signal REF2; the output end of the first comparator 21 is connected to the output end of the second comparator 22 through a NOT gate as the output end of the digital detection module 2, and the first reference signal REF1 is higher than the second reference signal REF2 for illustration. Among them, the first reference signal REF1 and the second reference signal REF2 are determined based on a preset range.

[0198] When the sampling circuit is normal, taking the first reference signal REF1 being higher than the second reference signal REF2 as an example, the output results of each module are as follows:

[0199] When the known signal selected and output by the channel switching module 1 is higher than the first reference signal REF1, the output result of the first comparator 21 is a high-level signal, the output result of the second comparator 22 is a low-level signal, and the output result of the digital detection module 2 is a high-level signal.

[0200] When the known signal selected and output by the channel switching module 1 is lower than the second reference signal REF2, the output result of the first comparator 21 is a low-level signal, the output result of the second comparator 22 is a high-level signal, and the output result of the digital detection module 2 is a high-level signal.

[0201] When the known signal selected and output by the channel switching module 1 is higher than the second reference signal REF2 and lower than the first reference signal REF1, the output result of the first comparator 21 is a low-level signal, the output result of the second comparator 22 is a low-level signal, and the output result of the digital detection module 2 is a low-level signal.

[0202] The output result of the analog detection module 3 is equal to the magnitude of the known signal selected and output by the channel switching module 1.

[0203] In summary, for the sampling circuit provided in the embodiment of the present application, the upper limit value and the lower limit value of the preset range can be respectively set through the first comparator 21 and the second comparator 22. Since the signals received by the two comparators are higher than the upper limit value, or lower than the lower limit value, or within the preset range, the two comparators output the results in an OR-connected manner, and it can be determined whether the input signal is within the preset range, which can reduce the number of connection terminals of the subsequent modules.

[0204] Figure 7 It is a schematic flowchart of the detection method for the third sampling circuit provided in the embodiment of the present application. As Figure 7 shown, on the basis of the Figure 4 embodiment, in combination with the Figure 6 sampling circuit shown, the detection method of the sampling circuit will be described in detail. The method includes:

[0205] S701. The processor controls the channel switching module 1 in the sampling circuit to be in the gating state corresponding to the known signal.

[0206] The gating state corresponding to the known signal may include, for example, a first gating state and a second gating state; the channel switching module 1 outputs the signal corresponding to the current gating state from multiple received signals;

[0207] The first gating state corresponds to a first known signal, and the second gating state corresponds to a second known signal;

[0208] In an example, when the channel switching module 1 is in the first gating state, the input channel S8 is turned on, and at this time, the channel switching module 1 selects to output a first known signal; when the channel switching module 1 is in the second gating state, the input channel S16 is turned on, and at this time, the channel switching module 1 selects to output a second known signal.

[0209] In the embodiment of the present application, the sequence of the channel switching module 1 being in the gating state corresponding to the first known signal and the gating state corresponding to the second known signal is not limited. For example, the processor can first control the channel switching module 1 in the sampling circuit to be in the first gating state corresponding to the first known signal, and then, the processor controls the channel switching module 1 in the sampling circuit to be in the second gating state corresponding to the second known signal; or, the processor can first control the channel switching module 1 in the sampling circuit to be in the second gating state corresponding to the second known signal, and then, the processor controls the channel switching module 1 in the sampling circuit to be in the first gating state corresponding to the first known signal.

[0210] Optionally, the first known signal is outside the preset range, and the second known signal is within the preset range; for example, the first known signal can be a voltage higher than the upper limit or a voltage lower than the lower limit; for example, the preset range is 2V - 4V, the first known signal can be 5V, and the second known signal can be 3.3V; or, the first known signal can be 0V, and the second known signal can be 3.3V.

[0211] Or, both the first known signal and the second known signal are outside the preset range and are respectively outside the upper and lower limits of the preset range. The first known signal can be a voltage higher than the upper limit, and the second known signal can be a voltage lower than the lower limit; or, the first known signal can be a voltage lower than the lower limit, and the second known signal can be a voltage higher than the upper limit. For example, if the preset range is 2V - 4V, then the first known signal can be 5V, and the second known signal can be 0V; or, the first known signal is 0V, and the second known signal is 5V.

[0212] In the embodiment of the present application, an example is given with the first known signal being higher than the upper limit voltage and the second known signal being lower than the lower limit voltage. For example, the first known signal is 5V, and the second known signal is 0V.

[0213] S702. When the channel switching module 1 is in the first gating state, the processor determines the output results of the analog detection module 3 and the first comparator 21 of the digital detection module 2; and when the channel switching module 1 is in the second gating state, the processor determines the output results of the analog detection module 3 and the second comparator 22 of the digital detection module 2.

[0214] S703. The processor determines the fault condition of the sampling circuit according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal.

[0215] As an example, in the embodiment of the present application, taking the processor controlling the channel switching module 1 to be in the first gating state and then controlling the channel switching module 1 to switch to the second gating state as an example, it is described how the processor determines the fault condition of the sampling circuit according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal.

[0216] S2. When the channel switching module 1 is in the first gating state, the processor determines whether the output result of the analog detection module 3 matches the first known signal, and whether the output result of the first comparator 21 of the digital detection module 2 matches the first known signal;

[0217] When the channel switching module 1 is in the first gating state, the channel switching module 1 should output a signal equal in magnitude to the first known signal; the output result of the analog detection module 3 after performing analog-to-digital conversion on the actually output signal of the channel switching module 1 should be equal in magnitude to the first known signal; therefore, in the first gating state, if the output result of the analog detection module 3 is equal in magnitude to the first known signal, it means that the output result of the analog detection module 3 matches the first known signal; if the output result of the analog detection module 3 is not equal in magnitude to the first known signal, it means that the output result of the analog detection module 3 does not match the first known signal.

[0218] When the first known signal is higher than the upper limit voltage, the signal actually output by the channel switching module 1 received by the negative input terminal of the first comparator 21 of the digital detection module 2 should be higher than the positive input terminal, the first comparator 21 should output a low-level signal, and the output after passing through the NOT gate 25 at the output terminal of the first comparator 21 should be a high-level signal, that is, the output result of the first comparator 21 should be a high-level signal. Therefore, in the first gating state, if the output result of the first comparator 21 is a high level, it means that the output result of the first comparator 21 matches the first known signal; if the output result of the first comparator 21 is a low level, it means that the output result of the first comparator 21 does not match the first known signal.

[0219] Taking the first known signal being equal to 5V as an example, in the first gating state, if the output result of the analog detection module 3 is equal to 5V, it means that the output result of the analog detection module 3 matches the first known signal; if the output result of the analog detection module 3 is not equal to 5V, it means that the output result of the analog detection module 3 does not match the first known signal; if the output result of the first comparator 21 is at a high level, it means that the output result of the first comparator 21 matches the first known signal; if the output result of the first comparator 21 is at a low level, it means that the output result of the first comparator 21 does not match the first known signal.

[0220] If the output results of the analog detection module 3 and the first comparator 21 in the first gating state both match the first known signal, then step S21 is executed.

[0221] If the output result of the first comparator 21 in the first gating state does not match the first known signal, then step S31 is executed.

[0222] If the output result of the analog detection module 3 in the first gating state does not match the first known signal, and the output result of the first comparator 21 matches the first known signal, then step S41 is executed.

[0223] S21. If the output results of the analog detection module 3 and the first comparator 21 in the first gating state both match the first known signal, then when the channel switching module 1 is in the second gating state, the processor determines whether the output result of the analog detection module 3 matches the second known signal, and whether the output result of the second comparator 22 of the digital detection module matches the second known signal.

[0224] The fact that the output results of the analog detection module 3 and the first comparator 21 in the first gating state both match the first known signal indicates that the detection results of the analog detection module 3 and the first comparator 21 for the signal actually output when the channel switching module 1 is in the first gating state are consistent. It can be considered that the analog detection module 3 and the first comparator 21 are normal, and the channel switching module 1 can output the signal corresponding to the first gating state.

[0225] Next, it is possible to further detect whether the second comparator 22 and the channel switching module 1 are faulty or the location of the fault.

[0226] When the channel switching module 1 is in the second gating state, the channel switching module 1 should output a signal equal in magnitude to the second known signal; the output result after the analog detection module 3 performs analog-to-digital conversion on the actually output signal of the channel switching module 1 should be equal in magnitude to the second known signal; therefore, in the second gating state, if the output result of the analog detection module 3 is equal in magnitude to the second known signal, it indicates that the output result of the analog detection module 3 matches the second known signal; if the output result of the analog detection module 3 is not equal in magnitude to the second known signal, it indicates that the output result of the analog detection module 3 does not match the second known signal.

[0227] When the second known signal is lower than the lower limit voltage, the signal actually output by the channel switching module 1 received by the negative input terminal of the second comparator 22 of the digital detection module 2 should be lower than the positive input terminal, and the second comparator 22 should output a high-level signal, that is, the output result of the second comparator 22 should be a high-level signal. Therefore, in the second gating state, if the output result of the second comparator 22 is a high level, it indicates that the output result of the second comparator 22 matches the second known signal; if the output result of the second comparator 22 is a low level, it indicates that the output result of the second comparator 22 does not match the second known signal.

[0228] Taking the second known signal equal to 0V as an example, in the second gating state, if the output result of the analog detection module 3 is equal to 0V, it indicates that the output result of the analog detection module 3 matches the second known signal; if the output result of the analog detection module 3 is not equal to 0V, it indicates that the output result of the analog detection module 3 does not match the second known signal; if the output result of the second comparator 22 is a high level, it indicates that the output result of the second comparator 22 matches the second known signal; if the output result of the second comparator 22 is a low level, it indicates that the output result of the second comparator 22 does not match the second known signal.

[0229] S22. The processor determines whether there is a fault in the sampling circuit and the fault location according to whether the output results of the analog detection module 3 and / or the second comparator 22 in the second gating state match the second known signal.

[0230] As an example, S22 may specifically include the following steps:

[0231] S221. If the output results of the analog detection module 3 and the second comparator 22 in the second gating state both match the second known signal, the processor determines that there is no fault in the sampling circuit.

[0232] If the output results of the analog detection module 3 and the second comparator 22 in the second gating state both match the second known signal, it indicates that the detection results of the analog detection module 3 and the second comparator 22 for the signal actually output by the channel switching module 1 in the second gating state are consistent. It can be considered that the analog detection module 3 and the second comparator 22 are normal, and the channel switching module 1 can output the signal corresponding to the second gating state, that is, when the channel switching module 1 is in the gating state corresponding to the known signal, it can select and output the signal corresponding to the current gating state from the known signals. It can be determined that the channel switching module 1 is normal. That is, the sampling circuit has no fault.

[0233] S222. If the output result of the analog detection module 3 in the second gating state does not match the second known signal, the processor determines that the channel switching module 1 is faulty.

[0234] After detecting that the analog detection module 3 is normal in step S21, at this time, if the output result of the analog detection module 3 in the second gating state does not match the second known signal, it indicates that the size of the signal actually output by the channel switching module 1 in the second gating state is different from the second known signal, that is, when the channel switching module 1 is in the second gating state, it cannot select and output the signal corresponding to the current gating state from the known signals, and it can be determined that the channel switching module 1 is faulty.

[0235] S223. If the output result of the analog detection module 3 in the second gating state matches the second known signal, and the output result of the second comparator 22 does not match the second known signal, the processor determines that the second comparator 22 is faulty.

[0236] Combined with the detection that the analog detection module 3 is normal in step S21, at this time, if the output result of the analog detection module 3 in the second gating state matches the second known signal, it indicates that the size of the signal actually output by the channel switching module 1 in the second gating state is the same as the second known signal, that is, when the channel switching module 1 is in the second gating state, it can select and output the signal corresponding to the current gating state from the known signals, and it can be determined that the channel switching module 1 is normal. The output result of the second comparator 22 does not match the second known signal, indicating that when the second comparator 22 receives the signal actually output by the channel switching module 1 normally at the negative input terminal, the second comparator 22 cannot output the correct comparison result, and it is determined that the second comparator 22 is faulty.

[0237] S31. If the output result of the first comparator 21 in the first gating state does not match the first known signal, when the channel switching module 1 is in the second gating state, the processor determines whether the output result of the analog detection module 3 matches the second known signal;

[0238] If, in the first gating state, the output result of the first comparator 21 does not match the first known signal, it indicates a failure of the sampling circuit. At this time, it may be that the signal actually output by the channel switching module 1 received by the first comparator 21 is different in magnitude from the first known signal, which may be a failure of the channel switching module 1; or, it may be due to a failure of the first comparator 21 itself. The signal actually output by the channel switching module 1 is the same in magnitude as the known signal, and the first comparator 21 cannot output the correct comparison result; or, both the first comparator 21 and the channel switching module 1 fail. At this time, the first comparator 21 cannot be used to verify whether the analog detection module 3 fails. Therefore, if the output result of the first comparator 21 in the first gating state does not match the first known signal, it may be that at least one of the analog detection module 3, the channel switching module 1, and the first comparator 21 fails.

[0239] Next, it is possible to further detect the fault location in the analog detection module 3, the channel switching module 1, and the first comparator 21.

[0240] S32. The processor determines the fault location of the sampling circuit in the analog detection module 3, the channel switching module 1, and the first comparator 21 according to whether the output result of the analog detection module 3 in the second gating state matches the second known signal.

[0241] As an example, S32 may specifically include the following steps:

[0242] S321. If the output result of the analog detection module 3 in the second gating state matches the second known signal, the processor determines that the first comparator 21 fails.

[0243] If the output result of the analog detection module 3 in the second gating state matches the second known signal, it indicates that the signal actually output when the channel switching module 1 is in the second gating state is the same in magnitude as the second known signal, that is, when the channel switching module 1 is in the second gating state, it can select and output a signal corresponding to the current gating state from the known signals, and it can be determined that the channel switching module 1 is normal and the analog detection module 3 is normal. Therefore, it is determined that the first comparator 21 fails.

[0244] S322. If the output result of the analog detection module 3 in the second gating state does not match the second known signal, the processor determines that the analog detection module 3 and / or the channel switching module 1 fails.

[0245] If the output result of the analog detection module 3 in the second selected state does not match the second known signal, it indicates that the signal actually output by the channel switching module 1 when it is in the second selected state is different in magnitude from the second known signal. That is, when the channel switching module 1 is in the second selected state, it cannot select and output a signal corresponding to the current selected state from the known signals, and it is determined that the channel switching module 1 is faulty; or the signal actually output by the channel switching module 1 is the same in magnitude as the second known signal, but the analog detection module 3 cannot output the correct result after performing analog-to-digital conversion on the signal actually output by the channel switching module 1 that is the same in magnitude as the second known signal, and it is determined that the analog detection module 3 is faulty; or both the channel switching module 1 and the analog detection module 3 are faulty.

[0246] S41. If the output result of the analog detection module 3 in the first selected state does not match the first known signal, and the output result of the first comparator 21 matches the first known signal, then when the channel switching module 1 is in the second selected state, the processor determines whether the output result of the analog detection module 3 matches the second known signal;

[0247] If in the first selected state, the output result of the first comparator 21 does not match the first known signal, and the output result of the first comparator 21 matches the first known signal, it indicates that the first comparator 21 is normal. At this time, it may be that the analog detection module 3 cannot output the correct result after performing analog-to-digital conversion on the signal actually output by the channel switching module 1 that is the same in magnitude as the second known signal, or the signal actually output by the channel switching module 1 is different in magnitude from the second known signal. Therefore, at least one of the analog detection module 3 and the channel switching module 1 may be faulty.

[0248] Next, the fault location in the analog detection module 3 and the channel switching module 1 can be further detected.

[0249] S42. The processor determines the fault location of the sampling circuit in the analog detection module 3 and the channel switching module 1 according to whether the output result of the analog detection module 3 in the second selected state matches the second known signal.

[0250] As an example, S42 may specifically include the following steps:

[0251] S421. If the output result of the analog detection module 3 in the second selected state matches the second known signal, the processor determines that the channel switching module 1 is faulty.

[0252] If the output result of the analog detection module 3 in the second selected state matches the second known signal, it indicates that the signal actually output by the channel switching module 1 in the second selected state is the same size as the second known signal. That is, when the channel switching module 1 is in the second selected state, it can select and output a signal corresponding to the current selected state from the known signals, and it can be determined that the channel switching module 1 is normal and the analog detection module 3 is normal. Therefore, it is determined that in the first selected state, the output result of the analog detection module 3 does not match the first known signal because the signal actually output by the channel switching module 1 in the first selected state is different in size from the first known signal, and it is determined that the channel switching module 1 is faulty.

[0253] S422. If the output result of the analog detection module 3 in the second selected state does not match the second known signal, the processor determines that the analog detection module 3 is faulty.

[0254] If the output result of the analog detection module 3 in the second selected state does not match the second known signal, it indicates that the analog detection module 3 cannot output the correct result for both the signal actually output by the channel switching module 1 in the first selected state and the signal actually output by the channel switching module 1 in the second selected state, and it is determined that the analog detection module 3 is faulty.

[0255] In summary, for the detection method of the sampling circuit provided in the embodiments of the present application, when controlling the channel switching module 1 of the sampling circuit to be in the first selected state corresponding to the first known signal, the output results of the analog detection module 3 and / or the first comparator 21 are detected. Different detection branches are formed according to whether the output results of the analog detection module 3 and / or the first comparator 21 match the first known signal. When controlling the channel switching module 1 of the sampling circuit to be in the second selected state corresponding to the second known signal, in different detection branches, the output results of the analog detection module 3 and / or the second comparator 22 are detected, so as to determine whether the sampling circuit is faulty or the faulty location.

[0256] Figure 8 For the fourth structural schematic diagram of the sampling circuit provided in the embodiments of the present application, as Figure 8 shown, the sampling circuit includes a channel switching module 1, a digital detection module 2, and an analog detection module 3;

[0257] The multi-channel selector 11 of the channel switching module 1 includes a multi-channel selection device U1; the second isolation module 12 of the channel switching module 1 includes a digital isolation conversion chip U2; the multi-channel selection device U1 includes 16 input channels S1 - S16, 4 selection terminals A1 - A4, and 1 output terminal Dout. The digital isolation conversion chip U2 includes four input terminals q1 - q4 and four output terminals a1 - a4;

[0258] The digital detection module 2 includes a first comparator 21, a second comparator 22, an optocoupler 24, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;

[0259] The analog detection module 3 includes an analog-to-digital converter ADC;

[0260] The calculation module 4 includes a microcontroller (Microcontroller Unit, MCU), and the MCU includes 4 output terminals Q1 - Q4, input terminals IN1, IN2;

[0261] The selection terminals A1 - A4 of the multi-channel 1-of-n device U1 are connected to the output terminals a1 - a4 of the digital isolation conversion chip U2; the input terminals q1 - q4 of the digital isolation conversion chip U2 are connected to the output terminals Q1 - Q4 of the calculation module 4; the output terminal Dout of the multi-channel 1-of-n device U1 is connected to the negative input terminal of the first comparator 21, the negative input terminal of the second comparator 22, and the input terminal of the analog-to-digital converter ADC.

[0262] The positive input terminal of the first comparator 21 is connected to one end of the third resistor R3 and one end of the fourth resistor R4; the other end of the third resistor R3 is connected to the power supply VCC; the other end of the fourth resistor R4 is connected to the ground HGND. The positive input terminal of the second comparator 22 is connected to one end of the fifth resistor R5 and one end of the sixth resistor R6; the other end of the fifth resistor R5 is connected to the power supply VCC; the other end of the sixth resistor R6 is connected to the ground HGND.

[0263] The output terminal of the first comparator 21 is provided with a NOT gate 25. The output terminal of the first comparator 21 is connected to the output terminal of the second comparator 22 through the NOT gate 25 and then connected to one end of the optocoupler 24. The other end of the optocoupler 24 is connected to the ground HGND. The third terminal of the optocoupler 24 is connected to the power supply VDD. The output terminal of the optocoupler 24 is connected to one end of the first resistor R1; the other end of the first resistor R1 and one end of the second resistor R2 are connected to the ground GND; the other end of the second resistor R2 is connected to the input terminal IN1 of the calculation module 4.

[0264] The output terminal of the analog-to-digital converter ADC is connected to the input terminal IN2 of the calculation module 4.

[0265] The input channels S1 - S5 of the multi-channel 1-of-n device U1 receive sampling signals UbalPackIsoVolt, LinkPosVolt, MaCtNegVolt, PackVolt, ItmidCtVolt; the input channel S8 of the multi-channel 1-of-n device U1 receives a known signal REF5V of 5V, and the input channel S16 of the multi-channel 1-of-n device U1 receives a known signal REF0V of 0V.

[0266] The third resistor R3 and the fourth resistor R4 are used to provide a first reference signal REF1 to the positive input terminal of the first comparator 21; the fifth resistor R5 and the sixth resistor R6 are used to provide a second reference signal REF2 to the positive input terminal of the second comparator 22. By selecting appropriate resistance values for the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6, the first reference signal REF1 can be set to the upper limit of a preset range, and the second reference signal REF2 can be set to the lower limit of the preset range.

[0267] The output results of the sampling circuit when the multi-channel 1-of-N device U1 selects and outputs signals of different magnitudes will be described below.

[0268] (1) The multi-channel 1-of-N device U1 selects and outputs a known signal higher than the upper limit of the preset range.

[0269] The output terminals Q1-Q4 of the calculation module 4 output a first gating signal, which can be, for example, 0111; the digital isolation and conversion chip U2 performs a level conversion on the first gating signal and then outputs a first gating signal that matches the multi-channel 1-of-N device U1; the multi-channel 1-of-N device U1, according to the first gating signal, conducts the connection between the input channel S8 and the output terminal Dout, and the output terminal Dout should output a known signal REF5V to the negative input terminal of the first comparator 21, the negative input terminal of the second comparator 22, and the input terminal of the analog-to-digital converter ADC; the output result of the first comparator 21 should be a high level; the output result of the second comparator 22 should be a low level, and after performing an OR operation on the output results of the first comparator 21 and the second comparator 22, a high-level signal should be output to one end of the optocoupler 24; the light-emitting diode of the optocoupler 24 conducts; the photosensitive switch of the optocoupler 24 conducts after receiving the light emitted by the light-emitting diode; the power supply VDD should output a high-level signal to the input terminal IN1 of the calculation module 4 through the first resistor R1 and the second resistor R2.

[0270] The analog-to-digital converter ADC performs analog-to-digital conversion on the signal actually output by the multi-channel 1-of-N device U1 and should output a digital signal equal to 5V to the input terminal IN2 of the calculation module 4.

[0271] If the signal received by the input terminal IN1 of the calculation module 4 is a high level, it is confirmed that the output result of the first comparator 21 matches the known signal REF5V. If the signal received by the input terminal IN1 of the calculation module 4 is a low level, the output results of both the first comparator 21 and the second comparator 22 are low levels, and it is confirmed that the output result of the first comparator 21 does not match the known signal REF5V.

[0272] If the magnitude of the signal received at the input terminal IN2 of the calculation module 4 is equal to 5V, it is confirmed that the output result of the analog-to-digital converter ADC matches the known signal REF5V. If the magnitude of the signal received at the input terminal IN2 of the calculation module 4 is not equal to 5V, it is confirmed that the output result of the analog-to-digital converter ADC does not match the known signal REF5V.

[0273] (2) The multi-channel select-1 device U1 selects and outputs a known signal higher than the upper limit of the preset range.

[0274] The output terminals Q1-Q4 of the calculation module 4 output a second strobe signal, which can be, for example, 1111; the digital isolation conversion chip U2 performs a level conversion on the second strobe signal and then outputs a second strobe signal that matches the multi-channel select-1 device U1; the multi-channel select-1 device U1 connects the input channel S16 to the output terminal Dout according to the second strobe signal, and the output terminal Dout should output the known signal REF0V to the negative input terminal of the first comparator 21, the negative input terminal of the second comparator 22, and the input terminal of the analog-to-digital converter ADC; the output result of the first comparator 21 should be a low level; the output result of the second comparator 22 should be a high level, and after the output results of the first comparator 21 and the second comparator 22 are subjected to an OR operation, a high-level signal should be output to one end of the optocoupler 24; the light-emitting diode of the optocoupler 24 conducts; the photosensitive switch of the optocoupler 24 conducts after receiving the light emitted by the light-emitting diode; the power supply VDD should output a high-level signal to the input terminal IN1 of the calculation module 4 through the first resistor R1 and the second resistor R2.

[0275] After the analog-to-digital converter ADC performs analog-to-digital conversion on the signal actually output by the multi-channel select-1 device U1, it should output a digital signal equal to 0V to the input terminal IN2 of the calculation module 4.

[0276] If the signal received at the input terminal IN1 of the calculation module 4 is a high level, it is confirmed that the output result of the second comparator 22 matches the known signal REF0V. If the signal received at the input terminal IN1 of the calculation module 4 is a low level, the output results of both the first comparator 21 and the second comparator 22 are low levels, and it is confirmed that the output result of the second comparator 22 does not match the known signal REF0V.

[0277] If the magnitude of the signal received at the input terminal IN2 of the calculation module 4 is equal to 0V, it is confirmed that the output result of the analog-to-digital converter ADC matches the known signal REF0V. If the magnitude of the signal received at the input terminal IN2 of the calculation module 4 is not equal to 0V, it is confirmed that the output result of the analog-to-digital converter ADC does not match the known signal REF0V.

[0278] (3) The multi-channel 1-out-of-n device U1 selects and outputs a known signal within a preset range. For example, the input channel S15 of the multi-channel 1-out-of-n device U1 receives a known signal REF3.3V of 3.3V. The input channel S15 of the multi-channel 1-out-of-n device U1 receives a known signal REF3.3V of 3.3V, Figure 8 not shown.

[0279] The output terminals Q1 - Q4 of the calculation module 4 output a third gating signal, which can be 1110 for example; the digital isolation and conversion chip U2 performs a level conversion on the third gating signal and then outputs a third gating signal that matches the multi-channel 1-out-of-n device U1; the multi-channel 1-out-of-n device U1 conducts the connection between the input channel S15 and the output terminal Dout according to the third gating signal, and the output terminal Dout should output the known signal REF3.3V to the negative input terminal of the first comparator 21, the negative input terminal of the second comparator 22, and the input terminal of the analog-to-digital converter ADC; the output result of the first comparator 21 should be a low level; the output result of the second comparator 22 should be a low level, and after the output results of the first comparator 21 and the second comparator 22 are ORed, a low-level signal should be output to one end of the optocoupler 24; the light-emitting diode of the optocoupler 24 is turned off; the photosensitive switch of the optocoupler 24 is turned off without receiving the light emitted by the light-emitting diode; the second resistor R2 should output a low-level signal to the input terminal IN1 of the calculation module 4.

[0280] The analog-to-digital converter ADC performs analog-to-digital conversion on the signal actually output by the multi-channel 1-out-of-n device U1 and should output a digital signal equal to 3.3V to the input terminal IN2 of the calculation module 4.

[0281] If the signal received by the input terminal IN1 of the calculation module 4 is a low level, it is confirmed that the output results of the first comparator 21 and the second comparator 22 match the known signal REF3.3V. If the signal received by the input terminal IN1 of the calculation module 4 is a high level, the output result of the first comparator 21 and / or the second comparator 22 is a high level, and it is confirmed that the output results of the first comparator 21 and / or the second comparator 22 do not match the known signal REF3.3V, and the first comparator 21 and / or the second comparator 22 is faulty.

[0282] If the magnitude of the signal received by the input terminal IN2 of the calculation module 4 is equal to 3.3V, it is confirmed that the output result of the analog-to-digital converter ADC matches the known signal REF3.3V. If the magnitude of the signal received by the input terminal IN2 of the calculation module 4 is not equal to 3.3V, it is confirmed that the output result of the analog-to-digital converter ADC does not match the known signal REF3.3V.

[0283] Combined with Figure 8For the sampling circuit shown, in the embodiments of the present application, two known signals outside the preset range can be used to detect faults in the sampling circuit. Taking the use of the known signal REF5V exceeding the upper limit of the preset range and the known signal REF0V lower than the lower limit of the preset range to detect faults in the sampling circuit as an example for illustration. The execution subject of this method can be, for example, Figure 8 the computing module 4 shown below. Taking the computing module 4 as a microcontroller MCU as an example for illustration.

[0284] Figure 9 is a schematic flowchart of the fourth method for detecting a sampling circuit provided by the embodiments of the present application. As Figure 9 shown, this method includes:

[0285] (1) The MCU controls the connection of channel S8. That is, the MCU controls the connection between the input channel S8 and the output terminal Dout of the multi-channel selection 1 device U1 in the sampling circuit to be conducted, so as to select the known signal REF5V with an output of 5V.

[0286] S901. The MCU determines whether the output result ADC_S8 of the analog-to-digital converter ADC is equal to 5V.

[0287] For example, when the signal received at the input terminal IN2 is equal to 5V, the MCU can confirm that the output result ADC_S8 of the analog-to-digital converter ADC is equal to 5V.

[0288] If so, step S902 is executed. If not, step S903 is executed.

[0289] S902. The MCU determines whether the output result Compare1Bool of the first comparator 21 is true (True), that is, whether the output result of the first comparator 21 is a high level.

[0290] For example, when the signal received at the input terminal IN1 is a high level, the MCU can detect that the output result of the first comparator 21 is true.

[0291] For the known signal of 5V, the output result of the first comparator 21 should be a high-level signal, the output result of the second comparator 22 should be a low-level signal, the output result of the first comparator 21 and the output result of the second comparator 22 are ORed and then output a high-level signal, and the input terminal IN1 of the MCU should receive a high-level signal. If the signal received by the MCU at the input terminal IN1 is a low level, it is confirmed that the output of the first comparator 21 does not match the result to be output, and the output of the first comparator 21 is false (False).

[0292] If so, no fault in the sampling circuit is recognized. If not, step S904 is executed.

[0293] S903. The MCU determines whether the output result Compare1Bool of the first comparator 21 is true (i.e., whether the output result of the first comparator 21 is at a high level).

[0294] If so, step S905 is executed; if not, step S904 is executed.

[0295] S904. The MCU identifies an ADC / Mux16 / Compare1 anomaly, i.e., a fault in at least one of the modules: the analog-to-digital converter ADC, the multi-channel selector U1 (Mux16), and the first comparator 21 (Compare1).

[0296] S905. The MCU identifies an ADC anomaly / Mux16 anomaly, i.e., a fault in at least one of the modules: the analog-to-digital converter ADC and the multi-channel selector U1 (Mux16).

[0297] (2) The MCU controls the connection of channel S16. That is, the MCU controls the connection between the input channel S16 and the output terminal Dout of the multi-channel selector U1 in the sampling circuit to be conductive, so as to select the known signal REF0V with an output of 0V.

[0298] If no sampling circuit fault is identified in step (1), step S911 is executed.

[0299] If an ADC / Mux16 / Compare1 anomaly is identified in step (1), step S921 is executed.

[0300] If an ADC anomaly / Mux16 anomaly is identified in step (1), step S931 is executed.

[0301] S911. The MCU determines whether the output result ADC_S16 of the analog-to-digital converter ADC is equal to 0V.

[0302] For example, when the signal received at the input terminal IN2 is equal to 0V, the MCU can confirm that the output result ADC_S16 of the analog-to-digital converter ADC is equal to 0V.

[0303] If so, step S912 is executed; if not, step S913 is executed.

[0304] S912. The MCU determines whether the output result Compare2Bool of the second comparator 22 is true (i.e., whether the output result of the second comparator 22 is at a high level).

[0305] For example, when the signal received at the input terminal IN1 is at a high level, the MCU can detect that the output result of the second comparator 22 is true.

[0306] For a known signal of 0V, the output of the first comparator 21 should be a low-level signal, and the output of the second comparator 22 should be a high-level signal. After ORing the output of the first comparator 21 and the output of the second comparator 22, a high-level signal is output, and the input terminal IN1 of the MCU should receive a high-level signal. If the signal received by the MCU at the input terminal IN1 is at a low level, it is confirmed that the output of the second comparator 22 does not match the expected output, and the output of the second comparator 22 is false.

[0307] If so, execute step S914; if not, execute step S915.

[0308] S913. The MCU identifies a fault in the multi-channel selection 1 device U1 (Mux16).

[0309] S914. The MCU confirms that the system check is OK. That is, the sampling circuit is normal.

[0310] S915. The MCU identifies an abnormality in Compare2, that is, a fault in the second comparator 22.

[0311] S921. The MCU determines whether the output result ADC_S8 of the analog-to-digital converter ADC is equal to 0V.

[0312] If so, execute step S922; if not, execute step S923.

[0313] S922. The MCU identifies an abnormality in Compare1, that is, a fault in the first comparator 21.

[0314] S923. The MCU identifies an ADC abnormality / Mux16 abnormality. That is, at least one module in the analog-to-digital converter ADC and the multi-channel selection 1 device U1 (Mux16) is faulty.

[0315] S931. The MCU determines whether the output result ADC_S8 of the analog-to-digital converter ADC is equal to 0V.

[0316] If so, execute step S932; if not, execute step S933.

[0317] S932. The MCU identifies an abnormality in Mux16, that is, a fault in the multi-channel selection 1 device U1 (Mux16).

[0318] S933. The MCU identifies an ADC abnormality, that is, an abnormality in the analog-to-digital converter ADC.

[0319] Based on the above method, a known signal REF0V of 0V can be used first, and then a known signal REF5V of 5V can be used to detect the sampling circuit. That is, in step (1), the channel S16 can be controlled to conduct first to select the output of the known signal REF0V of 0V, and check whether the analog-to-digital converter ADC, the multi-channel selection device U1 (Mux16), and the second comparator 22 (Compare2) are faulty. Then in step (2), the control channel S8 is selected to conduct. If the system fault is not identified in step (1), it is further determined whether the first comparator 21 is faulty. The specific method can refer to the above steps and will not be elaborated here.

[0320] In the embodiment of the present application, a known signal outside the preset range and a signal within the preset range can also be used to detect the fault of the sampling circuit.

[0321] The following takes the known signal REF5V exceeding the upper limit of the preset range and the signal REF3.3V within the preset range to detect the fault of the sampling circuit as an example. For example, the input channel S15 of the multi-channel selection device U1 receives the known signal REF3.3V of 3.3V.

[0322] As an example, step (2) may further include the following steps:

[0323] (2) The MCU controls the connection of channel S15. That is, the connection between the input channel S15 and the output terminal Dout of the multi-channel selection device U1 in the sampling circuit is controlled to conduct, so as to select the output of the known signal REF3.3V of 3.3V.

[0324] If the sampling circuit fault is not identified in step (1), step S911 is executed.

[0325] If ADC / Mux16 / Compare1 is identified as abnormal in step (1), step S921 is executed.

[0326] If ADC abnormality / Mux16 abnormality is identified in step (1), step S931 is executed.

[0327] S911. The MCU determines whether the output result ADC_S15 of the analog-to-digital converter ADC is equal to 3.3V.

[0328] If so, step S912 is executed; if not, step S913 is executed.

[0329] The S912 MCU determines whether the output result Compare2Bool of the second comparator 22 is false, that is, whether the output result of the second comparator 22 is at a low level. Since the first comparator 21 is not identified as abnormal in step (1), for the known signal REF3.3V, the output result of the first comparator 21 should be at a low level. If the signal received by the processor is at a high level at this time, it is considered that the output result Compare2Bool of the second comparator 22 is true.

[0330] If so, step S914 is executed; if not, step S915 is executed.

[0331] S913 The MCU identifies a fault in the multi-channel select 1 device U1 (Mux16).

[0332] S914 The MCU confirms that the system check is OK. That is, the sampling circuit is normal.

[0333] S915 The MCU identifies a Compare2 exception, that is, a fault in the second comparator 22.

[0334] S921 The MCU determines whether the output result ADC_S15 of the analog-to-digital converter ADC is equal to 3.3V.

[0335] If so, step S922 is executed; if not, step S923 is executed.

[0336] S922 The MCU identifies a Compare1 exception, that is, a fault in the first comparator 21.

[0337] S923 The MCU identifies an ADC exception / Mux16 exception. That is, at least one module of the analog-to-digital converter ADC and the multi-channel select 1 device U1 (Mux16) is faulty.

[0338] S931 The MCU determines whether the output result ADC_S15 of the analog-to-digital converter ADC is equal to 3.3V.

[0339] If so, step S932 is executed; if not, step S933 is executed.

[0340] S932 The MCU identifies a Mux16 exception, that is, a fault in the multi-channel select 1 device U1 (Mux16).

[0341] S933 The MCU identifies an ADC exception, that is, an exception in the analog-to-digital converter ADC.

[0342] The embodiments of the present application can also use a known signal REF0V below the lower limit of the preset range and a signal REF3.3V within the preset range to detect faults in the sampling circuit. For details, please refer to the above method and will not be elaborated here.

[0343] Combined with Figure 3 For the circuit shown, embodiments of the present application can detect multiple sampling signals and the effectiveness of the sampling conditioning module 5.

[0344] Figure 10 It is a schematic flowchart of the detection method for the fifth sampling circuit provided by the embodiments of the present application. As Figure 10 shown, the method includes:

[0345] S1001. If there is no fault in the sampling circuit, the processor controls the channel switching module in the sampling circuit to be in the gating state corresponding to the sampling signal, so as to output a signal corresponding to the current gating state from multiple received signals.

[0346] S1002. The processor can determine the effectiveness of the sampling signal and the sampling conditioning module 5 according to whether the output results of the first comparator 21 and the second comparator 22 of the digital detection module 2 in the gating state are within the preset range of the signal corresponding to the gating state.

[0347] For example, when the output results of both the first comparator 21 and the second comparator 22 are low levels, it indicates that the output results of the first comparator 21 and the second comparator 22 are within the preset range. When the output result of the first comparator 21 or the second comparator 22 is a high level, it indicates that the output result of the first comparator 21 or the second comparator 22 is outside the preset range.

[0348] As an example, step S1002 may specifically include the following steps:

[0349] (1) If the output result of the analog detection module 3 is within the preset range of the signal corresponding to the gating state, determine whether the output results of the first comparator 21 and the second comparator 22 of the digital detection module 2 in the gating state are within the preset range of the signal corresponding to the gating state; according to whether the output results of the first comparator 21 and the second comparator 22 of the digital detection module 2 in the gating state are within the preset range of the signal corresponding to the gating state, determine whether the sampling signal is valid.

[0350] If the output results of both the first comparator 21 and the second comparator 22 of the digital detection module 2 indicate that the signal corresponding to the gating state is within the preset range, determine that the sampling signal and the sampling conditioning module 5 are valid.

[0351] If the output result of the first comparator 21 or the second comparator 22 of the digital detection module 2 indicates that the signal corresponding to the gating state is outside the preset range, determine that the sampling conditioning module 5 is faulty.

[0352] (2) If the output result of the analog detection module 3 is outside the preset range of the signal corresponding to the gated state, then check whether the output results of the first comparator 21 and the second comparator 22 of the digital detection module 2 in the gated state are outside the preset range of the signal corresponding to the gated state; Determine whether the sampling signal and the sampling conditioning module 5 are valid according to whether the output results of the first comparator 21 and the second comparator 22 of the digital detection module 2 in the gated state are outside the preset range of the signal corresponding to the gated state.

[0353] If the output result of the first comparator 21 or the second comparator 22 of the digital detection module 2 indicates that the signal corresponding to the gated state is outside the preset range, then determine that the sampling signal is valid.

[0354] If the output results of both the first comparator 21 and the second comparator 22 of the digital detection module 2 indicate that the signal corresponding to the gated state is within the preset range, then determine that the sampling conditioning module 5 is faulty.

[0355] In summary, for the detection method of the sampling circuit proposed in this application, by controlling the channel switching module 1 in the sampling circuit to be in the gated state corresponding to the sampling signal, selecting and outputting the signal corresponding to the current gated state from multiple sampling signals, and performing verification according to the output results of the digital detection module 2 and the analog detection module 3, the effectiveness of the sampling signal and the sampling conditioning module 5 can be detected.

[0356] Combined with Figure 8 the shown circuit, this embodiment of the application illustrates how to detect the effectiveness of multiple sampling signals and the sampling conditioning module 5.

[0357] Figure 11 is a schematic flowchart of the sixth detection method of the sampling circuit provided by the embodiment of the application. As Figure 11 shown, this method includes:

[0358] S1101. The MCU controls the periodic switching of Sx, and obtains the ADC_Sx voltage and the state of the first comparator 21 or the second comparator 22.

[0359] For example, in the first period, control the input channel S1 of the multi-channel selector U1 to conduct, that is, conduct the connection between the input channel S1 and the output terminal Dout to output the sampling signal UbalPackIsoVolt; In the second period, control the input channel S2 of the multi-channel selector U2 to conduct, that is, conduct the connection between the input channel S2 and the output terminal Dout to output the sampling signal LinkPosVolt; In the third period, control the input channel S3 of the multi-channel selector U2 to conduct, that is, conduct the connection between the input channel S3 and the output terminal Dout to output the sampling signal MaCtNegVolt, etc.

[0360] In each cycle, the analog-to-digital converter ADC performs analog-to-digital conversion on the signal actually output by the multi-channel selector 11, and the MCU obtains the output result of the analog-to-digital converter ADC; for example, when the input channel S1 is turned on, the analog-to-digital converter ADC outputs the voltage ADC_S1; when the input channel S2 is turned on, the analog-to-digital converter ADC outputs the voltage ADC_S2; when the input channel S3 is turned on, the analog-to-digital converter ADC outputs the voltage ADC_S3; the first comparator 21 and the second comparator 22 compare the signal actually output by the multi-channel selector 11, and the MCU obtains the output results of the first comparator 21 and the second comparator 22, that is, the CompareBool state.

[0361] S1102. The MCU determines whether the Vout voltage corresponding to ADC_Sx is within the working range.

[0362] For example, the MCU can convert the voltage ADC_Sx output by the analog-to-digital converter ADC into the monitored voltage of the sampling point. For example, if the sampling signal UbalPackIsoVolt is obtained by dividing the voltage of the first sampling point of the battery system by the voltage divider ratio M1 by the sampling conditioning module, then the MCU can multiply the value of the voltage ADC_Sx by the voltage divider ratio M1 to obtain the monitored voltage of the sampling point. The calculated monitored voltage is compared with the normal working voltage of this sampling point to detect whether the Vout voltage corresponding to ADC_Sx is within the working range of the battery system.

[0363] If so, execute step S1103; if not, execute step S1104.

[0364] S1103. The MCU detects whether the output result of the first comparator 21 or the output result of the second comparator 22 is true.

[0365] If the Vout voltage corresponding to ADC_Sx is within the working range, then at this time, the output results of the first comparator 21 and the second comparator 22 should both indicate that they are within the working range. Refer to Figure 8 the shown circuit. At this time, the voltage received by the first comparator 21 should be less than the first reference voltage REF1, and the output result of the first comparator 21 after passing through the NOT gate 25 should be a low-level signal, that is, Compare1Bool is false (False).

[0366] The voltage received by the second comparator 22 should be greater than the second reference voltage REF2, and the output result of the second comparator 22 should be a low-level signal, that is, Compare2Bool is false (False).

[0367] At this time, the MCU can detect whether the output result of the first comparator 21 or the output result of the second comparator 22 is true according to the signal received at the input terminal IN1.

[0368] If the signal received at the input terminal IN1 of the MCU is a low-level signal, it means that the output results of both the first comparator 21 and the second comparator 22 are false.

[0369] If the signal received at the input terminal IN1 of the MCU is a high-level signal, it means that the output result of the first comparator 21 or the output result of the second comparator 22 is true.

[0370] If so, execute step S1105; if not, execute step S1106.

[0371] S1105. The MCU determines that the sampling conditioning module 5 is faulty.

[0372] If the comparison results output by the first comparator 21 and the second comparator 22 are not both false, it means that the detection results of the first comparator 21 and the second comparator 22 do not match the detection result of the analog-to-digital converter ADC. At this time, it may be that the sampling conditioning module 5 is faulty, and the MCU can record this fault and prompt this fault.

[0373] S1106. The MCU determines that the sampling signal and the sampling conditioning module 5 are valid.

[0374] If the comparison results output by the first comparator 21 and the second comparator 22 are both false, it means that the detection results of the first comparator 21 and the second comparator 22 match the detection result of the analog-to-digital converter ADC. It can be determined that the sampling signal and the sampling conditioning module 5 corresponding to the multi-channel selector U1 in this selected state are valid. The MCU can use the analog-to-digital converter ADC to calculate the monitored voltage of the sampling point for the voltage Voutx output by this sampling signal.

[0375] S1104. The MCU detects whether the comparison results output by the first comparator 21 and the second comparator 22 are both false.

[0376] If the Vout voltage corresponding to ADC_Sx is outside the working range, then at this time, the output result of the first comparator 21 or the output result of the second comparator 22 should indicate being outside the working range. Refer to Figure 8 the shown circuit. If it exceeds the upper limit of the working range, the voltage received by the first comparator 21 should be greater than the first reference voltage REF1, and the output result of the first comparator 21 after passing through the NOT gate 25 should be a high-level signal, that is, Compare1Bool is true (True).

[0377] If it is lower than the lower limit of the working range, the voltage received by the second comparator 22 should be less than the second reference voltage REF2, and the output result of the second comparator 22 should be a high-level signal, that is, Compare2Bool is true (True).

[0378] At this time, the MCU can detect whether the output results of both the first comparator 21 and the second comparator 22 are false according to the signal received at the input terminal IN1.

[0379] If the signal received at the input terminal IN1 of the MCU is a low-level signal, it means that the output results of both the first comparator 21 and the second comparator 22 are false.

[0380] If the signal received at the input terminal IN1 of the MCU is a high-level signal, it means that the output result of either the first comparator 21 or the second comparator 22 is true.

[0381] If so, execute step S1107; if not, execute step S1108.

[0382] S1107. The MCU determines that the sampling conditioning module 5 fails.

[0383] If the output results of both the first comparator 21 and the second comparator 22 are false, it means that the detection results of the first comparator 21 and the second comparator 22 do not match the detection result of the analog-to-digital converter ADC. At this time, it may be that the sampling conditioning module 5 fails, and the MCU can record this failure and prompt this failure.

[0384] S1108. The MCU determines that the sampling signal and the sampling conditioning module 5 are valid.

[0385] If the output results of both the first comparator 21 and the second comparator 22 are not false, it means that the detection results of the first comparator 21 and the second comparator 22 match the detection result of the analog-to-digital converter ADC. It can be determined that the sampling signal and the sampling conditioning module 5 corresponding to the multi-channel selector U1 in this gating state are valid. The MCU can calculate the monitoring voltage of the sampling point using the voltage Voutx output by the analog-to-digital converter ADC for this sampling signal.

[0386] In summary, the embodiment of the present application can detect the validity of the signal corresponding to the gating state by periodically controlling the multi-channel selector to be in different gating states. The MCU can use one analog-to-digital converter ADC to detect the validity of multiple sampling signals, saving the number of devices and the number of MCU interface requirements. By obtaining whether the output voltage of the analog comparator ADC matches the states of the first comparator 21 and the second comparator 22, the validity of the sampling signal and the sampling conditioning module 5 can be detected.

[0387] An embodiment of the present application further provides a detection device, including a sampling circuit and a detection device. This detection device can be applied to a battery system to monitor the voltage at preset sampling points of the battery system, or can also be applied to a power supply system at any other preset sampling point for voltage detection.

[0388] Figure 12 It is a schematic structural diagram of a power supply system provided by an embodiment of the present application. As Figure 12 shown, it includes a detection device and a battery system.

[0389] The battery system includes a battery module, a positive fuse, a negative fuse, a pre-charge resistor R, a pre-charge contactor, a main positive contactor, a negative contactor, a shunt resistor, etc. The battery module may include a plurality of series-connected and parallel-connected battery packs. Figure 12 Taking the battery module including battery pack Pack1 and battery pack Pack2 connected in series as an example for illustration.

[0390] The positive electrode of the battery module is connected to one end of the pre-charge resistor R and one end of the main positive contactor through the positive fuse; the other end of the pre-charge resistor R is connected to one end of the pre-charge contactor; after the other end of the pre-charge contactor is connected to the other end of the main positive contactor, it can be connected to one end of the load; the negative electrode of the battery module is connected to one end of the negative contactor through the shunt resistor and the negative fuse, and the other end of the negative contactor can be connected to the other end of the load. The negative electrode of the battery module is connected to the ground HGND.

[0391] When the battery system is powered on, it first enters the pre-charge stage. The pre-charge contactor is closed, the main positive contactor is open, and the negative contactor is closed. The battery module, the positive fuse, the pre-charge resistor, the pre-charge contactor, the negative contactor, the negative fuse, and the shunt resistor form a power supply loop.

[0392] After the pre-charge is completed, the battery system enters the normal power supply stage. The pre-charge contactor is open, the main positive contactor is closed, and the negative contactor is closed. The battery module, the positive fuse, the main positive contactor, the negative contactor, the negative fuse, and the shunt (Shunt) form a power supply loop.

[0393] The battery system can set six preset sampling points C1 - C6, where the sampling point C1 is located at the positive electrode of the battery module; the sampling point C2 is located between the positive fuse and one end of the main positive contactor; the sampling point C3 is located at the other end of the main positive contactor; the sampling point C4 is located between the shunt and the negative fuse; the sampling point C5 is located between the negative fuse and one end of the negative contactor; the sampling point C6 is located at the other end of the negative contactor. The embodiment of the present application does not limit the number and setting positions of the sampling points.

[0394] The detection device includes a sampling circuit and a detection device. The detection device can be, for example, a computing module 4.

[0395] The sampling circuit includes: a channel switching module 1, an analog detection module 3, a digital detection module 2, and a sampling conditioning module 5.

[0396] The sampling conditioning module 5 is connected to the channel switching module 1, and is used for monitoring a preset sampling point to obtain a plurality of sampling signals, and outputting the plurality of sampling signals to the channel switching module 1;

[0397] The channel switching module 1 is used for selecting and outputting a signal corresponding to the current gating state from the plurality of sampling signals in the gating state corresponding to the sampling signal.

[0398] The digital detection module 2 is used for detecting whether the magnitude of the signal actually output by the channel switching module 1 is within a preset range and outputting a detection result.

[0399] The analog detection module 3 is used for performing analog-to-digital conversion on the signal actually output by the channel switching module 1 and then outputting it.

[0400] The calculation module 4 determines whether the sampling signal is valid according to the output results of the digital detection module 2 and the analog detection module 3.

[0401] Figure 13 It is a schematic structural diagram of a detection device for a sampling circuit provided by an embodiment of the present application. As Figure 13 shown, the device may include a control module 1301 and a determination module 1302.

[0402] The control module 1301 is used for controlling the channel switching module 1 in the sampling circuit to be in the gating state corresponding to a known signal; wherein, the channel switching module 1 is used for selecting and outputting a signal corresponding to the current gating state from a plurality of received signals;

[0403] The determination module 1302 is used for determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal.

[0404] A possible implementation manner, the determination module 1302 is specifically used for determining that the sampling circuit has a fault if, in the gating state corresponding to any known signal, the output result of the sampling circuit indicates that the signal actually output by the channel switching module 1 does not match the known signal.

[0405] A possible implementation manner, the sampling circuit includes a digital detection module 2 and an analog detection module 3;

[0406] The analog detection module 3 is used for performing analog-to-digital conversion on the signal actually output by the channel switching module 1; the digital detection module 2 is used for detecting whether the magnitude of the signal actually output by the channel switching module 1 is within a preset range.

[0407] A possible implementation manner, the gating states corresponding to the known signals include a first gating state and a second gating state;

[0408] The first gating state corresponds to a first known signal, and the second gating state corresponds to a second known signal.

[0409] A possible implementation manner, the first known signal is outside the preset range, and the second known signal is within the preset range;

[0410] Or, both the first known signal and the second known signal are outside the preset range, and are respectively outside the upper limit and the lower limit of the preset range.

[0411] A possible implementation manner, the determining module 1302 is specifically configured to determine the output results of the analog detection module 3 and the first comparator 21 of the digital detection module 2 when the channel switching module 1 is in the first gating state;

[0412] And, when the channel switching module 1 is in the second gating state, determine the output results of the analog detection module 3 and the second comparator 22 of the digital detection module 2;

[0413] Determine the fault condition of the sampling circuit according to the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal.

[0414] A possible implementation manner, the determining module 1302 is specifically configured to if the output results of the analog detection module 3 and the first comparator 21 of the digital detection module 2 in the first gating state both match the first known signal;

[0415] And, if the output results of the analog detection module 3 and the second comparator 22 in the second gating state both match the second known signal, determine that the sampling circuit has no fault.

[0416] A possible implementation manner, the determining module 1302 is specifically configured to if the output results of the analog detection module 3 and the first comparator 21 of the digital detection module 2 in the first gating state both match the first known signal;

[0417] And, if the output result of the analog detection module 3 in the second gating state does not match the second known signal, determine that the channel switching module 1 is faulty.

[0418] A possible implementation manner, the determining module 1302 is specifically configured to if the output results of the analog detection module 3 and the first comparator 21 of the digital detection module 2 in the first gating state both match the first known signal;

[0419] Moreover, if the output result of the analog detection module 3 in the second gating state matches the second known signal, and the output result of the second comparator 22 does not match the second known signal, it is determined that the second comparator 22 is faulty.

[0420] A possible implementation, the determination module 1302 is specifically configured to, if the output result of the first comparator 21 in the first gating state does not match the first known signal;

[0421] Moreover, if the output result of the analog detection module 3 in the second gating state matches the second known signal, it is determined that the first comparator 21 is faulty.

[0422] A possible implementation, the determination module 1302 is specifically configured to, if the output result of the first comparator 21 in the first gating state does not match the first known signal;

[0423] Moreover, if the output result of the analog detection module 3 in the second gating state does not match the second known signal, it is determined that the analog detection module 3 and / or the channel switching module 1 is faulty.

[0424] A possible implementation, the determination module 1302 is specifically configured to, if the output result of the analog detection module 3 in the first gating state does not match the first known signal, and the output result of the first comparator 21 matches the first known signal;

[0425] Moreover, if the output result of the analog detection module 3 in the second gating state matches the second known signal, it is determined that the channel switching module 1 is faulty.

[0426] A possible implementation, the determination module 1302 is specifically configured to, if the output result of the analog detection module 3 in the first gating state does not match the first known signal, and the output result of the first comparator 21 matches the first known signal;

[0427] Moreover, if the output result of the analog detection module 3 in the second gating state does not match the second known signal, it is determined that the analog detection module 3 is faulty.

[0428] A possible implementation, the determination module 1302 is configured to determine the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal. After that, the determination module 1302 is further configured to, if the sampling circuit is not faulty, control the channel switching module 1 in the sampling circuit to be in the gating state corresponding to the sampling signal, so as to output the signal corresponding to the current gating state from multiple received signals; the sampling signal is obtained by monitoring preset sampling points through the sampling conditioning module 5 of the sampling circuit;

[0429] Determine the validity of the sampling signal and the sampling conditioning module 5 according to the magnitude of the sampling signal and the output results of the digital detection module 2 and the analog detection module 3 in the corresponding strobe state.

[0430] A possible implementation, the determination module 1302 is specifically configured to determine that the sampling signal and the sampling conditioning module 5 are valid if the output result of the analog detection module 3 is within the preset range of the signal corresponding to the strobe state, and the output results of the first comparator 21 and the second comparator 22 of the digital detection module 2 both indicate that the signal corresponding to the strobe state is within the preset range.

[0431] A possible implementation, the determination module 1302 is specifically configured to determine that the sampling conditioning module 5 is faulty if the output result of the analog detection module 3 is within the preset range of the signal corresponding to the strobe state, and the output result of either the first comparator 21 or the second comparator 22 of the digital detection module 2 indicates that the signal corresponding to the strobe state is outside the preset range.

[0432] A possible implementation, the determination module 1302 is specifically configured to determine that the sampling signal is valid if the output result of the analog detection module 3 is outside the preset range of the signal corresponding to the strobe state, and the output result of either the first comparator 21 or the second comparator 22 of the digital detection module 2 indicates that the signal corresponding to the strobe state is outside the preset range.

[0433] A possible implementation, the determination module 1302 is specifically configured to determine that the sampling circuit is faulty if the output result of the analog detection module 3 is outside the preset range of the signal corresponding to the strobe state, and the output results of the first comparator 21 and the second comparator 22 of the digital detection module 2 both indicate that the signal corresponding to the strobe state is within the preset range.

[0434] The detection device of the sampling circuit provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here in this embodiment.

[0435] This application also provides a computer-readable storage medium, which may include: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks or optical discs that can store program codes. Specifically, the computer-readable storage medium stores program instructions for implementing the actions of the above method embodiments.

[0436] The embodiment of this application also provides a traffic device, including a power supply system.

[0437] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed by the present invention. It is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A detection method for a sampling circuit, characterized in that Including: Controlling the channel switching module (1) in the sampling circuit to be in the gating state corresponding to the known signal; wherein, the channel switching module (1) is used to output the signal corresponding to the current gating state from multiple received signals; Determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal.

2. The method according to claim 1, characterized in that The determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal specifically includes: If, in the gating state corresponding to any known signal, the output result of the sampling circuit indicates that the signal actually output by the channel switching module (1) does not match the known signal, it is determined that the sampling circuit has a fault.

3. The method according to claim 2, wherein The sampling circuit includes a digital detection module (2) and an analog detection module (3); The analog detection module (3) is used to perform analog-to-digital conversion on the signal actually output by the channel switching module (1); the digital detection module (2) is used to detect whether the magnitude of the signal actually output by the channel switching module (1) is within a preset range.

4. The method according to claim 3, characterized in that, The gating state corresponding to the known signal includes a first gating state and a second gating state; The first gating state corresponds to a first known signal, and the second gating state corresponds to a second known signal.

5. The method according to claim 4, wherein The first known signal is outside the preset range, and the second known signal is within the preset range; Or, both the first known signal and the second known signal are outside the preset range and are respectively outside the upper and lower limits of the preset range.

6. The method according to claim 4, wherein The determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal specifically includes: When the channel switching module (1) is in the first gating state, determining the output result of the first comparator (21) of the analog detection module (3) and the digital detection module (2); And, when the channel switching module (1) is in the second gating state, determining the output result of the second comparator (22) of the analog detection module (3) and the digital detection module (2); Determining the fault condition of the sampling circuit according to the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal.

7. The method according to claim 6, wherein The determining according to the matching relationship between the output result in the first gating state and the first known signal and the matching relationship between the output result in the second gating state and the second known signal specifically includes: If the output result of the first comparator (21) of the analog detection module (3) and the digital detection module (2) in the first gating state all match the first known signal; And, the output result of the analog detection module (3) and the second comparator (22) in the second gating state all match the second known signal, it is determined that the sampling circuit has no fault.

8. The method according to claim 6, characterized in that, Specifically, it includes: according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal. If the output results of the analog detection module (3) and the first comparator (21) of the digital detection module (2) in the first gating state both match the first known signal; and the output result of the analog detection module (3) in the second gating state does not match the second known signal, it is determined that the channel switching module (1) is faulty.

9. The method according to claim 6, wherein Specifically, it includes: according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal. If the output results of the analog detection module (3) and the first comparator (21) of the digital detection module (2) in the first gating state both match the first known signal; and the output result of the analog detection module (3) in the second gating state matches the second known signal, and the output result of the second comparator (22) does not match the second known signal, it is determined that the second comparator (22) is faulty.

10. The method according to claim 6, characterized in that, Specifically, it includes: according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal. If the output result of the first comparator (21) in the first gating state does not match the first known signal; and the output result of the analog detection module (3) in the second gating state matches the second known signal, it is determined that the first comparator (21) is faulty.

11. The method according to claim 6, characterized in that, Specifically, it includes: according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal. If the output result of the first comparator (21) in the first gating state does not match the first known signal; and the output result of the analog detection module (3) in the second gating state does not match the second known signal, it is determined that the analog detection module (3) and / or the channel switching module (1) is faulty.

12. The method according to claim 6, wherein Specifically, it includes: according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal. If the output result of the analog detection module (3) in the first gating state does not match the first known signal, and the output result of the first comparator (21) matches the first known signal; and the output result of the analog detection module (3) in the second gating state matches the second known signal, it is determined that the channel switching module (1) is faulty.

13. The method according to claim 6, wherein Specifically, it includes: according to the matching relationship between the output result in the first gating state and the first known signal, and the matching relationship between the output result in the second gating state and the second known signal. If the output result of the analog detection module (3) in the first gating state does not match the first known signal, and the output result of the first comparator (21) matches the first known signal; Moreover, if the output result of the analog detection module (3) in the second gating state does not match the second known signal, it is determined that the analog detection module (3) has a fault.

14. The method according to any one of claims 3 to 13, characterized in that, After determining the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gating state corresponding to the known signal, the method further includes: If the sampling circuit has no fault, control the channel switching module (1) in the sampling circuit to be in the gating state corresponding to the sampling signal, so as to output a signal corresponding to the current gating state from multiple received signals; the sampling signal is obtained by the sampling conditioning module (5) of the sampling circuit monitoring a preset sampling point; Determine the effectiveness of the sampling signal and the sampling conditioning module (5) according to the magnitude of the sampling signal and the output results of the digital detection module (2) and the analog detection module (3) in the gating state corresponding to the sampling signal.

15. The method according to claim 14, characterized in that, The determining the effectiveness of the sampling signal and the sampling conditioning module (5) according to the magnitude of the sampling signal and the output results of the digital detection module (2) and the analog detection module (3) in the gating state corresponding to the sampling signal specifically includes: If the output result of the analog detection module (3) is within the preset range of the signal corresponding to the gating state, and the output results of the first comparator (21) and the second comparator (22) of the digital detection module (2) both indicate that the signal corresponding to the gating state is within the preset range, it is determined that the sampling signal and the sampling conditioning module (5) are effective.

16. The method according to claim 14, characterized in that, The determining the effectiveness of the sampling signal and the sampling conditioning module (5) according to the magnitude of the sampling signal and the output results of the digital detection module (2) and the analog detection module (3) in the gating state corresponding to the sampling signal specifically includes: If the output result of the analog detection module (3) is within the preset range of the signal corresponding to the gating state, and the output result of either the first comparator (21) or the second comparator (22) of the digital detection module (2) indicates that the signal corresponding to the gating state is outside the preset range, it is determined that the sampling conditioning module (5) has a fault.

17. The method according to claim 14, characterized in that, The determining the effectiveness of the sampling signal and the sampling conditioning module (5) according to the magnitude of the sampling signal and the output results of the digital detection module (2) and the analog detection module (3) in the gating state corresponding to the sampling signal specifically includes: If the output result of the analog detection module (3) is outside the preset range of the signal corresponding to the gating state, and the output result of either the first comparator (21) or the second comparator (22) of the digital detection module (2) indicates that the signal corresponding to the gating state is outside the preset range, it is determined that the sampling signal is effective.

18. The method according to claim 14, wherein Determine the validity of the sampling signal and the sampling conditioning module (5) according to the magnitude of the sampling signal and the output results of the digital detection module (2) and the analog detection module (3) in the corresponding gating state, specifically including: If the output result of the analog detection module (3) is outside the preset range of the signal corresponding to the gating state, and the output results of the first comparator (21) and the second comparator (22) of the digital detection module (2) both indicate that the signal corresponding to the gating state is within the preset range, it is determined that the sampling circuit has a fault.

19. A sampling circuit, characterized in that, Including: A channel switching module (1) for outputting a signal corresponding to the current gating state from multiple received signals in the gating state corresponding to a known signal; An analog detection module (3) connected to the channel switching module (1) for performing analog-to-digital conversion on the signal actually output by the channel switching module (1); A digital detection module (2) connected to the channel switching module (1) for detecting whether the magnitude of the signal actually output by the channel switching module (1) is within a preset range.

20. The sampling circuit according to claim 19, wherein The digital detection module (2) includes: a first comparator (21) and a second comparator (22); The first input terminal of the first comparator (21) and the first input terminal of the second comparator (22) are connected to the channel switching module (1); the second input terminal of the first comparator (21) is connected to a first reference signal; the second input terminal of the second comparator (22) is connected to a second reference signal; the output terminals of the first comparator (21) and the second comparator (22) are connected as the output terminal of the digital detection module (2); wherein, the first reference signal and the second reference signal are determined based on the preset range.

21. The sampling circuit according to claim 20, wherein The first reference signal is higher than the second reference signal; the output terminal of the first comparator (21) is OR-connected to the output terminal of the second comparator (22) through a NOT gate (25) as the output terminal of the digital detection module (2); Or, the first reference signal is lower than the second reference signal; the output terminal of the second comparator (22) is OR-connected to the output terminal of the first comparator (21) through a NOT gate (25) as the output terminal of the digital detection module (2).

22. The sampling circuit according to claim 19, wherein The digital detection module (2) further includes: a first isolation module (23) provided at the output terminal of the digital detection module (2); The first isolation module (23) is used to conduct / disconnect based on the output signal of the digital detection module (2) to output the output signal of the digital detection module (2) after level conversion.

23. The sampling circuit according to claim 22, characterized in that, The first isolation module (23) includes: an optocoupler (24); One end of the optocoupler (24) receives the output signal of the digital detection module (2), the other end of the optocoupler (24) is grounded, the third end of the optocoupler (24) is connected to a power supply, and the output terminal of the optocoupler (24) is used to output the processed signal.

24. The sampling circuit according to claim 23, wherein The digital detection module (2) further includes: an output setting module (26); One end of the output setting module (26) is connected to the output end of the optocoupler (24), the other end of the output setting module (26) is grounded, and the third end of the output setting module (26) outputs the output signal of the optocoupler (24); The output setting module (26) is configured to output a known level when the optocoupler (24) is disconnected, and invert the output level when the optocoupler (24) is conducting.

25. The sampling circuit according to claim 24, wherein The output setting module (26) includes: a first resistor and a second resistor; One end of the first resistor is connected to the output end of the optocoupler (24); the other end of the first resistor and one end of the second resistor are connected to the ground; the other end of the second resistor outputs the output signal of the optocoupler (24).

26. The sampling circuit according to claim 19, wherein The channel switching module (1) includes: a multi-channel selector (11); The multi-channel selector (11) is configured to be in a corresponding gated state according to the received gating signal.

27. The sampling circuit according to claim 26, wherein The sampling circuit further includes: a second isolation module (12) connected to the multi-channel selector (11); The second isolation module (12) is configured to conduct / turn off based on the received gating signal, and output the received gating signal to the multi-channel selector (11) after level conversion.

28. The sampling circuit according to any one of claims 19 to 27, characterized in that, The sampling circuit further includes: a sampling conditioning module (5); The sampling conditioning module (5) is connected to the channel switching module (1), and is configured to monitor a preset sampling point to obtain a plurality of sampling signals, and output the plurality of sampling signals to the channel switching module (1); The channel switching module (1) is further configured to select and output a signal corresponding to the current gated state from the plurality of sampling signals in the gated state corresponding to the sampling signal.

29. A detection device for a sampling circuit, characterized in that, Includes: A control module, configured to control the channel switching module (1) in the sampling circuit to be in a gated state corresponding to a known signal; wherein, the channel switching module (1) is configured to output a signal corresponding to the current gated state from a plurality of received signals; A determination module, configured to determine the fault condition of the sampling circuit according to the magnitude of the known signal and the output result of the sampling circuit in the gated state corresponding to the known signal.

30. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the method according to any one of claims 1 to 18.

31. A detection device, characterized in that, Includes the sampling circuit according to any one of claims 19 to 28, and the detection device according to claim 29.

32. A power supply system, characterized in that, Includes: The detection device according to claim 31, and a battery system.

33. A traffic device, characterized in that, Includes the power supply system according to claim 32.

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