Method of operating memory controller, memory device, and method of operating memory device

Abstract

The invention provides a method of operating a memory controller, a memory device, and a method of operating the memory device. The method includes selecting, by the memory controller, a representative page stored in a first group in a first region included in a non-volatile memory device; receiving, by the memory controller, the representative page from the non-volatile memory device; performing, by the storage controller, an error detection operation that determines an error number of bits of the representative page; based on determining that the number of error bits of the representative page exceeds a threshold, performing, by the memory controller, an external write-back operation for each page in the first group to store it to a second region included in the non-volatile memory device; and based on determining that the number of error bits of the representative page is less than or equal to the threshold value, performing, by the storage controller, an internal write-back operation for each page in the first group and storing the same to the second region.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor memories, and more particularly, to methods of operating a storage controller, a storage device, and a method of operating a storage device. Background Art

[0002] Semiconductor memories may include volatile storage devices and flash memory devices such as static random access memories (SRAMs), dynamic RAMs (DRAMs), etc., in which data stored therein disappears when their power supply is cut off; and non-volatile storage devices such as phase change RAMs (PRAMs), magnetoresistive RAMs (MRAMs), resistive RAMs (RRAMs), ferroelectric RAMs (FRAMs), etc., in which data stored therein is maintained even when their power supply is cut off.

[0003] Data movement may occur inside non-volatile storage devices. Data movement is required if data stored in a single-level cell (SLC) region is migrated to a three-level cell (TLC) region. Data movement is required in garbage collection operations. In one or more embodiments, data movement is required in reclaim operations. In these operations, data may be moved from a first storage block of a non-volatile storage device to a second storage block of the non-volatile storage device. When data stored in a non-volatile storage device is read, the data may include errors according to a reliability level. To correct the errors, the non-volatile storage device may send the data to a storage controller, and the storage controller may correct the errors by performing an error detection operation or an error correction operation. However, it takes time to output data from the non-volatile storage device to the storage controller and to send the corrected data from the storage controller to the non-volatile storage device, thereby degrading performance. Summary of the Invention

[0004] Embodiments of the present disclosure provide a method of operating a storage controller, a storage device, and a method of controlling the storage device.

[0005] According to one aspect of the present disclosure, a method of operating a storage controller and a storage device including a non-volatile storage device includes: selecting, by the storage controller, a representative page in a first page group stored in a first area included in the non-volatile storage device; receiving, by the storage controller, the representative page from the non-volatile storage device; performing, by the storage controller, an error detection operation to determine the number of error bits of the representative page; based on determining that the number of error bits of the representative page exceeds a threshold, performing, by the storage controller, an external copy-back operation for each of a plurality of pages in the first page group and storing it in a second area included in the non-volatile storage device; and based on determining that the number of error bits of the representative page is less than or equal to the threshold, performing, by the storage controller, an internal copy-back operation for each of the plurality of pages in the first page group and storing it in the second area.

[0006] According to one aspect of the present disclosure, a storage device includes: a non-volatile storage device including a first area and a second area; and a storage controller configured to perform a migration operation of moving a page in a first page group stored in the first area to the second area, wherein, to perform the migration operation, the storage controller is configured to select a representative page in the first page group, perform an error detection operation to determine the number of error bits of the representative page in the first page group, based on determining that the number of error bits of the representative page exceeds a threshold, perform an external copy-back operation for each of a plurality of pages in the first page group and store it in the second area, and based on determining that the number of error bits of the representative page is less than or equal to the threshold, perform an internal copy-back operation for each of the plurality of pages in the first page group and store it in the second area.

[0007] According to one aspect of the present disclosure, a method of operating a storage controller configured to control a non-volatile storage device including a first area and a second area includes: selecting a representative page in a first page group stored in the first area included in the non-volatile storage device; receiving the representative page from the non-volatile storage device; performing an error detection operation to determine the number of error bits of the representative page; based on determining that the number of error bits of the representative page exceeds a threshold, performing an external copy-back operation for each of a plurality of pages in the first page group and storing it in the second area included in the non-volatile storage device; and based on determining that the number of error bits of the representative page is less than or equal to the threshold, performing an internal copy-back operation for each of the plurality of pages in the first page group and storing it in the second area. Description of the Drawings

[0008] Embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a storage system according to one or more embodiments;

[0010] Figure 2 is according to one or more embodiments Figure 1 a more detailed block diagram of a non-volatile storage device;

[0011] Figure 3 is according to one or more embodiments Figure 2 an equivalent circuit diagram of an example of a storage block;

[0012] Figure 4 is according to one or more embodiments Figure 1 a diagram of an example of the operation of a storage device;

[0013] Figure 5A and Figure 5B is a diagram of an example of a write-back operation of a storage device according to one or more embodiments;

[0014] Figure 6 is according to one or more embodiments Figure 1 a flowchart of an example of the operation of a storage device;

[0015] Figure 7 is a flowchart of an example of the operation of a storage device according to one or more embodiments;

[0016] Figure 8 is a flowchart of an example of the operation of a storage device according to one or more embodiments;

[0017] Figure 9A and Figure 9B is a flowchart of an example of the operation of a storage device according to one or more embodiments;

[0018] Figure 10A and Figure 10B is a timing diagram of an example of the operation of a storage device according to one or more embodiments;

[0019] Figure 11 is a diagram of an example of the operation of a storage device according to one or more embodiments;

[0020] Figure 12 is a block diagram of a storage system according to one or more embodiments;

[0021] Figure 13 is according to one or more embodiments Figure 12 a flowchart of an example of the operation of a storage device; and

[0022] Figure 14 is a block diagram of a non-volatile memory device according to one or more embodiments. Detailed implementation

[0023] Hereinafter, embodiments will be described clearly and in detail so that those of ordinary skill in the art can easily implement the embodiments of the present disclosure.

[0024] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Modifications and variations are possible in light of the above disclosure, or may be acquired from practice of the implementations. Additionally, one or more features or components of one embodiment may be incorporated into another embodiment (or one or more features of another embodiment) or combined with another embodiment (or one or more features of another embodiment). Additionally, in the flowcharts and descriptions of operations provided below, it should be understood that one or more operations may be omitted, one or more operations may be added, one or more operations may be performed simultaneously (at least in part), and the order of one or more operations may be swapped.

[0025] It will be clear that the systems and / or methods described herein may be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual specific control hardware or software code for implementing these systems and / or methods does not limit these implementations. Thus, the operations and behaviors of the systems and / or methods are described herein without reference to specific software code—it should be understood that software and hardware can be designed based on the description herein to implement these systems and / or methods.

[0026] Even if specific combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and / or not disclosed in the specification. Although each of the dependent claims listed below may directly depend on only one claim, the disclosure of possible implementations includes each dependent claim in combination with every other claim in the claim set.

[0027] Unless explicitly described as such, any element, act, or instruction used herein should not be construed as critical or essential. In one or more embodiments, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." In cases where only one item is involved, the term "one" or similar language is used. In one or more embodiments, as used herein, the terms "have", "has", "contain", "include", "including", etc. are intended to be open-ended terms. Additionally, unless otherwise explicitly stated, the phrase "based on" is intended to mean "at least partially based on." Further, expressions such as "at least one of [A] and [B]" or "at least one of [A] or [B]" will be understood to include only A, only B, or both A and B.

[0028] References throughout this specification to "one embodiment", "an embodiment", or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment", "in an embodiment", and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0029] Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner. Given the description herein, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not exist in all embodiments of the present disclosure.

[0030] Figure 1 is a block diagram of a storage system 1000 according to one or more embodiments.

[0031] Referring to Figure 1 , the storage system 1000 may include a host device 10 and a storage device 1100. In one or more embodiments, the storage device 1100 may include a storage controller 1200 and a non-volatile storage device (NVM) 1300. According to one or more embodiments, the host device 10 may include a host controller 11 and a host memory 12. The host memory 12 may be used as a buffer memory for temporarily storing data to be sent to or from the storage device 1100.

[0032] The storage device 1100 may include a storage medium for storing data according to requests from the host device 10. For example, the storage device 1100 may include at least one of a solid state drive (SSD), an embedded memory, a removable external memory, or any other suitable memory structure known to those of ordinary skill in the art. When the storage device 1100 includes an SSD, the storage device 1100 may comply with the Non-Volatile Memory Express (NVMe) protocol. When the storage device 1100 includes an embedded memory or an external memory, the storage device 1100 may comply with the Universal Flash Storage (UFS) protocol or the Embedded MultiMediaCard (eMMC) protocol. The host device 10 and the storage device 1100 may each generate and send packets according to the adopted standard protocol.

[0033] When the NVM 1300 of the storage device 1100 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. In some embodiments, the storage device 1100 may include various other types of NVM. Examples of the storage device 1100 may include magnetic RAM (MRAM), spin transfer torque MRAM (STT MRAM), conductive-bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), and various other types of memories.

[0034] According to one or more embodiments, the host controller 11 and the host memory 12 may be implemented as separate semiconductor chips. According to one or more embodiments, the host controller 11 and the host memory 12 may be integrated on the same semiconductor chip. As an example, the host controller 11 may be any one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system-on-chip (SoC). In one or more embodiments, the host memory 12 may be an embedded memory included in the application processor, or may be an NVM or a memory module provided outside the application processor.

[0035] The host controller 11 may manage operations of storing data (e.g., write data) in the storage buffer region in the NVM 1300 or storing data in the NVM 1300 in the buffer region (e.g., read data). In one or more examples, the host controller 11 may retrieve data from the NVM 1300 or store data in the NVM 1300 via the storage controller 1200.

[0036] The storage controller 1200 may include a host interface circuit HI, a memory interface circuit MI, and a central processing unit (CPU) 1210. In one or more embodiments, the storage controller 1200 may further include a flash translation layer (FTL) 1220, a data movement manager 1230, a buffer memory 1240, an error correction code (ECC) engine 1250, and an advanced encryption standard (AES) engine 1260. The storage controller 1200 may further include a working memory loaded with the FTL 1220, and data write operations and read operations of the NVM may be controlled by running the FTL 1220 by the CPU 1210. The storage controller 1200 may further include a packet manager.

[0037] In one or more examples, the host interface circuit HI may send packets to and receive packets from the host device 10. Packets sent from the host device 10 to the host interface circuit HI may include commands or data to be written to the NVM 1300, and packets sent from the host interface circuit HI to the host device 10 may include responses to commands or data read from the NVM 1300. The memory interface circuit MI may send data to be written to the NVM 1300 to the NVM 1300 or receive data read from the NVM 1300. The memory interface circuit MI may comply with a standard protocol such as Toggle, Open NAND Flash Interface (ONFI), or any other suitable protocol known to those of ordinary skill in the art.

[0038] In one or more examples, the FTL 1220 may perform several functions such as address mapping, wear leveling, and garbage collection. Address mapping is an operation of changing a logical address received from the host to a physical address for actually storing data in the NVM 1300. Wear leveling is a technique for preventing excessive degradation of a specific block by uniformly using blocks in the NVM 1300, and may be implemented by, for example, a firmware technique for balancing the erase counts of physical blocks. Garbage collection is a technique for ensuring the available capacity in the NVM 1300 by copying valid data of a block to a new block and erasing the existing block.

[0039] The ECC engine 1250 may perform error detection and correction functions for read data read from the NVM 1300. The ECC engine 1250 may perform an error detection operation and an error correction operation. The ECC engine 1250 may perform an error detection operation to determine whether an error exists in the data. The ECC engine 1250 may perform an error detection operation to determine the number of error bits (NEB) in the data.

[0040] More specifically, the ECC engine 1250 can generate parity bits for write data to be written to the NVM 1300, and the generated parity bits can be stored in the NVM 1300 together with the write data. When reading data from the NVM 1300, the ECC engine 1250 can correct errors in the read data by using the parity bits read from the NVM 1300 together with the read data, and can output the read data with errors corrected.

[0041] In one or more embodiments, the ECC engine 1250 can perform an error detection operation or an error correction operation by using one of cyclic redundancy check (CRC) (e.g., CRC-16, CRC-32, CRC-64, CRC-128, CRC-256, etc.), Hamming code, low density parity check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, Reed-Solomon (RS) code, Viterbi code, and Turbo code.

[0042] The AES engine 1260 can perform at least one of an encryption operation and a decryption operation on data input to the storage controller 1200 by using a symmetric key algorithm.

[0043] The packet manager can generate packets that comply with the protocol of the interface between the packet manager and the host device 10, or parse each piece of information from the packets received from the host device 10. The buffer memory 1240 can temporarily store data to be written to the NVM 1300 or data to be read from the NVM 1300. The buffer memory 1240 can be included in the storage controller 1200, or can be provided outside the storage controller 1200.

[0044] The data movement manager 1230 can perform a write-back operation. The data movement manager 1230 can be in the form of hardware, software, or a combination thereof, all of which are configured to manage the write-back operation. The data movement manager 1230 can determine the write-back method for the remaining pages in the group based on the NEB representing the page. The data movement manager 1230 can determine from one of an internal write-back operation and an external write-back operation.

[0045] The data movement manager 1230 can manage groups. The data movement manager 1230 can divide the pages stored in the source area (e.g., the first area A1) in the write-back operation into multiple groups. For example, multiple pages included in the same group can have a similar error rate. The data movement manager 1230 can select a representative page to represent the group. The data movement manager 1230 can select a page expected to have a high error rate in the group as the representative page. For example, the data movement manager 1230 can select the page programmed first as the representative page.

[0046] The data movement manager 1230 can determine the write-back method of a group based on the error level representative of a page. The data movement manager 1230 can perform an external write-back operation only for a group expected to have many errors and can perform an internal write-back operation for a group expected to have fewer errors. Accordingly, performance degradation due to the external write-back operation can be prevented. The operation of the data movement manager 1230 can be described in more detail with reference to the following drawings.

[0047] In one or more examples, each of the FTL 120, the data movement manager 1230, the ECC engine 1250, and the AES engine 1260 can be implemented by a separate processor or can be implemented by a separate circuit. In one or more examples, the operations performed by each of the FTL 120, the data movement manager 1230, the ECC engine 1250, and the AES engine 1260 can be performed by one or more processors.

[0048] Figure 2 is according to one or more embodiments of Figure 1 block diagram of the NVM 1300.

[0049] Referring to Figure 1 and Figure 2 NVM 1300 may include an input / output (I / O) circuit 1310, a control logic circuit 1320, a memory cell array 1330, a page buffer circuit 1340, a voltage generator 1350, and a row decoder 1360. In one or more examples, NVM 1300 may further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

[0050] In one or more examples, the control logic circuit 1320 can generally control various operations of the NVM 1300. The control logic circuit 1320 can output various control signals in response to a command CMD and / or an address ADDR from the host controller 11. For example, the control logic circuit 1320 can output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0051] In one or more examples, the memory cell array 1330 can include a plurality of memory blocks, and each of the plurality of memory blocks can include a plurality of memory cells. The memory cell array 1330 can be connected to the page buffer circuit 1340 through bit lines BL and can be connected to the row decoder 1360 through word lines WL, string selection lines SSL, and ground selection lines GSL.

[0052] In one or more embodiments, the memory cell array 1330 may include a 3D memory cell array. The 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. Further disclosures regarding the structure, operation, and fabrication of non-volatile memory devices are found in U.S. Patent Publication No. 7679133, U.S. Patent Publication No. 8553466, U.S. Patent Publication No. 8654587, U.S. Patent Publication No. 8559235, and U.S. Patent Application Publication No. 2011 / 0233648, which are incorporated herein by reference in their entirety. In one or more embodiments, the memory cell array 1330 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0053] In one or more examples, the page buffer circuit 1340 may include a plurality of page buffers (e.g., n is an integer of 3 or greater), and the plurality of page buffers may be respectively connected to the memory cells through a plurality of bit lines BL. The page buffer circuit 1340 may select at least one bit line from the bit lines BL in response to a column address Y-ADDR. The page buffer circuit 1340 may operate as a write driver or a read amplifier according to an operation mode. For example, during a programming operation, the page buffer circuit 1340 may apply a bit line voltage corresponding to data to be programmed to the selected bit line. During a read operation, the page buffer circuit 1340 may detect the current or voltage of the selected bit line and detect the data stored in the memory cell.

[0054] In one or more examples, the voltage generator 1350 may generate various types of voltages for programming operations, read operations, and erase operations based on a voltage control signal CTRL_vol. For example, the voltage generator 1350 may generate a programming voltage, a read voltage, a program verify voltage, an erase voltage, etc. as a word line voltage VWL.

[0055] In one or more examples, the row decoder 1360 may select one of the word lines WL and one of the string select lines SSL in response to a row address X-ADDR. For example, the row decoder 1360 may apply a programming voltage and a program verify voltage to the selected word line during a programming operation, and may apply a read voltage to the selected word line during a read operation.

[0056] The storage controller 1200 can transmit a chip enable signal ( / CE), a command latch enable signal (CLE), an address latch enable signal (ALE), a read enable signal ( / RE), and a write enable signal ( / WE) to the NVM 1300. The storage controller 1200 and the NVM 1300 can send and receive data signals (DQx) and data strobe signals (DQS) therebetween.

[0057] [Table 1]

[0058]

[0059]

[0060] Table 1 illustrates the operation modes of the NVM 1300 according to the state of each signal according to one or more embodiments. Referring to Table 1, when the NVM 1300 receives a command CMD or an address ADDR or inputs and outputs DATA, the chip enable signal ( / CE) remains at a low level (L). During the command input mode (CMD Input), the storage controller 1200 can control the signal lines such that the clock latch enable signal (CLE) has a high level (H), the address latch enable signal (ALE) has a low level (L), the write enable signal ( / WE) toggles between a high level (H) and a low level (L), and the read enable signal ( / RE) has a high level (H). During the command input mode (CMD Input), the storage controller 1200 can send the command CMD to the NVM 1300 through the data signal DQx synchronously with the rising edge (↑) of the write enable signal ( / WE). The NVM 1300 can identify the command CMD from the data signal DQx in response to the rising edge (↑) of the write enable signal ( / WE).

[0061] In one or more examples, during the address input mode (ADDR Input), the storage controller 1200 can control the signal lines such that the clock latch enable signal (CLE) has a low level (L), the address latch enable signal (ALE) has a high level (H), the write enable signal ( / WE) toggles between a high level (H) and a low level (L), and the read enable signal ( / RE) has a high level (H). During the address input mode (ADDR Input), the storage controller 1200 can send the address ADDR to the NVM 1300 through the data signal DQx synchronously with the rising edge (↑) of the write enable signal ( / WE). The NVM 1300 can identify the address ADDR from the data signal DQx in response to the rising edge (↑) of the write enable signal ( / WE).

[0062] In one or more examples, during a data input mode (Data Input), the memory controller 1200 may control signal lines such that a clock latch enable signal (CLE) has a low level (L), an address latch enable signal (ALE) has a low level (L), a write enable signal ( / WE) has a high level (H), a read enable signal ( / RE) has a high level (H), and a data strobe signal (DQS) toggles between a high level (H) and a low level (L). During the data input mode (Data Input), the memory controller 1200 may send DATA to the NVM 1300 through data signals DQx synchronously with rising edges (↑) and falling edges (↓) of the data strobe signal (DQS). The NVM 1300 may identify DATA from the data signals DQx in response to the rising edges (↑) and falling edges (↓) of the data strobe signal DQS.

[0063] In one or more examples, during a data input mode (Data Input), the memory controller 1200 may control signal lines such that a clock latch enable signal (CLE) has a low level (L), an address latch enable signal (ALE) has a low level (L), a write enable signal ( / WE) has a high level (H), a read enable signal ( / RE) has a high level (H), and the read enable signal ( / RE) toggles between a high level (H) and a low level (L). During a data output mode (Data Output), the NVM 1300 may generate a data strobe signal (DQS) that toggles between a high level (H) and a low level (L) in response to the read enable signal ( / RE). The NVM 1300 may transfer DATA to the memory controller 1200 through data signals DQx synchronously with rising edges (↑) and falling edges (↓) of the data strobe signal (DQS). The memory controller 1200 may identify DATA from the data signals DQx in response to the rising edges (↑) and falling edges (↓) of the data strobe signal (DQS). The above switching interfaces are examples, and the scope of embodiments of the present disclosure is not limited thereto.

[0064] Figure 3 is an example of Figure 2 an equivalent circuit diagram of a memory block according to one or more embodiments.

[0065] Referring to Figure 3 , memory block BLKi shows a three-dimensional memory block having a three-dimensional structure on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate. As understood by those of ordinary skill in the art, although Figure 3The memory blocks illustrated in the figure show three bit lines each connected to eight memory cells, but embodiments of the present disclosure are not limited to these configurations, and a memory block may include any desired number of bit lines and memory cells.

[0066] Referring Figure 3 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST. Figure 3 It is shown that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 to MC8, but it is not necessarily limited to this.

[0067] In one or more examples, the string select transistor SST may be connected to its corresponding string select lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be respectively connected to corresponding gate lines GTL1 to GTL8. The gate lines GTL1 to GTL8 may correspond to word lines, and some of the gate lines GTL1 to GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to its corresponding ground select lines GSL1 to GSL3. The string select transistor SST may be connected to each of its corresponding first bit line BL1 to third bit line BL3, and the ground select transistor GST may be connected to the common source line CSL.

[0068] In one or more examples, word lines at the same height (e.g., WL1) may be commonly connected, and the ground select lines GSL1 to GSL3 and the string select lines SSL1 to SSL3 may be separated from each other. In Figure 3 , the memory block BLKi is shown connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3, but embodiments are not limited to this.

[0069] Figure 4 is Figure 1 a diagram of an example of the operation of the storage device 1100.

[0070] Referring Figure 1 and Figure 4 , according to one or more embodiments, the NVM 1300 of the storage device 1100 may include a first region A1 and a second region A2. The first region A1 may refer to the source region for the write-back operation. For example, the first region A1 may refer to the space where data to be read in the write-back operation is stored. The second region A2 may refer to the destination region for the write-back operation. For example, the second region A2 may refer to the space where data is reprogrammed in the write-back operation.

[0071] In one or more examples, the storage device 1100 may perform a write-back operation. For example, the storage device 1100 may perform a write-back operation when executing a programming operation based on an SLC buffer scheme. As part of the write-back operation, the storage device 1100 may first write data to a first region A1 and then write the data to a second region A2, rather than directly writing the data to the second region A2. For example, the storage device 1100 may write data to an SLC region and then write the data to a TLC or quad-level cell (QLC) region. The storage device 1100 may collect data from the first region A1 and simultaneously program the data into the second region A2.

[0072] In one or more examples, the storage device 1100 may first write the write data received from the host device 10 to the first region A1. In this case, since the write data received from the host device 10 is written to the first region A1 (e.g., SLC programming), a faster operation speed can be guaranteed compared to when performing a normal write operation for the second region A2 (e.g., TLC programming or QLC programming).

[0073] The data written to the first region A1 may be refreshed or migrated to the second region A2. For example, according to an explicit command from the host device 10 or an internal predetermined policy, the data written to the first region A1 may be migrated to the second region A2. For example, the policy may specify one or more conditions that, when satisfied, cause the data to be migrated from the first region A1 to the second region A2. For example, migration may be performed when a predetermined number of storage cells in the second region A2 become available or when the first region A1 is full and the second region A2 has the necessary number of available cells. In one or more embodiments, the storage device 1100 may perform a write-back operation during idle time.

[0074] In one or more embodiments, the first region A1 may be a buffer region. The second region A2 may be a user storage region. In one or more embodiments, each storage cell corresponding to the first region A1 may be used as an SLC and each storage cell corresponding to the second region A2 may be used as a TLC. In one or more embodiments, each storage cell corresponding to the first region A1 may be used as an SLC and each storage cell corresponding to the second region A2 may be used as a QLC. In one or more examples, each storage cell corresponding to the first region A1 may be configured to store n bits of data (e.g., n is a positive integer) and each memory cell corresponding to the second region A2 may be configured to store m bits of data (e.g., m is a positive integer greater than n). For example, the first region A1 may refer to a region that supports faster high-speed writing compared to the second region A2.

[0075] In one or more embodiments, the storage device 1100 may perform garbage collection. The storage controller 1200 may select a sacrificial block from among used blocks (or blocks having valid data) to generate a free block. The storage controller 1200 may copy the valid pages within the selected sacrificial block to the free block. The storage controller 1200 may perform a write-back operation. In one or more embodiments, the first region A1 may refer to the selected sacrificial block. The second region A2 may be the free block in which the valid pages are stored.

[0076] Figure 5A and Figure 5B is a diagram illustrating an example of the write-back operation of the storage device.

[0077] Refer to Figure 5A to describe the external write-back operation and refer to Figure 5B to describe the internal write-back operation. Refer to Figure 1 、 Figure 5A and Figure 5B According to, the storage device 1100 may move the data stored in the first region A1 to the second region A2. For example, the storage device 1100 may perform a write-back operation.

[0078] In one or more embodiments, the storage device 1100 may perform one of an external write-back operation and an internal write-back operation. The external write-back operation may refer to a write-back operation including data transmission and reception between the NVM 1300 and the storage controller 1200. The internal write-back operation may refer to a write-back operation not including data transmission and reception between the NVM 1300 and the storage controller 1200. For example, the write-back operation may be performed by transmitting data within the NVM 1300 through the NVM 1300, or the write-back operation may be performed by transmitting data within the storage controller 1200 through the storage controller 1200.

[0079] In one or more examples, the external write-back operation may include sending data from the NVM 1300 to the storage controller 1200 and receiving data from the storage controller 1200 by the NVM 1300.

[0080] According to one or more embodiments, the external write-back operation may include operations S11 to S14. In operation S11, the NVM 1300 may send the data stored in the first region A1 to the page buffer circuit 1340. The NVM 1300 may read out the data stored in the first region A1 and store the read-out data in the page buffer circuit 1340.

[0081] In operation S12, the NVM 1300 may send the data stored in the page buffer circuit 1340 to the storage controller 1200. Operation S12 may be referred to as a data output operation.

[0082] In one or more examples, the storage controller 1200 may perform an error detection operation and an error correction operation on the received data. The storage controller 1200 may perform an error correction operation to generate corrected data. In operation S13, the storage controller 1200 may send the corrected data to the NVM 1300. The NVM 1300 may store the corrected data in the page buffer circuit 1340. Operation S13 may be referred to as a data input operation.

[0083] In operation S14, the NVM 1300 may store the data in the second area A2. For example, the NVM 1300 may program the data into the second area A2. The NVM 1300 may store the corrected data stored in the page buffer circuit 1340 in the second area A2.

[0084] The internal write-back operation may include operations S21 and S22. In operation S21, the NVM 1300 may send the data stored in the first area A1 to the page buffer circuit 1340. The NVM 1300 may read out the data stored in the first area A1 and store the read-out data in the page buffer circuit 1340. In operation S22, the NVM 1300 may store the data in the second area A2. For example, the NVM 1300 may store the data stored in the page buffer circuit 1340 in the second area A2.

[0085] In one or more examples, the internal write-back operation may not include the data output operation and the data input operation of the external write-back operation. The internal write-back operation may not include the error correction operation performed by the storage controller 1200. Compared with the time required for the internal write-back operation, the external write-back operation may also include the time required for the data output operation, the time required for the error correction operation, and the time required for the data input operation. The external write-back operation may take more time than the internal write-back operation.

[0086] Figure 6 is an example of the operation of a Figure 1 storage device according to one or more embodiments.

[0087] Reference Figure 6Describe an example method of a write-back operation. The storage device 1100 is assumed to store data in the first area A1. The storage device 1100 can perform operations S110 to S150 to move the data stored in the first area A1 to the second area A2. The data stored in the first area A1 can be divided into multiple groups. Each of the multiple groups can include multiple pages. The storage device 1100 can move the data to the second area A2 in group units. The group unit can also be referred to as a page group.

[0088] In one or more embodiments, a group can include multiple pages, and it can be expected that the pages included in the same group exhibit similar characteristics. For example, the pages in the same group can have the same or similar error rates. For example, the pages included in the same group can have similar reliability levels. The pages included in the same group can be stored in physically adjacent storage cells. The pages included in the same group can be programmed in the same or similar manner. The time elapsed after the pages included in the same group are programmed can be similar. The pages included in the same group can have the same or similar characteristics. Therefore, the write-back method for the remaining pages in the group can be determined based on the error rate (e.g., NEB) of the representative page in the group.

[0089] For example, the pages included in the same group can refer to the pages stored in the storage cells of the string selection lines connected to the same word line. The pages included in the same group can refer to the pages stored in the storage cells connected to adjacent word lines in the same block. The pages included in the same group can refer to the pages stored in the storage cells connected to the same word line in different blocks. The pages included in the same group can refer to the pages stored in the storage cells connected to the same word line in the same block of different planes. In one or more examples, the pages included in the same group can have similar physical locations. The pages included in the same group can have similar error levels. In one or more examples, one of the pages from the group can be selected as the representative page of the group.

[0090] In one or more embodiments, the storage device 1100 can move the data stored in the first area A1 to the second area A2 by either an internal write-back operation or an external write-back operation. The storage device 1100 can determine the write-back method for the entire group based on the error rate or NEB of the representative page in the group.

[0091] Reference Figure 1 and Figure 6, in operation S110, the storage device 1100 may select a representative page in a group. In one or more embodiments, the storage controller 1200 may determine any one of the multiple pages in the group as the representative page (e.g., a sample page). The storage controller 1200 may select the page that is first programmed in the group as the representative page. In one or more examples, the storage controller 1200 may select the page that is expected to have the lowest transfer rate between the storage controller 1200 and the NVM 1300. In one or more examples, the storage controller 1200 may select the page that is expected to have the highest error rate as the representative page.

[0092] For example, during the process of programming the memory cells connected to adjacent string select lines, programming interference may occur in the memory cells connected to the adjacent string select lines. As a result, the errors of the memory cells connected to the first programmed string select line may increase. The storage controller 1200 may select the page stored in the memory cells of the first programmed string select line among the multiple string select lines that are further connected to the same word line. The storage controller 1200 may select the page that is prone to errors as the representative page.

[0093] In one or more examples, the storage controller 1200 may perform a read operation on the selected representative page. The storage controller 1200 may send a read command including the address corresponding to the representative page to the NVM 1300. The storage controller 1200 may receive the representative page from the NVM 1300.

[0094] In operation S120, the storage device 1100 may perform an error detection operation on the representative page. The storage controller 1200 may perform an error detection operation to determine the error rate or NEB of the representative page. The storage controller 1200 may determine the NEB of the representative page.

[0095] In operation S130, the storage device 1100 may compare the NEB with a threshold. The threshold may be a predetermined value. The threshold may be selected as fixed or variable by the designer, manufacturer, and / or user. The storage controller 1200 may determine whether an error correction operation is required based on the NEB of the representative page. The storage controller 1200 may determine whether to perform an external write-back operation to perform the error correction operation based on the NEB. In one or more examples, the storage device 1100 may perform operation S140 when the NEB exceeds the threshold, and may perform operation S150 when the NEB is equal to or less than the threshold. In one or more examples, the storage controller 1200 may be configured with a threshold. In one or more examples, the storage controller 1200 may dynamically determine the threshold based on the error rate of the data stored in the non-volatile memory.

[0096] In operation S140, the memory device 1100 may perform an external write-back operation for a page in the group. Since the NEB is greater than the threshold, the memory controller 1200 may determine that an error correction operation is required. For example, since the error rate of the representative page is high, the memory controller 1200 may determine that an external write-back operation is to be performed for multiple pages in the group including the representative page. The memory controller 1200 may perform an external write-back operation for multiple pages in the group.

[0097] In operation S150, the memory device 1100 may perform an internal write-back operation for a page in the group. Since the NEB is equal to or less than the threshold, the memory controller 1200 may determine that an error correction operation is not required. For example, since the error rate of the representative page is low, the memory controller 1200 may determine that an internal write-back operation is to be performed for multiple pages in the group including the representative page. The memory controller 1200 may perform an internal write-back operation for multiple pages in the group.

[0098] As described above, the memory device 1100 may select a representative page in the group stored in the first area A1. The memory device 1100 may perform an error detection operation to determine the NEB of the representative page. When the NEB of the representative page exceeds a threshold value, the memory device 1100 may repeat an external write-back operation for each page in the group and store it in the second area A2 included in the NVM 130. When the NEB of the representative page is equal to or less than the threshold value, the memory device 1100 may repeat an internal write-back operation for each page in the group and store it in the second area A2.

[0099] Therefore, the storage device 1100 can advantageously omit determination for the remaining pages in the group except for the representative page. In this regard, by applying the result of determining the NEB of the representative page to the remaining pages, the storage device 1100 may not determine the write-back method for each of the remaining pages. The storage device 1100 can collectively determine the write-back method for the remaining pages in the group based on the determination result of the representative page. Therefore, a storage device with improved performance can be provided.

[0100] Figure 7 , Figure 8 , Figure 9A and Figure 9B is a flowchart illustrating an example of the operation of the storage device.

[0101] refer to Figure 8 , describes an external write-back operation for multiple pages in a group. Figure 9A , describes a first example of an internal write-back operation for multiple pages in a group. Figure 9B , describes a second example of an internal write-back operation for multiple pages in a group.

[0102] refer to Figure 1 , Figure 7 ,Figure 8 , Figure 9A and Figure 9B , according to one or more embodiments, the storage device 1100 may perform a write-back operation. The storage device 1100 may move data stored in the first area A1 to the second area A2.

[0103] Referring Figure 7 , in operation S201, the storage controller 1200 may select a representative page in the group. The storage controller 1200 may select the representative page R_PAGE in the group stored in the first area A1. The storage controller 1200 may select the page that was first programmed in the group as the representative page R_PAGE. The storage controller 1200 may perform a read operation to identify the NEB of the representative page R_PAGE.

[0104] In operation S202, the storage controller 1200 may send a read command for the representative page R_PAGE to the NVM 1300. The storage controller 1200 may send a read command including an address corresponding to the representative page R_PAGE to the NVM 1300. This address may refer to a part of the first area A1.

[0105] In operation S203, the NVM 1300 may read the representative page R_PAGE in the first area A1 into the page buffer circuit 1340. In response to the read command, the NVM 1300 may store the representative page R_PAGE read by performing a read-out operation in the page buffer circuit 1340.

[0106] In operation S204, the NVM 1300 may send the representative page R_PAGE to the storage controller 1200. The NVM 1300 may send the representative page R_PAGE to the storage controller 1200 via the data signal DQx.

[0107] In operation S205, the storage controller 1200 may perform an error detection operation. The storage controller 1200 may determine the NEB of the representative page R_PAGE. In operation S206, the storage controller 1200 may compare the NEB with a threshold. The storage controller 1200 may perform operation S207 (error correction operation) when the NEB of the representative page R_PAGE exceeds the threshold, and may perform operation S220 when the NEB of the representative page R_PAGE is equal to or less than the threshold.

[0108] If the NEB representing the representative page R_PAGE is less than the threshold, the error correction operation for the representative page R_PAGE may not be performed. The storage controller 1200 may program the representative page R_PAGE into the second area A2. In one or more examples, the storage controller 1200 may send a write-back command (or write-back programming command) for the representative page R_PAGE to the NVM 1300 to store the representative page R_PAGE in the second area A2. In response to the write-back command (or write-back programming command), the NVM 1300 may store the representative page R_PAGE stored in the page buffer circuit 1340 in the second area A2. Subsequently, the storage controller 1200 may repeat the internal write-back operation for the remaining pages in the group. The storage controller 1200 may perform operations S220 to S229.

[0109] In operation S207, the storage controller 1200 may perform an error correction operation for the representative page R_PAGE. The storage controller 1200 may correct the representative page R_PAGE to generate a corrected representative page R_PAGE.

[0110] In operation S208, the storage controller 1200 may send a programming command and the corrected representative page R_PAGE to the NVM 1300. The NVM 1300 may receive the programming command and the corrected representative page R_PAGE through the data signal DQx.

[0111] In operation S209, the NVM 1300 may program the representative page R_PAGE into the second area A2. The NVM 1300 may store the corrected representative page R_PAGE in the second area A2. Subsequently, the storage device 1100 may perform operation S210.

[0112] If the NEB of the representative page R_PAGE is greater than the threshold, the storage device 1100 may perform an external write-back operation for the remaining pages in the group. The external write-back operation may include operations S210 to S218( Figure 8 ). Refer to Figure 8 , in operation S210, the storage controller 1200 may set the variable i to 1. For example, the variable i is used to describe the repeated execution of the external write-back operation and does not limit the scope of the embodiments of the present disclosure.

[0113] The storage controller 1200 may perform a read operation for the i-th page. In operation S211, the storage controller 1200 may send a read command to the NVM 1300. The storage controller 1200 may send a read command including an address corresponding to the i-th page to the NVM 1300. This address may refer to a part of the first area A1.

[0114] In operation S212, the NVM 1300 may read the i-th page in the first region A1 into the page buffer circuit 1340. In response to the read command, the NVM 1300 may store the i-th page read by performing the read operation in the page buffer circuit 1340.

[0115] In operation S213, the NVM 1300 may send the i-th page to the storage controller 1200. The NVM 1300 may send the i-th page to the storage controller 1200 via the data signal DQx.

[0116] In operation S214, the storage controller 1200 may perform an error correction operation on the i-th page. The storage controller 1200 may correct the i-th page to generate a corrected i-th page.

[0117] In one or more embodiments, the storage controller 1200 may perform an error detection operation before performing the error correction operation. The storage controller 1200 may perform an error detection operation on the i-th page. If an error is detected in the i-th page, the storage controller 1200 may perform an error correction operation on the i-th page. If no error is detected in the i-th page, the storage controller 1200 may not perform the error correction operation. If no error is detected in the i-th page, the storage controller 1200 may program the i-th page into the second region A2. In one or more examples, the storage controller 1200 may send a write-back command for the i-th page to the NVM 1300 to store the i-th page in the second region A2.

[0118] The storage controller 1200 may store the i-th page in the second region A2. In operation S215, the storage controller 1200 may send a program command and the corrected i-th page to the NVM 1300. The NVM 1300 may receive the program command and the corrected i-th page. In operation S216, the NVM 1300 may program the i-th page into the second region A2. The NVM 1300 may store the corrected i-th page in the second region A2 in response to the program command.

[0119] In operation S217, the storage controller 1200 may determine whether the variable i is the maximum value (MAX). For example, the maximum value may refer to the number of pages in a group. If the variable i is the maximum value, since all the pages in the group have been moved from the first region A1 to the second region A2, the write-back operation is completed. If the variable i is not the maximum value, the storage controller 1200 performs operation S218. In operation S218, the storage controller 1200 may increment the variable i by 1. Subsequently, the storage controller 1200 may perform operation S211. In one or more examples, the maximum value may be set to an integer corresponding to the number of pages in the page group. In one or more examples, the maximum value may be set to an integer less than the number of pages in the page group.

[0120] As described above, the storage device 1100 may perform an external write-back operation. The storage controller 1200 may send a read command for a page to the NVM 1300. The NVM 1300 may output the page to the storage controller. The storage controller 1200 may perform an error correction operation on the page. The storage controller 1200 may output a programming command and the corrected i-th page to the NVM 1300.

[0121] If the NEB representing the reference page R_PAGE is equal to or less than the threshold, the storage device 1100 may perform an internal write-back operation on the remaining pages in the group. The internal write-back operation may include operations S220 to S229( Figure 9A ). Refer to Figure 9A , in operation S220, the storage controller 1200 may set the variable k to 1. For example, the variable k is used to describe the repeated execution of the internal write-back operation and does not limit the scope of the embodiments of the present disclosure.

[0122] The storage controller 1200 may perform an internal write-back operation on the k-th page. In operation S222, the storage controller 1200 may send a write-back command to the NVM 1300. The NVM 1300 may receive the write-back command. In operation S224, the NVM 1300 may read the k-th page in the first region A1 into the page buffer circuit 1340. In response to the write-back command, the NVM 1300 may store the k-th page read by performing the read operation in the page buffer circuit 1340.

[0123] In operation S226, the NVM 1300 may program the k-th page into the second region A2. The NVM 1300 may store the k-th page stored in the page buffer circuit 1340 in the second region A2. In one or more examples, after the k-th page is programmed into the second region A2, the k-th page is deleted from the page buffer circuit 1340.

[0124] In operation S228, the storage controller 1200 may determine whether the variable k is the maximum value (MAX). For example, the maximum value may refer to the number of pages in a group. If the variable k is the maximum value, since all the pages in the group have been moved from the first area A1 to the second area A2, the write-back operation is completed. If the variable k is not the maximum value, the storage controller 1200 performs operation S229. In operation S229, the storage controller 1200 may increment the variable k by 1. Subsequently, the storage controller 1200 may perform operation S222. In one or more examples, after the k-th page is programmed into the second area A2, the k-th page is deleted from the page buffer circuit 1340.

[0125] As described above, the storage device 1100 may perform an internal write-back operation. The storage controller 1200 may send a write-back command. In response to the write-back command, the NVM 1300 may read the data stored in the first area A1 and store the read data in the page buffer circuit 1340. The NVM 1300 may store the page stored in the page buffer circuit 1340 in the second area A2.

[0126] Reference Figure 9B , since operations S220, S224, S226, S228, and S229 are the same as or similar to Figure 9A operations S220, S224, S226, S228, and S220 thereof, their detailed descriptions are omitted. In operation S220, the storage controller 1200 may set the variable k to 1. In operation S223, the storage controller 1200 may send a read command for write-back to the NVM 1300. In operation S224, the NVM 1300 may read the k-th page in the first area A1 in response to the read command for write-back. The NVM 1300 may store the k-th page in the page buffer circuit 1340.

[0127] In operation S225, the storage controller 1200 may send a write-back programming command to the NVM 1300. In operation S226, the NVM 1300 may program the k-th page into the second area A2 in response to the write-back programming command. The NVM 1300 may store the k-th page stored in the page buffer circuit 1340 in the second area A2. In operation S228, the storage controller 1200 may determine whether the variable k is the maximum value (MAX). If the variable k is not the maximum value, the storage controller 1200 performs operation S229. In operation S229, the storage controller 1200 may increment the variable k by 1. Subsequently, the storage controller 1200 may perform operation S223. The maximum value may be determined as described above.

[0128] As described above, when the error rate of the representative page R_PAGE is low, the storage controller 1200 may not perform error detection operations on the remaining pages in the group and may not perform error correction operations on the remaining pages in the group. In one or more embodiments, the NVM 1300 may not output the remaining pages in the group to the outside or may not receive data input from the outside. That is, the NVM 1300 may only move the remaining pages in the group internally. In one or more examples, when the error rate of the representative page R_PAGE is low, the maximum value discussed above may be set to be less than the number of pages in the group.

[0129] Figure 10A and Figure 10B is a timing diagram showing an example of the operation of the storage device.

[0130] Refer to Figure 10A to describe the external write-back operation and refer to Figure 10B to describe the internal write-back operation. In addition to the input / output of the representative page R_PAGE, Figure 10A and Figure 10B are also illustrated.

[0131] Refer to Figure 1 and Figure 10A , when the NEB of the representative page R_PAGE exceeds the threshold, the storage controller 1200 may repeat the external write-back operation for the remaining pages in the group. For example, the storage controller 1200 may perform a read operation PAGE1 DRead OP for the first page. The storage controller 1200 may perform a programming operation PAGE1 DPgm OP for the first page. The storage controller 1200 may perform a read operation PAGE2 DRead OP for the second page. The storage controller 1200 may perform a programming operation PAGE2 DPgm OP for the second page.

[0132] Specifically, the storage controller 1200 may perform a read operation PAGE1 DRead OP for the first page. The storage controller 1200 may send a first read command RD1 during the command input mode (CMD Input). Subsequently, the storage controller 1200 may send a first address AD1 during the address input mode (ADDR Input). For example, the first address AD1 may be the address of the first area A1 for the first page.

[0133] Subsequently, in one or more examples, the storage controller 1200 may send a second read command RD2 to the NVM 1300 during the command input mode (CMD Input). In response to the second read command RD2, the NVM 1300 may read the data of the first page corresponding to the first address AD1 as the first data DT1 during the time tR.

[0134] Subsequently, in one or more examples, the storage controller 1200 may perform an error detection operation and an error correction operation on the received first data DT1. The storage controller 1200 may generate the corrected first data DT1. The storage controller 1200 may store the corrected first data DT1 in the second area A2.

[0135] Subsequently, in one or more examples, the storage controller 1200 may perform a programming operation PAGE1 DPgm OP on the first page. The storage controller 1200 may send a first programming command PM1 to the NVM 1300 during the command input mode (CMD Input). Subsequently, in one or more examples, the storage controller 1200 may send a second address AD2 to the NVM 1300 during the address input mode (ADDRInput). For example, the second address AD2 may be the address of the second area A2 for the first page.

[0136] Subsequently, in one or more examples, the storage controller 1200 may send the first data DT1 to the NVM 1300 during the data input mode (DataInput). Subsequently, the storage controller 1200 may send a second programming command PM2 to the NVM 1300 during the command input mode (CMDInput). In response to the second programming command PM2, the NVM 1300 may program the first data DT1 into the second address AD2 during the time tPROG. In one or more embodiments, after the time tPROG, the storage controller 1200 may send a status read command to the NVM 1300 and receive the status of the NVM1300 from the NVM 1300.

[0137] The storage controller 1200 may perform a read operation PAGE2 DRead OP on the second page. The storage controller 1200 may send a first read command RD1 to the NVM 1300 during the command input mode (CMD Input). Subsequently, in one or more examples, the storage controller 1200 may send a third address AD3 to the NVM 1300 during the address input mode (ADDR Input). For example, the third address AD3 may be the address of the first area A1 for the second page.

[0138] Subsequently, in one or more examples, the storage controller 1200 may send a second read command RD2 to the NVM 1300 during the command input mode (CMD Input). In response to the second read command RD2, the NVM 1300 may read the data of the second page corresponding to the third address AD3 as the second data DT2 during the time tR.

[0139] Subsequently, in one or more examples, the storage controller 1200 may perform an error detection operation and an error correction operation on the received second data DT2. The storage controller 1200 may generate the corrected second data DT2. The storage controller 1200 may store the corrected second data DT2 in the second area A2.

[0140] Subsequently, in one or more examples, the storage controller 1200 may perform a programming operation PAGE2 DPgm OP on the second page. The storage controller 1200 may send a first programming command PM1 during the command input mode (CMD Input). Subsequently, in one or more examples, the storage controller 1200 may send a fourth address AD4 during the address input mode (ADDR Input). For example, the fourth address AD4 may be the address of the second area A2 for the second page.

[0141] Subsequently, the storage controller 1200 may send the second data DT2 during the data input mode (Data Input). Subsequently, the storage controller 1200 may send a second programming command PM2 during the command input mode (CMD Input). In response to the second programming command PM2, the NVM 1300 may program the second data DT2 into the fourth address AD4 during the time tPROG.

[0142] Subsequently, in one or more examples, similar to the above description, the storage controller 1200 may perform read operations and programming operations on the third to the nth pages in the group. Their detailed descriptions are omitted. In this way, by performing read operations and programming operations on the pages in the group, the storage controller 1200 may move the data stored in the first area A1 to the second area A2.

[0143] For example, the storage controller 1200 may start a read operation PAGE1DRead OP on the first page at the first time point t1. The storage controller 1200 may complete a programming operation PAGE2 DPgmOP on the second page at the second time point t2. For example, the storage controller 1200 may perform an external write-back operation on the first page and the second page from the first time point t1 to the second time point t2.

[0144] Reference Figure 1 and Figure 10BWhen the NEB representing the representative page R_page is equal to or lower than the threshold, the storage controller 1200 may repeat the external write-back operation for the remaining pages in the group. For example, the storage controller 1200 may perform a write-back operation PAGE1 CB OP for the first page. The storage controller 1200 may perform a write-back operation PAGE2 CB OP for the second page.

[0145] In particular, the storage controller 1200 may perform a write-back operation PAGE1 CB OP for the first page. The storage controller 1200 may send a first read command RC1 for write-back during the command input mode (CMD Input). Subsequently, in one or more examples, the storage controller 1200 may send a first address AD1 during the address input mode (ADDR Input). For example, the first address AD1 may be the address of the first area A1 of the first page.

[0146] Subsequently, in one or more examples, the storage controller 1200 may send a second read command RC2 for write-back during the command input mode (CMD Input). In response to the second read command RC2 for write-back, the NVM 1300 may read the data of the first page corresponding to the first address AD1 into the page buffer circuit 1340 during the time tR.

[0147] Subsequently, in one or more examples, the storage controller 1200 may send a first write-back programming command CP1 during the command input mode (CMD Input). Subsequently, the storage controller 1200 may send a second address AD2 during the address input mode (ADDR Input). For example, the second address AD2 may be the address of the second area A2 of the first page.

[0148] Subsequently, in one or more examples, the storage controller 1200 may send a second write-back programming command CP2 during the command input mode (CMD Input). In response to the second write-back programming command CP2, the NVM 1300 may program the data of the page buffer circuit 1340 into the second address AD2 during the time tPROG.

[0149] The storage controller 1200 may perform a write-back operation PAGE2 CB OP for the second page. The storage controller 1200 may send a first read command RC1 for write-back during the command input mode (CMD Input). Subsequently, in one or more examples, the storage controller 1200 may send a third address AD3 during the address input mode (ADDR Input). For example, the third address AD3 may be the address of the first area A1 of the second page.

[0150] Subsequently, in one or more examples, the storage controller 1200 may send a second read command RC2 for write-back during the command input mode (CMD Input). In response to the second read command RC2 for write-back, the NVM 1300 may read the data of the second page corresponding to the third address AD3 into the page buffer circuit 1340 during the time tR.

[0151] Subsequently, in one or more examples, the storage controller 1200 may send a first write-back programming command CP1 during the command input mode (CMD Input). Subsequently, the storage controller 1200 may send a fourth address AD4 during the address input mode (ADDR Input). For example, the fourth address AD4 may be the address of the second region A2 for the second page.

[0152] Subsequently, in one or more examples, the storage controller 1200 may send a second write-back programming command CP2 during the command input mode (CMD Input). In response to the second write-back programming command CP2, the NVM 1300 may program the data of the page buffer circuit 1340 into the fourth address AD4 during the time tPROG.

[0153] Subsequently, in one or more examples, similar to the above description, the storage controller 1200 may perform write-back operations for the third to the nth pages in the group. Their detailed descriptions are omitted. In this way, by performing write-back operations for the pages in the group, the storage controller 1200 may move the data stored in the first region A1 to the second region A2.

[0154] For example, the storage controller 1200 may start the write-back operation PAGE1DRead OP for the first page at the first time point t1. The storage controller 1200 may complete the write-back operation PAGE2 CB OP for the second page at the third time point t3. For example, the storage controller 1200 may perform an internal write-back operation for the first page and the second page from the first time point t1 to the second time point t3. The third time point t3 may be earlier than the second time point t2. The storage controller 1200 may perform an internal write-back operation to reduce the time required for the write-back operation. The internal write-back operation may improve the write performance by performing data input / output operations without passing through the data signal DQx.

[0155] Figure 11 is a diagram of an example of the operation of a storage device according to one or more embodiments.

[0156] Reference Figure 1 and Figure 11, the first area A1 may include the first to the sixteenth pages. For example, the storage controller 1200 may store the first to the sixteenth pages in the first area A1. The storage controller 1200 may classify the first to the sixteenth pages into the first group G1 to the fourth group G4. For example, the first group G1 may include the first to the fourth pages, the second group G2 may include the fifth to the eighth pages, the third group G3 may include the ninth to the twelfth pages, and the fourth group G4 may include the thirteenth to the sixteenth pages. Although each group includes an equal number of pages, the number of pages in each group may vary such that two groups contain different numbers of pages.

[0157] The storage controller 1200 may select a representative page in the group. For example, the storage controller 1200 may select the first page as the representative page in the first group G1. The storage controller 1200 may select the fifth page as the representative page in the second group G2. The storage controller 1200 may select the ninth page as the representative page in the third group G3. The storage controller 1200 may select the thirteenth page as the representative page in the fourth group G4.

[0158] The NEB of the first page may be a first value v1, the NEB of the fifth page may be a second value v2, the NEB of the ninth page may be a third value v3, and the NEB of the thirteenth page may be a fourth value v4. The first value v1 may be greater than the fourth value v4, the fourth value v4 may be greater than the threshold, the third value v3 may be less than the threshold, and the second value v2 may be less than the third value v3.

[0159] The storage controller 1200 may determine the write-back method of the group based on the NEB of the representative page. The storage controller 1200 may calculate the error rate of the first page related to the first group G1. The storage controller 1200 may read the first page from the NVM 1300 and perform an error detection operation on the first page. The storage controller 1200 may determine that the NEB of the first page is the first value v1. Since the threshold is less than the first value v1, the storage controller 1200 may determine to perform an external write-back operation for the first group G1. The storage controller 1200 may perform an external write-back operation for the second to the fourth pages and may store the second to the fourth pages in the second area A2.

[0160] The storage controller 1200 may calculate the error rate of the fifth page related to the second group G2. The storage controller 1200 may read the fifth page, which is the representative page of the second group G2, from the NVM 1300 and perform an error detection operation on the fifth page. The storage controller 1200 may determine that the NEB of the fifth page is the second value v2. Since the second value v2 is less than the threshold, the storage controller 1200 may determine to perform an internal write-back operation for the second group G2. The storage controller 1200 may perform an internal write-back operation for the sixth to the eighth pages and may store the sixth to the eighth pages in the second area A2.

[0161] The storage controller 1200 may calculate the error rate of the ninth page associated with the third group G3. The storage controller 1200 may read the ninth page, which is a representative page of the third group G3, from the NVM 1300 and perform an error detection operation on the ninth page. The storage controller 1200 may determine that the NEB of the ninth page is the third value v3. Since the third value v3 is less than the threshold, the storage controller 1200 may determine to perform an internal write-back operation on the third group G3. The storage controller 1200 may perform an internal write-back operation on the tenth to twelfth pages and may store the tenth to twelfth pages in the second area A2.

[0162] The storage controller 1200 may calculate the error rate of the thirteenth page associated with the fourth group G4. The storage controller 1200 may read the thirteenth page from the NVM 1300 and perform an error detection operation on the thirteenth page. The storage controller 1200 may determine that the NEB of the thirteenth page is the fourth value v4. Since the fourth value v4 is greater than the threshold, the storage controller 1200 may determine to perform an external write-back operation on the fourth group G4. The storage controller 1200 may perform an external write-back operation on the fourteenth to sixteenth pages and may store the fourteenth to sixteenth pages in the second area A2.

[0163] As described above, according to the error level of the representative page, the write-back method of the remaining pages in the group may be determined during the write-back operation. The external write-back operation may be adaptively performed instead of always performing the external write-back operation. The proportion of performing the external write-back operation may be advantageously reduced. Therefore, a storage device with improved performance may be provided.

[0164] Figure 12 is a block diagram of a storage system 1000a according to one or more embodiments.

[0165] Refer to Figure 12 , the storage system 1000a may include a host device 10 and a storage device 1100a. In one or more embodiments, the storage device 1100a may include a storage controller 1200a and an NVM 1300. The host device 10 may include a host controller 11 and a host memory 12.

[0166] The storage controller 1200a may include a host interface circuit HI, a memory interface circuit MI, and a CPU 1210. In one or more embodiments, the storage controller 1200a may further include an FTL 1220, a data movement manager 1230, a buffer memory 1240, an ECC engine 1250, an AES engine 1260, and a read level manager 1270. For the sake of simplicity of illustration, the detailed description of the above components is omitted.

[0167] The read level manager 1270 may perform a read voltage search operation. The read voltage search operation may refer to an operation for determining an optimal read voltage level or a plurality of optimal read voltage levels. The read level manager 1270 may be in the form of hardware, software, or a combination thereof, all of which are configured to perform the read voltage search operation.

[0168] Due to various factors, the threshold voltage of the memory cells in the NVM 1300 may change. For example, "retention degradation" or "charge loss" may occur in the memory cells. In one or more examples, "retention degradation" or "charge loss" may refer to a degradation characteristic in which the threshold voltage of the memory cells decreases. "Retention degradation" or "charge loss" may occur over time from the time point when the memory cells are programmed.

[0169] "Read disturbance" or "charge gain" may occur in the memory cells. In one or more examples, "read disturbance" or "charge gain" may refer to a degradation characteristic in which the threshold voltage of the memory cells increases. "Read disturbance" or "charge gain" may be generated by repeatedly reading the memory cells or the surrounding memory cells.

[0170] In a programmed memory cell, an error may occur in the data read from the memory cell when the threshold voltage increases or the threshold voltage decreases. In the memory cells, when retention degradation or read disturbance occurs, an operation of controlling the read level or searching for an optimal read level may be performed.

[0171] The read level manager 1270 may be configured to manage the read voltage levels used during read operations in the NVM 1300. For example, the NVM 1300 may perform read operations using multiple read voltages. In this case, an error in reading data may occur due to various factors. In this case, by changing the levels of the multiple read voltages, errors can be prevented. The read level manager 1270 may be configured to control the levels of the multiple read voltages based on the degradation information of the memory cells included in the NVM 1300. In one or more embodiments, the read level manager 1270 may control multiple read levels or search for an optimal read level through a read voltage search operation. In one or more examples, the optimal read level may be a read voltage that minimizes the error rate of the pages stored in the NVM 1300.

[0172] For example, the read level manager 1270 may be configured to search for the optimal read voltage used in the NVM 1300. The read level manager 1270 may set operation parameters based on the degradation state of the memory cells and perform a read voltage search operation based on the set operation parameters.

[0173] The read level manager 1270 can perform a read voltage search operation for the representative page in the group and search for the optimal read level. The read level manager 1270 can read the remaining pages in the group from the NVM 1300 by using the searched optimal read level. For example, the read level manager 1270 can apply the optimal read level of the representative page to the remaining pages in the group. Therefore, a storage device with improved reliability can be provided.

[0174] Figure 13 Yes Figure 12 is a flowchart of an example of the operation of the storage device.

[0175] Refer to Figure 6 、 Figure 12 and Figure 13 , since operations S310, S340, S350, S360, and S370 are similar to operations S110, S120, S130, S140, and S150 of Figure 6 respectively, their detailed descriptions are omitted.

[0176] In operation S310, the storage controller 1200a can select a representative page in the group. For example, the storage controller 1200a can select the page that was first programmed in the group as the representative page. In operation S320, the storage device 1100a can perform a read voltage search operation. In one or more embodiments, the storage controller 1200a can search for the optimal read voltage of the representative page. The storage controller 1200a can perform the read voltage search operation based on the degradation state of the storage cells. The storage controller 1200a can search for the optimal read level through the read voltage search operation. In operation S330, the storage device 1100a can determine the optimal read level. The storage controller 1200a can determine the optimal read level of the representative page.

[0177] In operation S340, the storage device 1100a can perform an error detection operation for the representative page. The storage controller 1200a can determine the NEB of the representative page. In operation S350, the storage device 1100a can compare the NEB with a threshold. The storage device 1100a can perform operation S360 when the NEB exceeds the threshold, and can perform operation S370 when the NEB is equal to or less than the threshold.

[0178] In operation S360, the storage device 1100a may perform an external write-back operation on the pages in the group. The storage controller 1200a may perform the external write-back operation by using the optimal read level representative of the page. The storage controller 1200a may perform a read operation on the remaining pages in the group. The storage controller 1200a may perform an error detection operation or an error correction operation on the pages received from the NVM 1300. The storage controller 1200a may program the pages into the second region A2.

[0179] In one or more embodiments, the storage controller 1200a may perform a read operation on the remaining pages in the group by using the optimal read level representative of the page. For example, the storage controller 1200a may send a read command including the optimal read level information to the NVM 1300. In one or more examples, the storage controller 1200a may set the optimal read level by a separate command (e.g., a set feature command). The NVM 1300 may read the pages of the first region A1 by using the optimal read level representative of the page.

[0180] In operation S370, the storage device 1100a may perform an internal write-back operation on the pages in the group. The storage controller 1200a may perform the internal write-back operation by using the optimal read level representative of the page. The storage controller 1200a may send a write-back command. In response to the write-back command, the NVM 1300 may store the pages in the group stored in the first region A1 in the page buffer circuit 1340. The NVM 1300 may store the pages stored in the page buffer circuit 1340 in the second region A2.

[0181] In one or more embodiments, the storage controller 1200a may send a write-back command (or a read command for write-back) including the optimal read level information to the NVM 1300. In one or more examples, the storage controller 1200a may set the optimal read level by a separate command (e.g., a set feature command). The NVM 1300 may read the pages of the first region A1 by using the optimal read level representative of the page.

[0182] As described above, the storage device 1100a may perform a read voltage search operation on the representative page. The storage device 1100a may determine the optimal read level based on the result of the read voltage search operation. The storage device 1100a may repeat the external write-back operation based on the optimal read level applied to the representative page. The storage device 1100a may repeat the internal write-back operation based on the optimal read level applied to the representative page.

[0183] Figure 14 is a block diagram of the NVM 1300a according to one or more embodiments.

[0184] Reference Figure 2 and Figure 14 ,The NVM 1300a may include an input / output (I / O) circuit 1310, a control logic circuit 1320, a memory cell array 1330, a page buffer circuit 1340, a voltage generator 1350, and a row decoder 1360. For ease of explanation, a detailed description of the above components is omitted.

[0185] In one or more embodiments, the NVM 1300a may include an ECC circuit 1370. The ECC circuit 1370 may perform error detection and correction functions on data read from the memory cell array 1330. The ECC circuit 1370 may perform error detection operations and error correction operations. The ECC circuit 1370 may perform an error detection operation to determine whether an error exists in the data. The ECC circuit 1370 may perform an error detection operation to determine the NEB of the data.

[0186] More specifically, the ECC circuit 1370 may generate parity bits for write data to be written to the memory cell array 1330, and the generated parity bits may be stored in the memory cell array 1330 together with the write data. When reading data from the memory cell array 1330, the ECC circuit 1370 may correct an error in the read data by using the parity bits read from the memory cell array 1330 together with the read data, and may output the read data with the error corrected.

[0187] In one or more embodiments, the ECC circuit 1370 may perform an error detection operation or an error correction operation by using one of CRC (e.g., CRC-16, CRC-32, CRC-64, CRC-128, CRC-256, etc.), Hamming code, LDPC, BCH code, RS code, Viterbi code, and Turbo code.

[0188] In one or more embodiments, since the NVM 1300a includes the ECC circuit 1370, data may not be sent to the storage controller 1200 for error detection operations and error correction operations. The NVM 1300a may not output data to the storage controller 1200 in order to move data stored in the first area A1 to the second area A2.

[0189] In one or more embodiments, the NVM 1300a may read data stored in the first area A1 and store the read data in the page buffer circuit 1340. The NVM 1300a may perform error detection operations and error correction operations on the data stored in the page buffer circuit 1340. The NVM 1300a may program the corrected data into the second area A2.

[0190] In one or more embodiments, the NVM 1300a may determine whether to perform error detection operations and error correction operations on the remaining pages in the group based on the NEB of the representative page in the group. The NVM 1300 may select the representative page. The NVM 1300a may read the representative page of the first area A1 and store the read representative page in the page buffer circuit 1340. The NVM1300a may determine the NEB by performing error detection operations on the representative page. When the NEB exceeds the threshold, the NVM 1300a may perform error detection operations and error correction operations on the remaining pages in the group. When the NEB is less than or equal to the threshold, the NVM1300a may not perform error detection operations and error correction operations on the remaining pages in the group.

[0191] In one or more embodiments, the NVM 1300a may read the remaining pages in the group located in the first area A1 and store the remaining pages in the page buffer circuit 1340. The NVM 1300a may directly store the remaining pages in the group in the second area A2 without error correction operations or error detection operations.

[0192] The above description is a specific example of implementing the embodiments of the present disclosure.

[0193] Although the embodiments of the present disclosure have been specifically shown and described with reference to the embodiments of the present disclosure, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a storage controller and a storage device including a non-volatile storage device, the method comprising: selecting, by the storage controller, a representative page in a first page group stored in a first area included in the non-volatile storage device; receiving, by the storage controller, the representative page from the non-volatile storage device; performing, by the storage controller, an error detection operation to determine an error bit number of the representative page; based on determining that the error bit number of the representative page exceeds a threshold, performing, by the storage controller, an external write-back operation for each page in a plurality of pages in the first page group and storing it in a second area included in the non-volatile storage device; and based on determining that the error bit number of the representative page is less than or equal to the threshold, performing, by the storage controller, an internal write-back operation for each page in the plurality of pages in the first page group and storing it in the second area.

2. The method according to claim 1, wherein The first area includes a first group of storage cells configured to store n bits per cell, wherein the second area includes a second group of storage cells configured to store m bits per cell, wherein n is a positive integer, and wherein m is a positive integer greater than n.

3. The method according to claim 1, wherein The external write-back operation includes: sending, by the storage controller, a read command for the representative page to the non-volatile storage device; outputting, by the non-volatile storage device, the representative page to the storage controller; performing, by the storage controller, an error correction operation on the representative page to generate a corrected page; and outputting, by the storage controller, a programming command and the corrected page to the non-volatile storage device.

4. The method according to claim 1, wherein, The internal write-back operation includes: sending, by the storage controller, a write-back command to the non-volatile storage device.

5. The method according to claim 4, wherein The internal write-back operation further includes: in response to the write-back command, (i) reading, by the non-volatile storage device, a page stored in the first area, and (ii) storing, by the non-volatile storage device, the read page in a page buffer circuit; and programming, by the non-volatile storage device, the read page stored in the page buffer circuit into the second area.

6. The method according to claim 1, wherein the method further comprises: Comparing the error bit number with the threshold.

7. The method according to claim 1, wherein Selecting the representative page in the first page group includes selecting a page programmed before other pages in the first page group.

8. The method according to claim 1, the method further comprising: performing a read voltage search operation for the representative page; and determining, based on a result of the read voltage search operation, one or more optimal read voltage levels.

9. The method according to claim 8, wherein performing the external write-back operation further includes repeating the external write-back operation based on the one or more optimal read voltage levels applied to the representative page, and performing the internal write-back operation includes repeating the internal write-back operation based on the one or more optimal read voltage levels applied to the representative page.

10. A storage device, the storage device comprising: a non-volatile storage device including a first area and a second area; and A storage controller configured to perform a migration operation in which pages in a first page group stored in the first area are moved to the second area, where To perform the migration operation, the storage controller is configured to select a representative page in the first page group, perform an error detection operation to determine the number of error bits of the representative page in the first page group, and based on determining that the number of error bits of the representative page exceeds a threshold, perform an external write-back operation for each of a plurality of pages in the first page group to store them in the second area, and based on determining that the number of error bits of the representative page is less than or equal to the threshold, perform an internal write-back operation for each of the plurality of pages in the first page group to store them in the second area.

11. The storage device according to claim 10, wherein, The external write-back operation further includes: The storage controller sends a read command for the representative page to the non-volatile storage device; The non-volatile storage device outputs the representative page to the storage controller; The storage controller performs an error correction operation on the representative page to generate a corrected page; and The non-volatile storage device receives a programming command and the corrected page from the storage controller.

12. The storage device according to claim 10, wherein, The internal write-back operation further includes: The storage controller sends a write-back command to the non-volatile storage device; The non-volatile storage device, in response to the write-back command, (i) reads out the page stored in the first area and (ii) stores the read-out page in a page buffer circuit; and The non-volatile storage device programs the page stored in the page buffer circuit into the second area.

13. The storage device according to claim 10, wherein, Selecting the representative page includes: The storage controller selects a page that was programmed before other pages in the first page group from the first page group.

14. The storage device according to claim 10, wherein, The storage controller is configured to: perform a read voltage search operation on the representative page and determine one or more optimal read voltage levels based on the result of the read voltage search operation.

15. The storage device according to claim 14, wherein, The storage controller is configured to: repeat the internal write-back operation and repeat the external write-back operation based on the one or more optimal read voltage levels applied to the representative page.

16. A method of operating a storage controller configured to control a non-volatile storage device including a first area and a second area, the method including: Selecting a representative page in a first page group stored in the first area included in the non-volatile storage device; Receiving the representative page from the non-volatile storage device; Performing an error detection operation to determine the number of error bits of the representative page; Based on determining that the number of error bits of the representative page exceeds a threshold, performing an external write-back operation for each of a plurality of pages in the first page group to store them in the second area included in the non-volatile storage device; And Based on determining that the number of error bits of the representative page is less than or equal to the threshold, performing an internal write-back operation for each of the plurality of pages in the first page group to store them in the second area.

17. The method according to claim 16, wherein, The external write-back operation includes: Send a read command for the representative page to the non-volatile memory device; Receive the representative page from the non-volatile memory device; Perform an error correction operation on the representative page to generate a corrected page; and Output a programming command and the corrected page to the non-volatile memory device.

18. The method according to claim 16, wherein The internal write-back operation includes: sending a write-back command to the non-volatile memory device.

19. The method according to claim 16, wherein Selecting the representative page in the first page group includes selecting a page that was programmed before other pages in the first page group.

20. The method according to claim 16, the method further comprising: Performing a read voltage search operation for the representative page; and Determining one or more optimal read voltage levels based on the result of the read voltage search operation.

Images