Signal processing system, electronic apparatus, storage medium, and program product

Abstract

The invention discloses a signal processing system, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, and the method comprises the steps that when data needs to be received in a delayed manner, a substrate management controller can determine first data in a first memory, the first data can be an alternating bit sequence, and the first data are stored in a second memory according to a plurality of first delays; the first memory is used for receiving the first data, reading the first data to obtain a plurality of read second data, determining a second delay used for data receiving according to the first data, the plurality of read second data and the plurality of first delays, and storing the second delay in the second memory. Therefore, the first data of the alternate bit sequence is read by traversing the first delay, and the second delay used for data receiving is determined, so that the probability of conflict of signal receiving of the substrate management controller is reduced, and the success rate of signal receiving of the substrate management controller is improved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a signal processing system, an electronic device, a storage medium, and a program product. Background Art

[0002] By embedding a baseboard management controller on the motherboard of a server, it is convenient for users to remotely monitor and manage the hardware status.

[0003] In a complex system, when the baseboard management controller receives data from multiple devices simultaneously, problems such as signal interference and conflicts may occur. In the related art, signal interference can be reduced by controlling the baseboard management controller to delay receiving signals. However, in the above method, the delay receiving duration is determined by randomly selecting data, resulting in a poor effect of the delay receiving duration. Summary of the Invention

[0004] This application provides a signal processing system, an electronic device, a storage medium, and a program product to at least solve the problem of poor effect of the delay receiving duration.

[0005] This application provides a signal processing system, including:

[0006] The baseboard management controller determines first data and stores the first data in a first memory. The first data is an alternating bit sequence;

[0007] The baseboard management controller reads the first data in the first memory according to a plurality of first delays to obtain a plurality of second data;

[0008] The baseboard management controller determines a second delay according to the first data, the plurality of second data, and the plurality of first delays. The second delay is the delay for the baseboard management controller to receive data;

[0009] The baseboard management controller stores the second delay in a second memory.

[0010] This application also provides a data processing device, including: a first determination module, a reading module, and a second determination module, where

[0011] The first determination module is configured to determine first data and store the first data in a first memory. The first data is an alternating bit sequence;

[0012] The reading module is configured to read the first data in the first memory according to a plurality of first delays to obtain a plurality of second data;

[0013] A second determination module, configured to determine a second latency according to first data, multiple pieces of second data, and multiple first latencies, where the second latency is the latency for the baseboard management controller to receive data, and the baseboard management controller stores the second latency in a second memory.

[0014] This application further provides an electronic device, including: a memory, configured to store a computer program; and a processor, configured to implement any of the above signal processing systems when executing the computer program.

[0015] This application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, any of the above signal processing systems is implemented.

[0016] This application further provides a computer program product, including a computer program, which implements any of the above signal processing systems when executed by a processor.

[0017] Through this application, when data needs to be received with latency, the baseboard management controller can first determine first data in a first memory. The first data can be an alternating bit sequence. According to multiple first latencies, the first data is read to obtain multiple pieces of read second data. According to the first data, multiple pieces of read second data, and multiple first latencies, a second latency for data reception is determined and stored in the second memory. In the above process, by traversing the first latencies to read the first data of the alternating bit sequence, an optimal second latency for data reception is determined. Since the first data is an alternating bit sequence, the diversity of training samples is improved, and at the same time, the reliability of the second latency is improved, thereby improving the success rate of the baseboard management controller in receiving signals. Description of the Drawings

[0018] To more clearly illustrate the embodiments of this application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1a It is a schematic diagram of the system architecture provided by the embodiment of this application;

[0020] Figure 1b It is a schematic diagram of the system architecture provided by the embodiment of this application;

[0021] Figure 2 It is a schematic diagram of the data processing flow of the signal processing system provided by the embodiment of this application;

[0022] Figure 3Schematic diagram of the internal clock signal of the baseboard management controller;

[0023] Figure 4 Schematic diagram of the process of data reception by the signal processing system provided in the embodiment of the present application according to the second delay;

[0024] Figure 5 Schematic diagram of the first daughter board and the second daughter board provided in the embodiment of the present application;

[0025] Figure 6 Schematic diagram of the structure of the data processing device provided in the embodiment of the present application;

[0026] Figure 7 Schematic diagram of the structure of another data processing device provided in the embodiment of the present application;

[0027] Figure 8 Schematic diagram of the structure of the electronic device provided in the present application. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0029] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and not to describe a specific order or sequence.

[0030] First, the nouns involved in the present application are explained:

[0031] Baseboard Management Controller: The baseboard management controller is an embedded controller, usually used in servers and other enterprise-level hardware, providing remote management and monitoring functions for the hardware. The baseboard management controller runs independently of the main operating system and can still perform management operations when the operating system crashes or the server shuts down. The baseboard management controller is an important part of modern data centers and enterprise-level servers. The baseboard management controller can be used for remote power control, hardware monitoring, remote console access, firmware update, and remote management, etc.

[0032] In a complex system, when the baseboard management controller receives data from multiple devices simultaneously, problems such as signal interference and conflicts may occur. In the related art, the signal interference can be reduced by controlling the baseboard management controller to delay receiving the signal. However, in the above method, the delay receiving duration is determined by randomly selecting data, resulting in a poor effect of the delay receiving duration.

[0033] To address the above problems, in the embodiments of the present application, in a signal processing system, when data needs to be processed, the baseboard management controller can first determine first data in a first memory. The first data can be an alternating bit sequence. The first data is read according to multiple first delays to obtain multiple second data after reading. According to the first data, the multiple second data after reading, and the multiple first delays, a second delay for data reception is determined and stored in a second memory. In this way, by traversing the first delays to read the first data of the alternating bit sequence and determining the second delay for data reception, the probability of signal conflicts when the baseboard management controller receives signals is reduced, and thus the success rate of the baseboard management controller receiving signals is improved.

[0034] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the signal processing system depends, the specific application environment architecture or specific hardware architecture is described herein. Refer to Figure 1a and Figure 1b . Figure 1a This is a schematic diagram of the system architecture provided by the embodiments of the present application. Please refer to Figure 1a, including a board card, which includes a baseboard management controller, a first memory, a second memory, a central processing unit, a multiplexer, and a level shifter. The baseboard management controller can be used to receive the status information sent by the components within the board card and remotely monitor the components within the board card. The first memory can be used to store data. For example, the first memory can be used to store firmware storage, file system, etc. The second memory can be used to store data. For example, the second memory can be used to store configuration parameters, user settings, and other data that needs to be frequently updated. The storage capacity of the first memory can be greater than that of the second memory. The central processing unit can be used to execute instructions, process data, and coordinate the work of other hardware in the system. The multiplexer can be used to route signals. The level shifter can be used to convert the signal level between different voltage domains to ensure that devices with different voltages can communicate safely. Among them, the central processing unit can be connected to and communicate with the multiplexer. The level shifter can be used to perform level conversion between the baseboard management controller and the multiplexer. The baseboard management controller can be connected to the second memory. The baseboard management controller can read and receive the data of the second memory. The multiplexer can be connected to the first memory and perform data transmission.

[0036] Figure 1b Another schematic diagram of the system architecture provided by the embodiment of the present application. Please refer to Figure 1b , including a first daughter board, a second daughter board, and, where the first daughter board includes a second memory and a baseboard control manager, and the second daughter board includes a first memory, a second memory, a central processing unit, a level shifter, and a multiplexer. The first daughter board and the second daughter board are connected through a connector. Among them, the baseboard control manager is connected to the second memory of the first daughter board and the second memory of the second daughter board. The baseboard management controller can read and receive the data of the second memory. The baseboard control manager is connected to the level shifter of the second daughter board. The level shifter can be used to perform level conversion between the baseboard management controller and the multiplexer. The central processing unit can be connected to and communicate with the multiplexer. The multiplexer can be connected to the first memory and perform data transmission.

[0037] The following uses specific embodiments to detail the technical solution of the present application and how the technical solution of the present application solves the above technical problems. These several specific embodiments below can be combined with each other. For the same or similar concepts or processes, they may not be repeated in some embodiments. The following will describe the embodiments of the present application with reference to the accompanying drawings.

[0038] Figure 2 The flow diagram of data processing for the signal processing system provided by the embodiment of the present application is as Figure 2 shown as follows:

[0039] S201: A baseboard management controller determines first data and stores the first data in a first memory.

[0040] The execution subject of the embodiment of the present application may be a baseboard management controller, or a data processing device arranged in the baseboard management controller. The data processing device may be implemented by software, or by a combination of software and hardware.

[0041] The first data is an alternating bit sequence stored in a first memory corresponding to the board, that is, the first data is a discontinuous binary number, and the binary number may refer to 0 and 1.

[0042] Illustratively, the first data may be 010101010101010, or 1010101010, etc.

[0043] The board may refer to a board of a server or a board of a computer terminal device. A baseboard management controller and a first memory may be provided on the board, and the first memory may be used to store data, and the first memory may be a flash memory module.

[0044] The first data may be determined in the following manner: generating the first data, the first data being an alternating bit sequence, the data size corresponding to the first data being a preset size, and the preset size being a value preset by a user.

[0045] Optionally, the first data can also be determined in the following manner: traverse the data stored in the first memory to determine multiple pre-selected data, where the pre-selected data is an alternating bit sequence; determine the data size corresponding to each pre-selected data, and determine the target data within each pre-selected data, wherein the target data has the largest data size; and determine the target data as the first data.

[0046] S202: The baseboard management controller reads the first data in the first memory according to the plurality of first delays to obtain a plurality of second data.

[0047] The first delay may refer to a delay duration for delaying the receiving of data, for example, the first delay may be 30ns, 100ns, etc. The multiple first delays may be multiple delay durations preset by a user, and the multiple first delays are different from each other.

[0048] For any first delay, the baseboard management controller may read the first data from the first memory after delaying the first delay at the falling edge of the internal clock signal according to the internal clock signal.

[0049] For example, assuming that the first delay is 50 ns, the baseboard management controller reads the first data after a delay of 50 ns at the falling edge of the internal clock signal.

[0050] The second data may refer to the first data read by the baseboard management controller with a first delay. There is a one-to-one correspondence between multiple first delays and multiple second data read according to the multiple first delays.

[0051] Next, in combination with Figure 3 , through specific examples, the first delay will be described in detail.

[0052] Figure 3 For a schematic diagram of the internal clock signal of the baseboard management controller, please refer to Figure 3 . According to the preset clock period, the clock signal may include multiple falling edges. The baseboard management controller delays by the first delay after the falling edge and then performs data reception.

[0053] S203. The baseboard management controller determines a second delay according to the first data, multiple second data, and multiple first delays.

[0054] The second delay is the delay for the baseboard management controller to perform data reception.

[0055] The second delay can be determined in the following way: according to the first data and multiple second data, determine the target data among the multiple second data; determine the first delay corresponding to the target data; according to the first delay corresponding to the target data, determine the second delay.

[0056] Among them, the similarity between the target data and the first data is greater than or equal to a preset threshold, and the target data can be one or more; the preset threshold can be a value preset by the user in advance.

[0057] The target data can be determined in the following way: perform a comparison process on the first data and multiple second data; determine the similarity between the first data and multiple second data; according to the similarity, determine the target data among the multiple second data, where the similarity of the target data is greater than or equal to the preset threshold.

[0058] For example, assume that there is first data, second data A, second data B, second data C, and second data D, the preset threshold is 0.8, the similarity between the first data and second data A is 0.96, the similarity between the first data and second data B is 0.89, the similarity between the first data and second data C is 0.58, and the similarity between the first data and second data D is 0.75. Then the similarity between the first data and second data A and the similarity between the first data and second data B are greater than or equal to the preset threshold, that is, the target data are second data A and second data B.

[0059] Optionally, the second delay can be determined based on the first delay corresponding to the target data in the following manner: Among the first delays corresponding to the target data, sort the first delays corresponding to at least one target data in descending order. According to the sorting, determine the maximum first delay and the minimum first delay; Based on the maximum first delay and the minimum first delay, determine the delay interval, where the minimum value of the delay interval is the minimum first delay and the maximum value of the delay interval is the maximum first delay; According to the delay interval, determine the second delay, and the second delay is the median of the delay interval.

[0060] For example, assume that the first delay corresponding to target data A is 10, the first delay corresponding to target data B is 38, the first delay corresponding to target data C is 30, and the first delay corresponding to target data D is 6. Then sort the first delays corresponding to the target data in descending order, and the order is the first delay corresponding to target data B, the first delay corresponding to target data C, the first delay corresponding to target data A, and the first delay corresponding to target data D. That is, the maximum first delay is 38 and the minimum first delay is 6. In this way, the delay interval can be determined as (6, 38), and the median of the delay interval (6, 38) is 22, so the second delay can be determined as 22.

[0061] Optionally, the second delay can be determined based on the first delay corresponding to the target data in the following manner: Among the first delays corresponding to the target data, sort the first delays corresponding to at least one target data in descending order. If the number of target data is even, select the two target data in the middle positions of the sorting, calculate the average value of the first delays corresponding to the two target data, and determine the average value as the second delay; If the number of target data is odd, select the target data in the middle position of the sorting, and determine the target data as the second delay.

[0062] For example, assume that the number of target data is even, the first delay corresponding to target data A is 10, the first delay corresponding to target data B is 38, the first delay corresponding to target data C is 30, and the first delay corresponding to target data D is 6. Then sort the first delays corresponding to the target data in descending order, and the order is the first delay corresponding to target data B, the first delay corresponding to target data C, the first delay corresponding to target data A, and the first delay corresponding to target data D. Then the average value of the first delay corresponding to target data A and the first delay corresponding to target data C is 20, that is, the second delay is 20.

[0063] Assume that the number of target data is odd. The first delay corresponding to target data A is 10, the first delay corresponding to target data B is 30, and the first delay corresponding to target data C is 15. Then, sort the first delays corresponding to the target data in descending order, and the order is: the first delay corresponding to target data B is 30, the first delay corresponding to target data C is 15, and the first delay corresponding to target data A is 10. Then, the second delay is the first delay corresponding to target data C, that is, the second delay is 15.

[0064] S204. The baseboard management controller stores the second delay in the second memory.

[0065] The board also includes a second memory, which can be used to store data, and the second memory can be a programmable memory.

[0066] In the embodiments of the present application, when the baseboard management controller needs to receive data with a delay, it can first determine the first data in the first memory, and the first data is an alternating bit sequence; according to multiple first delays, read the first data in the first memory to obtain multiple second data, and there is a one-to-one correspondence between the multiple first delays and the multiple second data read according to the multiple first delays; according to the first data, the multiple second data read, and the corresponding multiple first delays, the second delay can be determined and stored in the second memory. Among them, at least one target data can be determined according to the multiple first delays, the interval of the first delays corresponding to the at least one target data can be determined as the delay interval, and the second delay can be the median of the delay interval. In this way, by traversing the first delays to read the first data, the optimal second delay for data reception can be determined, which reduces the probability of signal reception conflicts of the baseboard management controller, and further improves the success rate of signal reception of the baseboard management controller; at the same time, the first data is an alternating bit sequence, so there are no consecutive binary numbers in the first data, such as consecutive 0s or consecutive 1s, which can improve the diversity of the first data, thereby improving the accuracy of the second delay determination.

[0067] Based on any of the above embodiments, below, in combination with Figure 4 , the process of the signal processing system receiving data according to the second delay will be described in detail.

[0068] Figure 4 FIG. is a schematic diagram of the process of the signal processing system provided by the embodiments of the present application receiving data according to the second delay. Please refer to Figure 4 , the method may include:

[0069] S401. In response to a startup instruction for the board, the baseboard management controller obtains board information, the second delay, and the first check code from the second memory.

[0070] The startup instruction for the board can refer to the instruction sent by the board to the baseboard management controller when the board receives power supply from the power source.

[0071] The second memory can refer to the memory of the programmable memory, and the programmable memory can be set on the board.

[0072] The board information can include the serial number of the board. For example, the board information can be AB1234567890.

[0073] The first check code can be the check code generated according to the second delay and the board information after determining the second delay. The first check code can be used to indicate whether the second delay has been tampered with.

[0074] The first check code can be determined in the following way: obtain the second delay and the board information, perform a verification process on the second delay and the board information to obtain the first check code, where the verification process can refer to a hash verification process; after determining the first check code, it further includes storing the first check code and the second delay in the second memory.

[0075] Before obtaining the board information, the second delay, and the first check code from the second memory, it further includes: obtaining the target parameter of the target area of the second memory, the target area is the area storing the second delay, and the target parameter is used to indicate whether valid data has been stored in the target area; when the target parameters are all preset values, determine the first data. The preset value can be 0.

[0076] It can be understood that when the target parameters are all preset values, it means that the baseboard management controller has not generated the second delay yet; when any one of the target parameters is not a preset value, it indicates that data has been written to the target area, that is, the second delay has been generated, and then obtain the board information, the second delay, and the first check code from the second memory.

[0077] S402. The baseboard management controller performs a verification process on the board information and the second delay to obtain a second check code.

[0078] Perform a verification process on the board information and the second delay obtained from the second memory to obtain a second check code.

[0079] The second check code can be used to indicate whether the second delay after being stored in the second memory has been tampered with.

[0080] S403. The baseboard management controller determines whether the first check code and the second check code are the same.

[0081] If so, execute S404.

[0082] If not, execute S405.

[0083] S404. The baseboard management controller determines that the second delay has not been tampered with during storage, and receives data according to the second delay.

[0084] That the second delay has not been tampered with during storage may mean that the second delay obtained from the second memory is the same as the second delay stored in the second memory.

[0085] S405. The baseboard management controller determines that the second delay has been tampered with during storage.

[0086] That the second delay has been tampered with during storage may mean that the second delay obtained from the second memory is different from the second delay stored in the second memory.

[0087] S406. The baseboard management controller rereads the first data according to multiple first delays to obtain multiple third data.

[0088] S407. The baseboard management controller redetermines the target data according to the first data and the multiple third data.

[0089] S408. The baseboard management controller redetermines the second delay according to the first delay corresponding to the redetermined target data.

[0090] It should be noted that the execution process of the above steps S406 - S408 can refer to S202 - S203, which will not be elaborated here.

[0091] S409. The baseboard management controller receives data according to the redetermined second delay.

[0092] At Figure 4In the illustrated embodiment, in response to a startup instruction for a board card, the baseboard management controller can obtain a second delay from a second memory for delaying the reception of data. To prevent the second delay stored in the second memory from being tampered with and causing data reception conflicts, the board card information, the second delay, and a first check code can be obtained from the second memory first, and then a verification process can be performed based on the board card information and the second delay obtained from the second memory to obtain a second check code. The second check code can be used to indicate whether the second delay has been tampered with after being stored in the second memory. Determine whether the first check code and the second check code are the same. If they are the same, it can be determined that the second delay has not been tampered with during storage, and data reception can be performed according to the second delay. If they are different, it can be determined that the second delay has been tampered with during storage, and a new second delay needs to be determined. Specifically, according to multiple first delays, the first data is read again to obtain multiple third data, and then based on the first data and the multiple third data, the target data is determined again. According to the first delay corresponding to the re-determined target data, the second delay is determined again, and data reception is performed according to the re-determined second delay. In this way, when the second delay is generated for the first time, the first check code is generated, and each time the second delay is obtained, the second check code is generated according to the obtained second delay. By comparing whether the first check code and the second check code are the same, it can be determined whether the second delay stored in the second memory has been tampered with, thereby improving the accuracy of the second delay and improving the reliability of data reception.

[0093] Based on any of the above embodiments, below, in combination with Figure 5 , when the board card in the signal processing system includes a first daughter board and a second daughter board, that is, the first memory and the second memory are located on different boards, the process of the signal processing system determining the second delay will be described in detail.

[0094] Figure 5 For the schematic diagrams of the first daughter board and the second daughter board provided by the embodiments of the present application, please refer to Figure 5 , which includes a first daughter board and a second daughter board. The first daughter board and the second daughter board are connected by a connector. The first daughter board may include a first memory and a second memory, and the second daughter board may include a baseboard management controller. Among them, the second daughter board may further include a third memory, and the third memory may be a programmable memory corresponding to the second daughter board.

[0095] The second memory stores the first daughter board information corresponding to the first daughter board and the second delay of the first daughter board, and the third memory stores the second daughter board information corresponding to the second daughter board and the second delay of the second daughter board.

[0096] The baseboard management controller can obtain the second latency of the first daughter board and the second latency of the second daughter board, and determine whether the second latency of the first daughter board is the same as the second latency of the second daughter board. If they are the same, the baseboard management controller reads data according to the second latency; if they are different, the baseboard management controller will re-determine the second latency and receive data according to the re-determined second latency.

[0097] From the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0098] Based on any of the above embodiments, the method for the signal processing system to process data can also be implemented based on a data processing device. Next, in combination with Figure 6 , the structure of the data processing device will be described in detail.

[0099] Figure 6 It is a schematic structural diagram of the data processing device provided by the embodiments of the present application. As Figure 6 shown, an embodiment of the present application also provides a data processing device 10, including: a first determination module 11, a reading module 12, and a second determination module 13, where

[0100] The first determination module 11 is configured to determine first data and store the first data as an alternating bit sequence stored in the first memory corresponding to the board in the first memory;

[0101] The reading module 12 is configured to read the first data in the first memory according to multiple first latencies to obtain multiple second data;

[0102] The second determination module 13 is configured to determine a second latency according to the first data, the multiple second data, and the multiple first latencies, and store the second latency in the second memory, where the second latency is the latency for the board to receive data.

[0103] A data processing device provided by an embodiment of the present application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, and will not be described in detail here.

[0104] In a possible design, the second determination module 13 is specifically configured to

[0105] Determine target data in the multiple second data according to the first data and the multiple second data, where the similarity between the target data and the first data is greater than or equal to a preset threshold;

[0106] Determine a first delay corresponding to the target data;

[0107] Determine the second delay according to the first delay corresponding to the target data.

[0108] In a possible design, the second determination module 13 is specifically configured to,

[0109] Determine the maximum first delay and the minimum first delay among the first delays corresponding to the target data;

[0110] Determine the second delay according to the maximum first delay and the minimum first delay.

[0111] In a possible design, the second determination module 13 is specifically configured to,

[0112] Perform a comparison process on the first data and the multiple second data;

[0113] Determine the similarity between the first data and the multiple second data;

[0114] According to the similarity, determine target data among the multiple second data, and the similarity of the target data is greater than or equal to a preset threshold.

[0115] A data processing device provided in an embodiment of the present application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0116] Figure 7 It is a structural schematic diagram of another data processing device provided in an embodiment of the present application. On the basis of the Figure 6 shown embodiment, please refer to Figure 7 , the data processing device 10 further includes: a verification module 14 and a third determination module 15, where,

[0117] The verification module 14 is configured to determine the board information of the board, and the board information includes the serial number of the board;

[0118] Perform a verification process on the board information and the second delay to obtain a first verification code;

[0119] Store the board information, the second delay, and the first verification code into the second memory corresponding to the board.

[0120] In a possible design, the verification module 14 is further configured to,

[0121] In response to a startup instruction for the board, obtain the board information, the second delay, and the first verification code from the second memory;

[0122] Perform a verification process on the board information and the second delay to obtain a second verification code;

[0123] Determine whether the first verification code is the same as the second verification code;

[0124] When the first verification code is the same as the second verification code, determine that the second delay has not been tampered with during storage;

[0125] Receive data according to the second delay;

[0126] When the first verification code is different from the second verification code, determine that the second delay has been tampered with during the storage;

[0127] According to the multiple first delays, reread the first data to obtain multiple third data;

[0128] According to the first data and the multiple third data, re-determine the target data;

[0129] According to the first delay corresponding to the re-determined target data, re-determine the second delay;

[0130] Receive data according to the re-determined second delay.

[0131] The third determination module 15 is configured to obtain a target parameter of a target area of a second memory, where the target area is an area storing the second delay, and the target parameter is used to indicate whether valid data has been stored in the target area;

[0132] When the target parameters are all preset values, determine the first data.

[0133] A data processing device provided by an embodiment of the present application can execute the technical solutions shown in the above method embodiments, and its implementation principle and beneficial effects are similar, and will not be elaborated here.

[0134] Figure 8 It is a schematic structural diagram of an electronic device provided by the present application. As Figure 8 shown, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. Among them, the processor 501, the memory 502, and the communication component 503 are connected through a bus.

[0135] In a specific implementation process, at least one processor 501 executes computer execution instructions stored in the memory 502, so that at least one processor 501 executes the above-mentioned method embodiment of managing a server cluster.

[0136] For the specific implementation process of the processor 501, reference may be made to the foregoing method embodiments. Their implementation principles and technical effects are similar, and will not be elaborated herein.

[0137] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU for short), or may also be other general-purpose processors, digital signal processors (DSP for short), application specific integrated circuits (ASIC for short), etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in combination with the application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0138] The memory may include a high-speed random access memory (RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory.

[0139] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience in representation, the buses in the drawings of this application are not limited to only one bus or one type of bus.

[0140] The embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute a signal processing system when running.

[0141] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs, etc., all of which can store computer programs.

[0142] Embodiments of the present application also provide a computer program product. The computer program product includes a computer program which, when executed by a processor, implements the above signal processing system.

[0143] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program which, when executed by a processor, implements the above signal processing system.

[0144] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0145] The above has introduced in detail a signal processing system, an electronic device, a storage medium, and a program product provided by the present application. Specific examples are used herein to elaborate on the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A signal processing system, characterized in that, The signal processing system includes: a board card, the board card includes a baseboard management controller, a first memory, and a second memory, where, The baseboard management controller determines first data and stores the first data in the first memory, and the first data is an alternating bit sequence; The baseboard management controller reads the first data in the first memory according to a plurality of first delays to obtain a plurality of second data; The baseboard management controller determines a second delay according to the first data, the plurality of second data, and the plurality of first delays, and the second delay is the delay for the baseboard management controller to receive data; The baseboard management controller stores the second delay in the second memory.

2. The signal processing system according to claim 1, wherein The baseboard management controller determines target data from the plurality of second data according to the first data and the plurality of second data, and the similarity between the target data and the first data is greater than or equal to a preset threshold; The baseboard management controller determines the first delay corresponding to the target data and determines the second delay according to the first delay corresponding to the target data.

3. The signal processing system according to claim 2, wherein The baseboard management controller determines the maximum first delay and the minimum first delay among the first delays corresponding to the target data, and determines the second delay according to the maximum first delay and the minimum first delay.

4. The signal processing system according to claim 2, wherein The baseboard management controller performs a comparison process on the first data and the plurality of second data and determines the similarity between the first data and the plurality of second data; The baseboard management controller determines target data from the plurality of second data according to the similarity, and the similarity of the target data is greater than or equal to a preset threshold.

5. The signal processing system according to any one of claims 1-4, wherein The baseboard management controller determines the board card information of the board card, and the board card information includes the serial number of the board card; The baseboard management controller performs a verification process on the board card information and the second delay to obtain a first verification code; The baseboard management controller stores the board card information, the second delay, and the first verification code in the second memory.

6. The signal processing system according to any one of claims 1-4, wherein The baseboard management controller, in response to a startup instruction for the board card, obtains the stored board card information, the second delay, and the first verification code from the second memory; The baseboard management controller performs a verification process on the board card information and the second delay to obtain a second verification code; The baseboard management controller determines whether the first verification code is the same as the second verification code; When the first verification code is the same as the second verification code, the baseboard management controller determines that the second delay has not been tampered with in the second memory; The baseboard management controller receives data according to the second delay; When the first check code and the second check code are different, the baseboard management controller determines that the second delay has been tampered with in the second memory; The baseboard management controller rereads the first data in the first memory according to the multiple first delays to obtain multiple third data; The baseboard management controller re-determines the target data according to the first data and the multiple third data; The baseboard management controller re-determines the second delay according to the first delay corresponding to the re-determined target data; The baseboard management controller receives data according to the re-determined second delay.

7. The signal processing system according to any one of claims 1-3, wherein The baseboard management controller obtains target parameters of a target area of the second memory, the target area is the area storing the second delay, and the target parameters are used to indicate whether valid data has been stored in the target area; When the target parameter indicates that no valid data has been stored in the target area, the baseboard management controller determines the first data.

8. The signal processing system according to any one of claims 1 to 3, characterized in that, The board card includes a first daughter board and a second daughter board. The first daughter board and the second daughter board are connected through a connector. The first daughter board includes the baseboard management controller and the second memory, and the second daughter board includes the first memory.

9. An electronic device, characterized in that, Comprising: A memory for storing a computer program; A processor for implementing the signal processing system according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the signal processing system according to any one of claims 1 to 8 when executed by a processor.

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