Integrated circuit process deviation sensitivity analysis method, device, equipment and medium

Abstract

The invention provides an integrated circuit process deviation sensitivity analysis method and device, equipment and a medium, and the method comprises the steps: carrying out N times of random sampling on process deviation variables corresponding to all devices in an integrated circuit, and obtaining a sampling matrix of the process deviation variables; performing circuit simulation according to the sampling matrix to obtain a corresponding circuit performance vector, and forming a data set by the sampling matrix and the circuit performance vector; constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector; and combining the influences of the random process deviation variables belonging to the same device on the circuit performance so as to evaluate the influence of each device on the circuit performance, and identifying a key device which has the greatest influence on the circuit performance. According to the embodiment of the invention, on the premise of ensuring the analysis precision, the sensitivity analysis of the high-dimensional process deviation space can be efficiently completed, the key device which has the greatest influence on the circuit performance can be accurately identified, and the circuit design can be conveniently optimized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a method, device, equipment and medium for analyzing the sensitivity of integrated circuit process variations. Background Art

[0002] In the process of integrated circuit design and manufacturing, as the process node enters the nanoscale, the impact of process variations on circuit performance becomes increasingly significant, which directly affects the reliability and yield of chips. Especially in large-scale integrated circuits, the failure of a small unit may lead to the malfunction of the entire system. For example, for a SRAM (Static Random Access Memory) array containing millions of units, the failure rate of any single unit must be extremely low (typical value is 10 -6 ), in order to ensure the normal operation of the entire array. Against this background, it is particularly important to establish an accurate and efficient method for analyzing the sensitivity of process variations. It is not only a necessary means to evaluate the robustness of circuits, but also an important basis for optimizing design margins and improving chip yields.

[0003] The finite difference method widely used in current process variation sensitivity analysis has significant limitations. This method is based on the principle of numerical differentiation, and calculates the sensitivity coefficient by applying a small perturbation to a single process parameter and observing the change in circuit response. It requires 2n simulations to complete the first-order sensitivity analysis of n parameters. Therefore, the computational efficiency of this method will deteriorate sharply in a high-dimensional parameter space. For modern large-scale integrated circuit design, the number of simulations required by this method will increase linearly, resulting in an unbearable computational cost. In addition, this method adopts an isolated parameter perturbation strategy and completely fails to capture the complex coupling effects between process parameters, which makes its analysis results often deviate significantly from the actual situation at the nanoscale process node. Summary of the Invention

[0004] The purpose of this application is to provide a method, device, equipment and medium for analyzing the sensitivity of integrated circuit process variations, which can efficiently complete the sensitivity analysis of a high-dimensional process variation space while ensuring the analysis accuracy, and accurately identify the key devices that have the greatest impact on circuit performance, so as to optimize the circuit design.

[0005] To solve the above technical problems, an embodiment of this application provides a method for analyzing the sensitivity of integrated circuit process variations, including: performing NPerform secondary random sampling to obtain a sampling matrix of process deviation variables; perform circuit simulation based on the sampling matrix to obtain a corresponding circuit performance vector, and form a data set with the sampling matrix and the circuit performance vector; construct a circuit performance parameter model based on the sampling matrix and the circuit performance vector; combine the impacts of process deviation variables belonging to the same device on the circuit performance to evaluate the impact of each device on the circuit performance, and identify the device with the greatest impact on the circuit performance.

[0006] In one embodiment, constructing the circuit performance parameter model based on the sampling matrix and the circuit performance vector includes: performing normalization processing on the sampling matrix and the circuit performance vector, and constructing the circuit performance parameter model based on the normalized sampling matrix and circuit performance vector.

[0007] In one embodiment, performing normalization processing on the sampling matrix and the circuit performance vector includes: performing normalization processing on each item in the circuit performance vector to obtain a vector :

[0008] where and represent the minimum and maximum values of all items in the circuit performance vector respectively, and simultaneously performing normalization on each column in the sampling matrix to obtain a matrix under the standard normal distribution:

[0009] where represents the m th column in the original sampling matrix, represents the m th column in the normalized sampling matrix .

[0010] In one embodiment, evaluating the impact of each device on the circuit performance includes: Calculating the variance of each device on the circuit performance according to the coefficients of the circuit performance parameter model to evaluate key devices, where the larger the variance value, the greater the impact of the corresponding device on the circuit performance.

[0011] In one embodiment, constructing the circuit performance parameter model based on the sampling matrix and the circuit performance vector includes: using the Orthogonal Matching Pursuit (OMP) algorithm to construct the circuit performance parameter model by iteratively selecting key features and solving linear equations.

[0012] In one embodiment, N random samplings are performed on the process deviation variables corresponding to all devices in the integrated circuit according to the standard normal distribution.

[0013] In one embodiment, the process deviation variables corresponding to all devices in the integrated circuit can be represented as M-dimensional independent random variables , where are independent of each other and satisfy a normal distribution with a mean of and a standard deviation of .

[0014] The embodiment of the present application also provides an integrated circuit process deviation sensitivity analysis device, including: A sampling module that performs N random samplings on the process deviation variables corresponding to all devices in the integrated circuit to obtain a sampling matrix of the process deviation variables; A data construction module that performs circuit simulation according to the sampling matrix to obtain a corresponding circuit performance vector, and forms a data set with the sampling matrix and the circuit performance vector; A model construction module that constructs a circuit performance parameter model based on the sampling matrix and the circuit performance vector; An evaluation module that combines the influences of the process deviation variables belonging to the same device on the circuit performance to evaluate the influence of each device on the circuit performance, An identification module that identifies the key devices with the greatest influence on the circuit performance.

[0015] The embodiment of the present application also provides an electronic device, including a processor, a memory, and a computer program stored on the memory and capable of running on the processor. When the processor executes the computer program, the steps of the above-mentioned integrated circuit process deviation sensitivity analysis method are implemented.

[0016] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned integrated circuit process deviation sensitivity analysis method are implemented.

[0017] Based on the principle of sparse modeling, the embodiment of the present application uses a finite number of simulation points to quickly construct a circuit performance parameter model between the circuit performance and the process deviation variables. At the same time, multiple process deviation variables of the same device are combined, which can effectively identify the key devices that have a significant impact on the circuit performance. Therefore, the parameters of the key devices can be optimized targeted, providing a reliable basis for circuit optimization, thereby improving the reliability and overall performance of the product. It is particularly suitable for dealing with the complex integrated circuit sensitivity analysis problem under high-dimensional process deviation conditions. Description of the Drawings

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0019] Figure 1 is a flowchart of an integrated circuit process deviation sensitivity analysis method according to an embodiment of the present application; Figure 2 is a flowchart of constructing a circuit performance parameter model according to an embodiment of the present application; Figure 3 is a schematic structural diagram of an integrated circuit process deviation sensitivity analysis device according to an embodiment of the present application; Figure 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application. Detailed implementation manners

[0020] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application. It should be noted that the following describes various aspects of embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or this method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0021] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated. Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0022] Currently, in terms of integrated circuit design, in order to improve design accuracy and reduce costs, researchers have proposed a variety of new methods to accurately evaluate the reliability of large-scale integrated circuits, such as applying machine learning to process deviation modeling. However, these methods still have obvious limitations: either they fail to fully utilize the device-level correlation characteristics between process variables, or they lack an effective identification mechanism for key influencing factors in high-dimensional parameter space. In current integrated circuit design practice, how to efficiently complete the sensitivity analysis of high-dimensional process deviation space while ensuring analysis accuracy, and accurately identify the key components that have the greatest impact on circuit performance, is still an important technical problem that needs to be solved urgently.

[0023] Based on this, the present application embodiment proposes a method for analyzing the sensitivity of integrated circuit process deviation, and the process is as follows: Figure 1 As shown in, the details are as follows: In step 101, the process deviation variables corresponding to all devices in the integrated circuit are analyzed. N Random sampling is performed to obtain the sampling matrix of process deviation variables.

[0024] Assume that the integrated circuit contains D Devices, d Devices are recorded as . It is also assumed that the device contains process deviation variables. Then the total number of random process deviation variables in the entire integrated circuit is In an optional embodiment, the process deviation variables corresponding to all devices in these integrated circuits can be expressed as M dimensional independent random variables ,in are independent of each other and satisfy the mean , the standard deviation is In addition, if divided according to the device, x can also be expressed as , the mean of the corresponding variable can be expressed as , the standard deviation is .

[0025] After adopting independent variables with a normal distribution, random sampling can be performed according to a preset sampling standard. N times of random sampling. Specifically, for each variable in the random variable x, based on the known mean of and the standard deviation of N times of random sampling are performed for the normal distribution, and a sampling matrix of process deviation variables is obtained.

[0026] By using normal distribution random variables to characterize process deviation variables and performing sampling based on the normal distribution, the relationship between actual process conditions and circuit performance can be accurately reflected in the high-dimensional parameter space, and it is easier to perform modeling applications in the design of various integrated circuits.

[0027] In step 102, circuit simulation is performed according to the sampling matrix to obtain a corresponding circuit performance vector, and the sampling matrix and the circuit performance vector are used to form a data set. Based on the sampling matrix obtained in step 101, the circuit performance vector of the integrated circuit corresponding to these samples can be obtained through circuit simulation.

[0028] Since the sample data can initially represent a large number of process parameters in the integrated circuit, these sample data and circuit performance data can be used to form a sample set (i.e., data set) required for model training.

[0029] In step 103, a circuit performance parameter model is constructed based on the sampling matrix and the circuit performance vector.

[0030] In an optional embodiment, to make the training model more accurate, the data of the sampling matrix and the circuit performance vector can be normalized first, and the normalization method is as follows: Each item in the circuit performance vector y is normalized to obtain a vector : (1) where and respectively represent the minimum and maximum values of all items in the vector y.

[0031] At the same time, each column in the sampling matrix X is normalized to obtain a matrix under the standard normal distribution: (2) where represents the \(m\)-th column in matrix \(X\). represents matrix in the m column .

[0032] In this embodiment, a method for data normalization is provided. However, in practical applications, other methods can also be used, which are not limited in the embodiments of this application. By performing data normalization processing, data with different dimensions and orders of magnitude can be converted to the same scale, eliminating the dimensionality impact between data features, facilitating comprehensive comparison and evaluation, and thus improving the performance and training efficiency of the model.

[0033] After performing data normalization processing, a circuit performance parameter model can be constructed based on the normalized sampling matrix and the circuit performance vector.

[0034] In an alternative embodiment, the orthogonal matching pursuit (OMP) algorithm can be adopted to construct a circuit performance parameter model by iteratively selecting key features and solving linear equations. For example, based on the normalized vector and matrix A model for circuit performance parameters is constructed through the orthogonal matching pursuit (OMP) algorithm, and its process is referred to Figure 2 as follows: In step 1031: Initialize the model residual vector \(r = , initialize the set S to be empty, which is used to store the indices of the selected features. Initialize the feature coefficient vector M with a length of +1 to be a zero vector, where the first M feature coefficients correspond to process deviation variables, and the last feature coefficient corresponds to the constant term in the model. Given a residual threshold and the maximum number of iterations .

[0035] In step 1032: Add a column of unit vectors (corresponding to the last term in the feature coefficient vector) to the right side of matrix to obtain the extended matrix .

[0036] In step 1033: Calculate the inner product of each column of the extended matrix (i.e., the j -th column of c j ) with the current residual \(r\): (3) In step 1034: The index corresponding to the maximum value in the absolute value of the inner product ​ Add it to the set \(S\). It should be noted that if this step is executed for the first time, the index M +1 is directly added to the set S , that is, the constant term is surely selected in the first round of iteration; in other cases, the index corresponding to the maximum value of the absolute value of the inner product is added to the set S .

[0037] In step 1035: Extract the feature columns corresponding to all the indices in the set \(S\) from the extended matrix to form the matrix . Solve the following linear equation to obtain the corresponding feature coefficients : (4) In step 1036: Update the residual: (5) In step 1037: Judge whether the L2 norm of the residual \(r\) is less than the given threshold , or whether the number of iterations is greater than or equal to . If the L2 norm of the residual \(r\) is less than the given threshold , or the number of iterations is greater than or equal to , then go to step 1038; otherwise, repeat steps 1032 - 1037.

[0038] In step 1038, output the current model coefficients .

[0039] According to reconstruct the model coefficients , where the values of the terms with indices in the set S are determined by the corresponding terms in , and the values of other terms are 0. It can be expressed as , is the normalized model coefficient, c is the coefficient of the constant term. Then the obtained linear model can be expressed as follows: (6) is the \(m\)-th term in the vector . f(x) is the circuit performance index. After arrangement, it can be obtained that: (7) where C is the constant term: (8) Through the above steps, a model with process deviation as the input and circuit performance index as the output can be constructed. In this embodiment, the orthogonal matching pursuit algorithm is taken as an example to illustrate the construction of the circuit performance parameter model. In other embodiments, the circuit performance parameter model of the present application can also be constructed by other common machine learning algorithms, such as neural networks, positive LASSO algorithms, and so on. It should be noted that the processes of the learning models formed by these algorithms and the specific model forms can be implemented with reference to the prior art, and will not be elaborated here.

[0040] In step 104, the influences of the process deviation variables belonging to the same device on the circuit performance are combined to evaluate the influence of each device on the circuit performance.

[0041] In the foregoing description, it is assumed that the integrated circuit contains a total of D devices, and the d th device is denoted as . At the same time, it is assumed that the device contains process deviation variables. It is not difficult to know that in the circuit performance parameter model, the same device will correspond to multiple process deviation variables. In order to accurately evaluate the influence of each device on the circuit performance, it is necessary to combine the influences of the multiple process deviation variables corresponding to the same device on the circuit performance. The method is as follows: First, group the variables in formula (7) based on the device to obtain: (9) where represents the model coefficient corresponding to . Then the influence of the process deviation of the d th device on the circuit performance index of f(x) can be expressed as: , which is the sum of independent normal distributions and is also a random variable with a normal distribution. Its variance is as follows: (10) Then, by comparing , the influence of device d on the circuit performance can be evaluated.

[0042] In summary, according to the coefficient of the circuit performance parameter model, the variance of each device on the circuit performance can be calculated. Among them, the larger the variance value, the greater the influence of the corresponding device on the circuit performance, so as to evaluate the key devices.

[0043] In step 105, identify the device that has the greatest impact on circuit performance. The value of the impact of each device on circuit performance can be calculated through formula 10, and then the values corresponding to all devices are compared, and the device with the largest value is selected, which is the device that has the greatest impact on circuit performance.

[0044] Compared with the prior art, the embodiment of the present application is based on the sparse modeling principle, and uses a finite number of simulation points to quickly construct a circuit performance parameter model between circuit performance and process deviation variables. At the same time, multiple process deviation variables of the same device are merged, which can effectively identify the key devices that have a significant impact on circuit performance. Therefore, the parameters of the key devices can be optimized specifically, which is particularly suitable for dealing with the problem of complex integrated circuit sensitivity analysis under high-dimensional process deviation conditions. This method can efficiently and accurately complete the circuit process deviation sensitivity analysis, and provide clear guidance for circuit design optimization by extracting the key device information that has a significant impact on circuit performance. And while ensuring the analysis accuracy, it significantly improves the calculation efficiency, provides a reliable basis for circuit optimization, and thus improves the reliability and overall performance of the product.

[0045] Based on the same inventive concept, the present application also provides an integrated circuit process deviation sensitivity analysis device. It should be noted that the device exemplified below is an example of the device corresponding to the above method embodiment, and in other device embodiments, the function of the unit module and the setting of the number of modules can be set accordingly according to the foregoing method embodiment. As Figure 3 shown, the integrated circuit process deviation sensitivity analysis device includes: Sampling module 1, which performs N random sampling on the process deviation variables corresponding to all devices in the integrated circuit to obtain a sampling matrix of the process deviation variables; Data construction module 2, which performs circuit simulation according to the sampling matrix to obtain the corresponding circuit performance vector, and forms a data set with the sampling matrix and the circuit performance vector; Model construction module 3, which constructs a circuit performance parameter model based on the sampling matrix and the circuit performance vector; Evaluation module 4, which merges the impacts of the process deviation variables belonging to the same device on circuit performance to evaluate the impact of each device on circuit performance, Identification module 5, which identifies the key device that has the greatest impact on circuit performance.

[0046] In contrast to the prior art, in the embodiment of the present application, the model construction module 3 quickly constructs a circuit performance parameter model between circuit performance and process deviation variables based on the sparse modeling principle by using a finite number of simulation points. The evaluation module 4 merges multiple process deviation variables for the same device and evaluates the impact of each device on the circuit performance, enabling the identification module 5 to effectively identify the key devices that significantly affect the circuit performance, so that the parameters of the key devices can be optimized targeted. This device can efficiently and accurately complete the circuit process deviation sensitivity analysis, and provide clear guidance for circuit design optimization by extracting the key device information that significantly affects the circuit performance.

[0047] As Figure 4 shown, the embodiment of the present application also provides an electronic device, including a processor 6, a memory 7, and a computer program stored on the memory 7 and capable of running on the processor 6. When the processor 6 executes the computer program, the steps of the above-mentioned integrated circuit process deviation sensitivity analysis method are implemented.

[0048] The electronic device in the embodiment of the present application includes at least one processor 6 and a memory 7 communicatively connected to at least one processor 6. Figure 4 Taking one processor 6 as an example for illustration.

[0049] This electronic device may further include: an input device 8 and an output device 9.

[0050] The processor 6, the memory 7, the input device 8, and the output device 9 may be connected through a bus or other means. Figure 4 Taking the connection through a bus as an example.

[0051] The memory 7, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the integrated circuit process deviation sensitivity analysis method in the embodiment of the present application (for example, the sampling module 1, the data construction module 2, the model construction module 3, the evaluation module 4, and the identification module 5 in the appendix). The processor 6 executes various functional applications and data processing of the server by running the non-transitory software programs, instructions, and modules stored in the memory 7, that is, implements the integrated circuit process deviation sensitivity analysis method in the above method embodiment. Figure 3 The processor 6 executes various functional applications and data processing of the server by running the non-transitory software programs, instructions, and modules stored in the memory 7, that is, implements the integrated circuit process deviation sensitivity analysis method in the above method embodiment.

[0052] The memory 7 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created according to the use of the processing device operating on the list items, etc. In addition, the memory 7 may include a high-speed random access memory and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory 7 may optionally include a memory remotely disposed relative to the processor 6, and these remote memories may be connected to the processor 6 for the integrated circuit process deviation sensitivity analysis method through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0053] The input device 8 may receive input digital or character information and generate key signal inputs related to user settings and function controls of the processing device operating on the list items. The output device 9 may include display devices such as a display screen.

[0054] In this embodiment, when one or more modules stored in the memory 7 are executed by the one or more processors 6, the processor 6 executes the integrated circuit process deviation sensitivity analysis method in any of the above method embodiments.

[0055] The above product may execute the method provided in the embodiments of the present application and has corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment may be referred to the method provided in the embodiments of the present application.

[0056] The electronic device in the embodiments of the present invention exists in various forms, including but not limited to: (1) Mobile communication devices: These devices are characterized by having mobile communication functions and mainly aim to provide voice and data communication. Such terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones, etc.

[0057] (2) Ultra-mobile personal computer devices: These devices belong to the category of personal computers, have computing and processing functions, and generally also have the characteristic of mobile Internet access. Such terminals include: PDAs, MIDs, and UMPC devices, etc., such as iPad.

[0058] (3) Portable entertainment devices: These devices can display and play multimedia content. Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, and smart toys and portable vehicle navigation devices.

[0059] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the integrated circuit process deviation sensitivity analysis method described in any one of the embodiments of the present application are implemented.

[0060] It should be noted that the computer storage medium may include, but is not limited to: portable disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories, optical storage devices, magnetic storage devices, or any suitable combination of the above. In a possible implementation manner, the present invention may also provide a form of implementing data processing as a program product, which includes program code. When the program product runs on a terminal device, the program code is used to cause the terminal device to execute several steps of the method described in any one of the foregoing embodiments. As described above, only the specific implementation manners of the present application are provided, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for analyzing the sensitivity of integrated circuit process variations, characterized in that, Including: Perform N random samplings on the process deviation variables corresponding to all devices in the integrated circuit to obtain a sampling matrix of the process deviation variables; Performing circuit simulation according to the sampling matrix to obtain a corresponding circuit performance vector, and forming a data set with the sampling matrix and the circuit performance vector; Constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector; Combining the influences of process deviation variables belonging to the same device on circuit performance to evaluate the influence of each device on circuit performance, Identifying the device that has the greatest influence on circuit performance.

2. The integrated circuit process deviation sensitivity analysis method according to claim 1, wherein The constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector includes: Performing normalization processing on the sampling matrix and the circuit performance vector, Constructing a circuit performance parameter model based on the normalized sampling matrix and circuit performance vector.

3. The integrated circuit process deviation sensitivity analysis method according to claim 2, wherein The performing normalization processing on the sampling matrix and the circuit performance vector includes: For each item in the circuit performance vector perform normalization processing to obtain a vector : wherein and represent the minimum value and the maximum value of all items in the circuit performance vector, respectively Normalizing each column in the sampling matrix simultaneously to obtain a matrix under the standard normal distribution: Among them represents the m th column in the original sampling matrix represents the m th column in the normalized sampling matrix .

4. The integrated circuit process deviation sensitivity analysis method according to claim 1, characterized in that The evaluating the influence of each device on circuit performance includes: Calculating the variance of each device on circuit performance according to the coefficients of the circuit performance parameter model to evaluate key devices, wherein the larger the variance value, the greater the influence of the corresponding device on circuit performance.

5. The integrated circuit process deviation sensitivity analysis method according to claim 1, wherein The constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector includes: adopting the orthogonal matching pursuit (OMP) algorithm to construct the circuit performance parameter model by iteratively selecting key features and solving linear equations.

6. The integrated circuit process deviation sensitivity analysis method according to claim 1, wherein Perform N random samplings on the process deviation variables corresponding to all devices in the integrated circuit according to the standard normal distribution.

7. The integrated circuit process deviation sensitivity analysis method according to claim 1, wherein The process deviation variables corresponding to all devices in the integrated circuit can be expressed as M dimensional independent random variables , where are independent of each other and satisfy a normal distribution with a mean of and a standard deviation of .

8. An integrated circuit process deviation sensitivity analysis device, characterized in that Including: Sampling module, performing N random samplings on the process deviation variables corresponding to all devices in the integrated circuit to obtain a sampling matrix of the process deviation variables; A data construction module that performs circuit simulation according to the sampling matrix to obtain a corresponding circuit performance vector, and forms a data set with the sampling matrix and the circuit performance vector; A model construction module that constructs a circuit performance parameter model based on the sampling matrix and the circuit performance vector; An evaluation module that combines the influences of process deviation variables belonging to the same device on circuit performance to evaluate the influence of each device on circuit performance, An identification module that identifies the key device that has the greatest influence on circuit performance.

9. An electronic device includes a processor, a memory, and a computer program stored on the memory and capable of running on the processor, wherein When the processor executes the computer program, the steps of the integrated circuit process deviation sensitivity analysis method according to any one of claims 1-7 are implemented.

10. A computer-readable storage medium has a computer program stored thereon, wherein When the computer program is executed by a processor, the steps of the integrated circuit process deviation sensitivity analysis method according to any one of claims 1 to 7 are implemented.

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