Packaging test method and system for realizing storage chip

Abstract

The invention provides a packaging test method and system for realizing a storage chip, and relates to the technical field of storage chips, and the method comprises the steps: collecting an appearance image of a to-be-packaged storage chip; classifying the appearance images based on the texture feature difference and the structural feature difference, and determining a storage chip category of the to-be-packaged storage chip; selecting a corresponding packaging type to package the to-be-packaged storage chip according to the type of the storage chip to obtain a target storage chip; performing defect identification on the appearance image of the target storage chip to obtain an appearance defect set comprising different appearance defect categories; performing performance test on the target storage chip through the test equipment to obtain a performance parameter set comprising different performance indexes; calculating a quality score of the target storage chip in combination with the appearance defect set and the performance parameter set; and marking the target storage chip according to the quality score, and completing the packaging test of the to-be-packaged storage chip. And the packaging test automation capability and the product yield are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of storage chips, and particularly to a method and system for implementing the package testing of storage chips. Background Art

[0002] A storage chip refers to an integrated circuit chip used to store digital information (such as program codes, data files, operating states, etc.), and is one of the indispensable core components in electronic devices. According to whether the data can be retained after power-off, it is divided into two categories: non-volatile memories (such as NAND Flash, NOR Flash, EPROM, MRAM) and volatile memories (such as DRAM, SRAM). They are widely used in various electronic systems such as mobile phones, computers, servers, automotive electronics, and Internet of Things terminals.

[0003] The package testing of storage chips is a key link to ensure the reliability, stability, and mass producibility of chips. The packaging process transforms the fragile bare chip into a product that can be used in actual devices, and the testing is used to screen out chips with abnormal functions or packaging defects. Through package testing, not only problems such as solder ball defects, package cracks, and performance anomalies can be found, but also chip grading management can be realized, the yield rate can be improved, defective products can be prevented from flowing into the market, and the data security and operation stability of terminal devices can be ensured. With the improvement of chip integration and the complexity of application environments, the importance of package testing in modern chip manufacturing is increasing day by day.

[0004] However, the existing methods for package testing of storage chips have problems of low automation and reliance on manual identification and detection, which easily lead to incorrect identification of chip categories and inappropriate selection of packaging processes, thereby causing package failures, performance anomalies, and detection misjudgments. This not only affects the chip yield rate and testing accuracy, but also increases the probability of rework and manufacturing costs, reduces the packaging efficiency and production line coherence, and it is difficult to meet the requirements of large-scale automatic package testing. Summary of the Invention

[0005] In view of the above deficiencies of the prior art, the purpose of the embodiments of the present invention is to provide a method for implementing the package testing of storage chips, which can solve the technical problems existing in the prior art that the existing methods for package testing of storage chips have low automation and rely on manual identification and detection, easily lead to incorrect identification of chip categories and inappropriate selection of packaging processes, thereby causing package failures, performance anomalies, and detection misjudgments, not only affecting the chip yield rate and testing accuracy, but also increasing the probability of rework and manufacturing costs, reducing the packaging efficiency and production line coherence, and it is difficult to meet the requirements of large-scale automatic package testing.

[0006] In the first aspect of the embodiments of the present invention, a method for implementing the package testing of storage chips is proposed, including:

[0007] S1: Collect the appearance image of the storage chip to be encapsulated and stored;

[0008] S2: Classify the appearance image based on the texture feature difference and the structure feature difference, and determine the storage chip category of the storage chip to be encapsulated;

[0009] S3: Select the corresponding packaging type according to the storage chip category to package the storage chip to be encapsulated, and obtain the target storage chip;

[0010] S4: Collect the appearance image of the target storage chip;

[0011] S5: Identify the defects in the appearance image of the target storage chip to obtain an appearance defect set including different appearance defect categories;

[0012] S6: Perform performance testing on the target storage chip through a testing device to obtain a performance parameter set including different performance indicators;

[0013] S7: Combine the appearance defect set and the performance parameter set to calculate the quality score of the target storage chip;

[0014] S8: Mark the target storage chip according to the quality score to complete the packaging test of the storage chip to be encapsulated.

[0015] In the second aspect of the embodiments of the present invention, a packaging test system for implementing a storage chip is proposed, including: a processor and a memory;

[0016] The memory stores a program or instruction that can run on the processor. When the program or instruction is executed by the processor, the steps of the method for implementing the packaging test of the storage chip as described in the first aspect are realized.

[0017] The beneficial effects brought by the technical solutions provided by the embodiments of the present invention at least include:

[0018] In the embodiments of the present invention, through the automatic classification of storage chips based on texture feature differences and structure feature differences, the problem of relying on manual identification in traditional storage chip packaging tests is effectively solved, and the accuracy and efficiency of classification are significantly improved. This solution extracts the frequency-domain texture features and polar coordinate structure features of the image, avoids misjudgment caused by human factors, ensures the correct matching of the packaging process, and thus reduces the occurrence of problems such as packaging failure and performance anomalies. At the same time, the entire process realizes an automatic closed-loop from image acquisition, chip category identification, packaging selection, defect detection, performance testing to quality scoring, reduces the rework rate and production cost, improves production efficiency, good product rate and test consistency, and meets the requirements of large-scale and high-efficiency packaging tests. Description of the Drawings

[0019] The accompanying drawings are only for the purpose of showing specific embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 is a schematic flowchart of a method for implementing the package test of a storage chip provided by an embodiment of the present invention;

[0021] Figure 2 is a schematic structural diagram of a system for implementing the package test of a storage chip provided by an embodiment of the present invention. Detailed Embodiments

[0022] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0023] The method for implementing the package test of a storage chip provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0024] Refer to the attached drawings of the specification Figure 1 , which shows a schematic flowchart of a method for implementing the package test of a storage chip provided by an embodiment of the present invention.

[0025] The embodiment of the present invention provides a method for implementing the package test of a storage chip, which may include the following steps:

[0026] S1: Collect the appearance image of the storage chip to be packaged.

[0027] Among them, the appearance image refers to the image of the externally visible part of the storage chip obtained by an image acquisition device such as an industrial camera, and usually includes the package structure, surface texture, pin layout, silk screen information, etc. of the chip. This image reflects the external physical form of the chip before packaging and is the basic data for subsequent image recognition and classification.

[0028] S2: Classify the appearance image based on the texture feature difference and the structure feature difference to determine the storage chip category of the storage chip to be packaged.

[0029] Among them, the texture feature difference refers to the differences in the gray-scale distribution, texture direction, frequency composition, etc. of the chip surface image. Through frequency-domain analysis (such as Fourier transform), microscopic texture features inherent in different chip categories, such as pad edges, silk-screen details, and surface material roughness, can be extracted. The structural feature difference refers to the differences in the spatial distribution, symmetry, and arrangement of key elements (such as pins, solder balls, device markings, etc.) in the chip image. Through methods such as polar coordinate modeling and angular autocorrelation analysis, features reflecting the packaging structure rules can be extracted to distinguish the packaging formats and types.

[0030] By extracting the differences in texture and structural features in the chip appearance image, accurate automatic identification of chip categories can be achieved, significantly reducing the manual misjudgment rate and improving the accuracy of packaging process matching and the overall packaging efficiency.

[0031] In a possible implementation manner, the storage chip categories include: NAND flash memory, NOR flash memory, dynamic random access memory, static random access memory, electrically erasable programmable memory, magnetoresistive memory, three-dimensional stacked NAND flash memory, embedded flash memory module, ultraviolet erasable read-only memory, and mask read-only memory. S2 specifically includes:

[0032] S201: Convert the appearance image into a grayscale image.

[0033] S202: Use the process feature vector describing the texture features of the appearance image established based on the gray-scale Figure 2 order derivative.

[0034] In a possible implementation manner, S202 specifically includes:

[0035] S2021: Extract the texture weighted spectrum of the appearance image using the adaptive band weight term based on the gray-scale Figure 2 order derivative.

[0036] The calculation formula of the texture weighted spectrum is specifically:

[0037]

[0038] Among them, represents the grayscale image coordinate, represents the grayscale of the grayscale image Figure 2 order derivative, represents the statistical mean of the grayscale Figure 2 order derivative, e represents the natural constant, represents pi, represents the two-dimensional Fourier transform basis function, represents the adaptive band weight term, i represents the imaginary unit, represents the frequency coordinate, Represents the texture weighted spectrum.

[0039] Among them, the introduction of the adaptive frequency band weight term makes the weight of the high-frequency part (texture edge) large, and the low-frequency part (illumination change) is suppressed.

[0040] S2022: Construct a process feature vector with high-frequency energy concentration and texture weighted spectrum entropy based on the texture weighted spectrum.

[0041] The formula form of the process feature vector is specifically:

[0042]

[0043]

[0044] Among them, represents the process feature vector, represents the frequency threshold used to divide the high-frequency frequency and the low-frequency frequency, represents the high-frequency energy concentration, represents the texture weighted spectrum entropy, and log represents the logarithmic function.

[0045] It should be noted that those skilled in the art can set the size of the frequency threshold according to actual needs, and the present invention does not limit this here. Optionally, the frequency threshold can be set to 60% or more of the Nyquist frequency (the maximum resolvable frequency) of the appearance image.

[0046] Specifically, step S2021 constructs a texture weighted spectrum by introducing an adaptive frequency band weight term based on the second derivative in the Fourier transform of the grayscale image, effectively enhancing the expression ability of the high-frequency part (such as microscopic structures like pad edges and silk-screen lines) in the image, while suppressing the illumination interference and background clutter brought by the low-frequency part, and improving the extraction accuracy of texture features. Subsequently, in step S2022, the high-frequency energy concentration and texture spectrum entropy are calculated based on this spectrum, and a feature vector reflecting the differences in chip process features is constructed. This process not only improves the recognition ability of chip microscopic process differences, but also significantly enhances the robustness of the classification model to image quality changes, contributing to the realization of stable and high-precision chip category recognition.

[0047] S203: Establish a structural feature vector for eliminating position sensitivity through a polar coordinate transformation algorithm.

[0048] In a possible implementation manner, S203 specifically includes:

[0049] S2031: Use the center of the grayscale image as the pole and map the Cartesian coordinates to polar coordinates.

[0050] S2032: Perform grayscale integration on the circumcircle of the pole points to obtain the joint radial - angle distribution:

[0051]

[0052] Among them, and represent the polar - coordinate radius and the polar - coordinate angle respectively, represents the joint radial - angle distribution related to the polar coordinate , represents the rotation - angle variable, represents the cosine function, represents the polar coordinate at the grayscale value.

[0053] Effectively solve the interference caused by slight rotation and displacement of the image, characterize the distribution complexity of the marked elements along the radius direction, and resist radial deformation.

[0054] S2033: Calculate the radial distribution entropy of the grayscale image at different polar - coordinate radii.

[0055] The specific calculation formula of the radial distribution entropy is:

[0056]

[0057] Among them, represents the grayscale response probability at the polar - coordinate radius , represents the entropy value of the grayscale change on different polar - coordinate radii.

[0058] It can be understood that the polar - coordinate radius can take finite discrete values according to actual needs.

[0059] S2034: Combine the joint radial - angle distribution to calculate the angular autocorrelation value of the grayscale image at different discrete polar - coordinate angles.

[0060] The specific calculation formula of the angular autocorrelation value is:

[0061]

[0062] Among them, represents the angular autocorrelation value when the polar - coordinate angle offset is , represents the joint radial - angle distribution related to the polar coordinate , represents taking the expected value.

[0063] Among them, taking the expected value means taking the average of all polar - coordinate angles and / or polar - coordinate radii, and the purpose is to obtain the average correlation degree under a certain angle offset in the whole image.

[0064] S2035: Establish a structural feature vector based on the radial distribution entropy and the angular autocorrelation value.

[0065] The calculation formula of the structural feature vector is specifically as follows:

[0066]

[0067] Wherein, represents the structural feature vector, represents taking the .

[0068] Specifically, the whole process constitutes a complete process of structural feature extraction, aiming to enhance the robust recognition ability of the chip image structure information through polar coordinate modeling. First, in S2031, the chip grayscale image is converted from Cartesian coordinates to polar coordinates, with the image center as the pole, which is convenient for capturing the structural rules symmetrically distributed around the chip center and effectively resisting the interference caused by image rotation and position offset. S2032 constructs a radial-angular joint distribution function by performing grayscale integration on the pole circumference to depict the joint characteristics of grayscale changes in space. S2033 further calculates the grayscale response entropy at different radii to reflect the complexity of the structure in the radial direction. S2034 then uses angular autocorrelation analysis to obtain the symmetry distribution of the image in different directions. Finally, in S2035, the radial distribution entropy and the maximum angular autocorrelation value are combined to construct a stable and distinguishable structural feature vector. The whole process realizes the quantitative representation from local structural changes to global distribution patterns, enhances the spatial identification ability and anti-interference ability of storage chip category recognition, and provides a solid structural information basis for accurately matching packaging processes.

[0069] S204: Obtain the process standard template vectors and structural standard template vectors of different storage chip categories through orthogonal training.

[0070] Wherein, orthogonal training means that in the training stage, for different storage chip categories, a set of feature vector sets with good discrimination are constructed, so that different categories are as orthogonal as possible in the feature space (that is, not similar to each other and with low correlation), which can improve the discrimination ability of the classification model for different categories and reduce the misjudgment caused by feature overlap. The process standard template vector refers to the representative process feature vector obtained through training in the texture feature space for each type of storage chip, reflecting the typical process image features of this type of chip. The structural standard template vector refers to the standard template trained for each type of chip in the structural feature space to represent its typical structural layout features.

[0071] It should be noted that through the orthogonal training method, standard template vectors of different storage chip categories are established in the two feature spaces of texture and structure respectively, so that each type of chip has good separability and distinguishability in the feature dimension. This process effectively improves the accuracy and robustness of subsequent classification, avoids misjudgment caused by feature confusion, ensures that the chip category recognition is more stable and reliable, and helps the precise matching and automated execution of subsequent packaging processes.

[0072] S205: Based on the relative relationships between the process feature vector and the process standard template vector, and between the structural feature vector and the structural standard template vector, classify the appearance image based on the principle of orthogonal projection to obtain the storage chip category of the storage chip to be packaged.

[0073] The classification formula for the storage chip category is specifically as follows:

[0074]

[0075] Wherein, represents the process standard template vector of the k-th type of storage chip, represents the structural standard template vector of the k-th type of storage chip, represents the fusion weight, represents the storage chip category number, represents taking k under the maximum function value as the storage chip category number C for output.

[0076] Optionally, the fusion weight can be set to 0.5 or other values.

[0077] Specifically, by calculating the similarity between the process feature vector of the chip to be measured and the process standard template vectors of each category, and the matching degree between the structural feature vector and the structural standard template vectors, and performing weighted scoring in combination with the fusion weight, the automatic classification of the appearance image is realized by using the principle of orthogonal projection. This process evaluates the matching degree separately in two independent feature spaces, avoids misjudgment caused by feature coupling, significantly improves the accuracy and robustness of classification, ensures the scientific reliability of chip category recognition, and lays a foundation for the precise matching of subsequent packaging processes.

[0078] It should be noted that through the orthogonal projection classification method, combined with the second derivative of the grayscale image and the polar coordinate structure feature, the texture and structure features of the storage chip are accurately extracted. Through the standardized template training of the process and structural features of different storage chip categories, it is ensured that the appearance images of each type of storage chip can be accurately classified and the appropriate packaging process can be selected. This method greatly improves the classification accuracy, reduces the manual recognition error, and optimizes the packaging process through automated classification and process matching, improving the production efficiency, yield rate and packaging consistency.

[0079] S3: Select the corresponding packaging type according to the storage chip category to package the storage chip to be packaged, and obtain the target storage chip.

[0080] It can be understood that according to the identified storage chip category, the corresponding packaging type (such as BGA, TSOP, WLCSP, etc.) is automatically matched, and the corresponding packaging process flow is executed to ensure a high degree of adaptation between the chip structure, electrical interface and packaging form. This process can avoid welding failures, structural damages or electrical defects caused by incorrect selection of the packaging type, improve the packaging success rate and product consistency, and at the same time realize production line automation, reducing human intervention and rework costs.

[0081] In the actual application process, after determining the packaging process, the packaging can be carried out in the conventional way, that is, in the preset order. It is also possible to re-identify the sub-category of the storage chip in a similar way to the identification method of identifying the storage chip category in step S2, and automatically select the packaging process for each step according to the current state of the storage chip. Specifically: First, use the current state of the storage chip as a feature and the corresponding packaging process label as a category label to re-perform the orthogonal training in step S2, obtain the process standard template vectors and structure standard template vectors corresponding to the sub-categories under different storage chip categories, and re-identify the sub-category, that is, the current state of the storage chip, based on the obtained template vectors. Then, automatically determine the packaging process to be selected according to the sub-category, and then perform the packaging according to the selected packaging process. Among them, the packaging process includes chip dicing, solder ball mounting, chip bonding, packaging substrate, thermal pressing and sealing. Each time a packaging process is performed, it is identified once until the packaging is completed.

[0082] It should be noted that this process realizes a high degree of automation and flexibility by automatically selecting the packaging process for each step according to the current state of the storage chip and the sub-category of the packaging process. The selection of each packaging process is based on the previous state recognition, ensuring the matching of the packaging quality and process in each link, effectively avoiding packaging failures caused by improper process selection in the traditional fixed process, improving the packaging accuracy, flexibility and production efficiency, and reducing the rework rate and human intervention.

[0083] In a possible implementation manner, the packaging types include TSOP packaging type, BGA packaging type, WLCSP packaging type, eMMC module-level packaging type and UFS module-level packaging type.

[0084] It can be understood that by accurately matching the storage chip category with the corresponding packaging type, the most suitable packaging form can be selected according to the structural characteristics and application requirements of different chips, which helps to improve the packaging compatibility, reliability and production efficiency.

[0085] S4: Collect the appearance image of the target storage chip.

[0086] S5: Identify defects in the appearance image of the target storage chip to obtain an appearance defect set including different appearance defect categories.

[0087] It should be noted that by collecting the appearance image of the target storage chip after packaging and automatically analyzing it using an image recognition algorithm, different types of appearance defects such as packaging cracks, missing solder balls, blurred silk printing, and oxidation spots are identified, and a corresponding appearance defect set is generated. This process avoids problems such as missed inspections and misjudgments in manual inspections, improves the accuracy and stability of defect identification, helps to detect packaging quality problems at an early stage, and improves the overall product yield and detection efficiency.

[0088] In a possible implementation manner, the appearance defect categories include packaging cracks, missing solder balls, blurred silk printing, and oxidation spots. S5 specifically includes:

[0089] S501: Convert the appearance image of the target storage chip into a grayscale image of the appearance image of the target storage chip.

[0090] S502: Establish a process feature vector and a structure feature vector of the grayscale image of the appearance image of the target storage chip respectively.

[0091] S503: Obtain a process standard template vector and a structure standard template vector of different appearance images of the target storage chip through orthogonal training.

[0092] S504: Classify the appearance image of the target storage chip based on the principle of orthogonal projection to obtain the appearance defect categories of the appearance image of the target storage chip, where each appearance defect category constitutes an appearance defect set.

[0093] It should be noted that by converting the appearance image of the target storage chip into a grayscale image and extracting its process and structure feature vectors, combining orthogonal training to generate a standard defect template, and using the orthogonal projection classification method to realize the automatic identification and classification of typical appearance defects such as packaging cracks, missing solder balls, blurred silk printing, and oxidation spots. This process not only realizes the accurate detection and classification of appearance defects, but also effectively makes up for the blind area of traditional testing that only focuses on electrical parameters by introducing the linkage analysis of appearance factors and performance test results, improving the comprehensiveness, accuracy of the overall packaging test, and the reliability of defect screening.

[0094] S6: Perform performance testing on the target storage chip through a testing device to obtain a set of performance parameters including different performance indicators.

[0095] It should be noted that the electrical performance of the packaged target memory chip is tested by automatic testing equipment to obtain multiple performance indicators including read and write speed, bit error rate, power consumption, bad block rate, etc., to form a performance parameter set to ensure that the chip meets the functional and stability requirements before leaving the factory, thereby improving the test consistency and quality control level.

[0096] In a possible implementation manner, the performance indicators include read and write speed, bit error rate, power consumption and bad block rate. The performance test of the target storage chip by the test equipment in S6 is specifically:

[0097] The target memory chip is tested for performance using ATE testing equipment.

[0098] Among them, ATE (Automatic Test Equipment) refers to automated electronic testing equipment, which is used to perform batch tests on the functions, electrical properties, timing and performance of semiconductor chips (such as memory chips). Using ATE testing equipment to perform performance tests on target memory chips can efficiently obtain key performance indicators such as read and write speed, bit error rate, power consumption and bad block rate, and realize batch, standardized and high-precision electrical verification.

[0099] S7: Calculate the quality score of the target memory chip by combining the appearance defect set and the performance parameter set.

[0100] It should be noted that by comprehensively analyzing the appearance defect set and performance parameter set obtained in the early stage, the influence weights are assigned to various defects and performance indicators according to the preset quality assessment rules, and the comprehensive quality score of the target chip is calculated. This process can realize the linkage evaluation of appearance and performance factors, avoid misclassification or missed judgment caused by single-dimensional judgment, improve the objectivity and accuracy of chip grading, and provide a reliable basis for subsequent factory screening and product traceability.

[0101] In a possible implementation, S7 specifically includes:

[0102] S701: Mark different appearance defect categories and impact scores of different performance indicators according to the memory chip quality rating rules.

[0103] Among them, the storage chip quality rating rules are preset rules set according to the company's own situation, that is, a standard system for comprehensive quality scoring and grading of single chips in the chip manufacturing and packaging testing process. The core is to set quantifiable impact scores for different defect types and performance deviations, and finally obtain the total score through weighted summation, which is used for good product screening, graded shipment or failure analysis.

[0104] S702: Calculate the quality score of each target storage chip according to the impact score.

[0105] The specific calculation method of the quality score is as follows:

[0106]

[0107] Among them, represents the influence score of the jth influencing factor, where the influencing factors include various performance indicators and various appearance defect categories. represents the quality score.

[0108] It can be understood that by converting the appearance defects and performance test results of the chip into standardized influence scores and accumulating them to obtain the quality score, the quantitative evaluation of the chip quality is realized. Compared with the traditional manual judgment method, this method is more objective, controllable and convenient for batch processing, which helps to accurately screen out good products, control the outgoing quality, and improve the level of automatic grading and product consistency management.

[0109] S8: Mark the target storage chip according to the quality score, and complete the packaging test of the storage chip to be packaged.

[0110] In the actual application process, this method is based on the appearance image, extracts texture and structure features to achieve accurate identification of chip categories, and dynamically matches the packaging process according to the chip status during the packaging process to ensure process adaptability and flexibility. After packaging, complete quality parameters are obtained through automatic vision inspection and electrical testing, and then the chip quality score is obtained through fusion analysis to achieve efficient, accurate and closed-loop quality control. The overall solution significantly improves the packaging success rate, test consistency and good product rate, reduces rework and manual dependence, and is applicable to large-scale and high-reliability chip manufacturing scenarios.

[0111] The beneficial effects brought by the technical solution provided by the embodiment of the present invention at least include:

[0112] In the embodiment of the present invention, through the automatic classification of storage chips based on texture feature differences and structure feature differences, the problem of relying on manual identification in the traditional packaging test of storage chips is effectively solved, and the accuracy and efficiency of classification are significantly improved. This solution extracts the frequency-domain texture features and polar coordinate structure features of the image, avoids misjudgment caused by human factors, ensures the correct matching of the packaging process, and thus reduces the occurrence of problems such as packaging failure and performance anomalies. At the same time, the entire process realizes an automatic closed-loop from image acquisition, chip category identification, packaging selection, defect detection, performance testing to quality scoring, reduces the rework rate and production cost, improves production efficiency, good product rate and test consistency, and meets the requirements of large-scale and high-efficiency packaging testing.

[0113] Refer to the attached Figure 2 illustrates a schematic structural diagram of a packaging test system for implementing storage chips provided by an embodiment of the present invention.

[0114] An embodiment of the present invention provides a packaging and testing system 20 for implementing a storage chip, including: a processor 201 and a memory 202;

[0115] The memory 202 stores programs or instructions that can run on the processor 201. When the programs or instructions are executed by the processor 201, the steps of the above-mentioned method for implementing the packaging and testing of the storage chip are realized, and the same technical effects can be achieved. To avoid repetition, the present invention will not be described in detail.

[0116] It should be understood that the processor 201 in the embodiment of the present invention may be a central processing unit (CPU), and this processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or this processor may also be any conventional processor, etc.

[0117] It should also be understood that the memory 202 in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synch link dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM).

[0118] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that contains one or more collections of available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, or magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0119] It should be understood that in various embodiments of the present invention, the magnitudes of the sequence numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0120] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0121] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the devices, apparatuses, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0122] In several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0123] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0124] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0125] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0126] The embodiment of the present invention provides a readable storage medium including: programs or instructions are stored on the readable storage medium, and when the programs or instructions are executed by a processor, the steps for implementing the encapsulation and testing method of the storage chip as described above are realized, and the same technical effects can be achieved. To avoid repetition, the present invention will not be described in detail.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A packaging test method for implementing a storage chip, characterized in that, Including: S1: Collect the appearance image of the storage chip to be encapsulated and stored; S2: Classify the appearance image based on the texture feature difference and the structure feature difference, and determine the storage chip category of the storage chip to be encapsulated and stored; S3: Select the corresponding packaging type according to the storage chip category to package the storage chip to be encapsulated and stored, and obtain the target storage chip; S4: Collect the appearance image of the target storage chip; S5: Perform defect recognition on the appearance image of the target storage chip to obtain an appearance defect set including different appearance defect categories; S6: Perform performance testing on the target storage chip through a testing device to obtain a performance parameter set including different performance indicators; S7: Combine the appearance defect set and the performance parameter set to calculate the quality score of the target storage chip; S8: Mark the target storage chip according to the quality score to complete the packaging test of the storage chip to be encapsulated and stored.

2. The encapsulation test method for implementing a storage chip according to claim 1, wherein, The storage chip category includes: NAND flash memory, NOR flash memory, dynamic random access memory, static random access memory, electrically erasable programmable memory, magnetoresistive memory, 3D stacked NAND flash memory, embedded flash memory module, ultraviolet erasable read-only memory, and mask read-only memory; The S2 specifically includes: S201: Convert the appearance image into a grayscale image; S202: Use the process feature vector that describes the texture features of the appearance image established based on the second derivative of the grayscale image; S203: Establish a structure feature vector for eliminating position sensitivity through a polar coordinate transformation algorithm; S204: Obtain the process standard template vector and the structure standard template vector of different storage chip categories through orthogonal training; S205: Combine the relative relationship between the process feature vector and the process standard template vector, and the relative relationship between the structure feature vector and the structure standard template vector, and classify the appearance image based on the principle of orthogonal projection to obtain the storage chip category of the storage chip to be encapsulated and stored.

3. The encapsulation test method for implementing a storage chip according to claim 2, wherein The S202 specifically includes: S2021: Extract the texture weighted spectrum of the appearance image using the adaptive band weight term based on the second derivative of the grayscale image; S2022: Establish a process feature vector with high-frequency energy aggregation degree and texture weighted spectrum entropy based on the texture weighted spectrum.

4. The encapsulation test method for implementing a storage chip according to claim 2, wherein, The S203 specifically includes: S2031: Map the Cartesian coordinates to polar coordinates with the center of the grayscale image as the pole; S2032: Perform grayscale integration on the pole circumference to obtain the radial angle joint distribution; S2033: Calculate the radial distribution entropy of the grayscale image at different polar coordinate radii; S2034: Combine the radial angle joint distribution to calculate the angle autocorrelation value of the grayscale image at different discrete polar coordinate angles; S2035: Establish the structure feature vector according to the radial distribution entropy and the angle autocorrelation value.

5. The encapsulation test method for implementing a storage chip according to claim 1, wherein The packaging types include TSOP packaging type, BGA packaging type, WLCSP packaging type, eMMC module-level packaging type, and UFS module-level packaging type.

6. The encapsulation test method for implementing a storage chip according to claim 1, wherein The appearance defect categories include packaging cracks, missing solder balls, blurred silk printing, and oxidation spots; the specific steps of S5 are as follows: S501: Convert the appearance image of the target storage chip into a grayscale image of the appearance image of the target storage chip; S502: Establish the process feature vector and the structural feature vector of the grayscale image of the appearance image of the target storage chip respectively; S503: Obtain the process standard template vector and the structural standard template vector of different appearance images of the target storage chip through orthogonal training; S504: Classify the appearance image of the target storage chip based on the principle of orthogonal projection to obtain the appearance defect category of the appearance image of the target storage chip, where each of the appearance defect categories constitutes the appearance defect set.

7. The encapsulation test method for implementing a storage chip according to claim 1, wherein The performance indicators include read / write speed, error rate, power consumption, and bad block rate; the performance test of the target storage chip by the test device in S6 is specifically: Perform a performance test on the target storage chip through an ATE test device.

8. The encapsulation test method for implementing a storage chip according to claim 1, wherein The specific steps of S7 are as follows: S701: Mark the influence scores of different appearance defect categories and different performance indicators according to the storage chip quality rating rules; S702: Calculate the quality scores of each of the target storage chips according to the influence scores.

9. A packaging and testing system for implementing a storage chip, characterized in that, Including: A processor and a memory; The memory stores a program or instruction that can run on the processor, and when the program or instruction is executed by the processor, the steps of the method for implementing the package test of the storage chip as described in any one of claims 1 to 8 are realized.

10. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, the steps of the method for implementing the package test of the storage chip as described in any one of claims 1 to 8 are realized.

Images