Delay power-down control circuit, memory chip and reset method thereof

Abstract

The invention provides a time-delay power-down control circuit, a memory chip and a reset method thereof, and the time-delay power-down control circuit comprises a time-delay power-down module which receives an initial reset signal and carries out the time-delay operation of the initial reset signal to generate a time-delay reset signal; and the power failure control module receives the initial reset signal and the delay reset signal, and generates a chip reset signal based on the initial reset signal and the delay reset signal. According to the invention, the problem of false reset caused by power jitter in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memories, and particularly to a delay power-off control circuit, a memory chip, and a reset method thereof. Background Art

[0002] A traditional reset circuit realizes the reset of a chip by a power-off detection circuit that monitors the power supply voltage in real time when the chip is operating normally. For a memory chip, operations such as reading, writing, and erasing will instantaneously generate a large current, resulting in a sudden drop in the power supply voltage. Although the time of the sudden drop in the power supply voltage is short and can quickly recover to the original level, it may still trigger the power-off detection circuit, thereby causing the chip to reset; this kind of reset situation belongs to misreset. Generally, it is necessary to eliminate the misreset problem caused by power supply jitter.

[0003] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a delay power-off control circuit, a memory chip, and a reset method thereof, which are used to solve the problem of misreset caused by power supply jitter in the prior art.

[0005] To achieve the above object and other related objects, the present invention provides a delay power-off control circuit applicable to a memory chip, including:

[0006] A delay power-off module, which receives an initial reset signal and performs a delay operation on the initial reset signal to generate a delayed reset signal;

[0007] A power-off control module, which receives the initial reset signal and the delayed reset signal, and generates a chip reset signal based on the initial reset signal and the delayed reset signal.

[0008] Optionally, the delay power-off module is implemented by a D flip-flop.

[0009] Optionally, the delay power-off module includes N D flip-flops, where N is a natural number greater than 1; among them, the clock terminals of the N D flip-flops are all connected to a clock signal, the output terminal of the previous D flip-flop is connected to the data terminal of the next D flip-flop, the data terminal of the first D flip-flop receives the initial reset signal, and the output terminal of the Nth D flip-flop outputs the delayed reset signal.

[0010] Optionally, the value of N is greater than or equal to 10 and less than or equal to 20.

[0011] Optionally, the power-down control module performs a logical operation on the initial reset signal and the delayed reset signal to generate a valid chip reset signal when both the initial reset signal and the delayed reset signal are valid.

[0012] Optionally, the initial reset signal, the delayed reset signal, and the chip reset signal are all active low, and the power-down control module is implemented by an OR gate.

[0013] The present invention also provides a memory chip, comprising:

[0014] A power-down detection circuit that, after the memory chip is powered on, monitors the value of the power supply voltage in real time and generates an initial reset signal based on the comparison result between the power supply voltage value and the power-down detection threshold;

[0015] The delayed power-down control circuit as described in any one of the above, connected to the power-down detection circuit; a control logic circuit, respectively connected to the power-down detection circuit and the delayed power-down control circuit, determines a true reset based on the initial reset signal and the chip reset signal, and performs a reset operation when it is determined to be a true reset.

[0016] Optionally, it further includes a clock circuit, connected to the delayed power-down control circuit, for providing a clock signal.

[0017] Optionally, it further includes a power supply circuit, connected to the power-down detection circuit, for outputting a power supply voltage.

[0018] The present invention also provides a reset method for a memory chip as described in any one of the above, comprising:

[0019] Power on the memory chip;

[0020] Determine whether the initial reset signal is valid;

[0021] If the initial reset signal is invalid, the memory chip operates normally. If the initial reset signal is valid, continue to determine whether the chip reset signal is valid;

[0022] If the chip reset signal is invalid and it is determined to be a false reset, the memory chip operates normally. If the chip reset signal is valid and it is determined to be a true reset, perform a reset operation on the memory chip.

[0023] As described above, the power-down delay control circuit, memory chip and reset method thereof of the present invention combine the initial reset signal and the chip reset signal through the design of the power-down delay module and the power-down control module to perform true and false reset judgments and trigger chip reset during true reset, which can effectively eliminate the false reset caused by transient voltage drop of the power supply and is beneficial to improving the reliability of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It shows a schematic structural diagram of the power-down delay control circuit in the first embodiment of the present invention.

[0025] Figure 2 It shows a schematic structural diagram of the memory chip in the second embodiment of the present invention.

[0026] Figure 3 It shows a flowchart of the memory chip reset method in the second embodiment of the present invention.

[0027] Figure 4 It shows a waveform diagram of relevant signals of the memory chip in the second embodiment of the present invention.

[0028] DESCRIPTION OF REFERENCE NUMERALS

[0029] 100 Memory chip

[0030] 110 Power-down delay control circuit

[0031] 111 Power-down delay module

[0032] 112 Power-down control module

[0033] 120 Power-down detection circuit

[0034] 121 Sampling module

[0035] 122 Comparison module

[0036] 130 Control logic circuit

[0037] 140 Clock circuit

[0038] 150 Power supply circuit DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please refer to Figures 1 to 4It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The form, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0041] Embodiment 1

[0042] As Figure 1 shown, this embodiment provides a delay power-off control circuit 110, including a delay power-off module 111 and a power-off control module 112; the delay power-off control circuit 110 of this embodiment is applicable to the memory chip 100, and can effectively eliminate the misreset situation caused by the transient voltage of the power supply being too low, which is beneficial to improving the reliability of the memory chip 100.

[0043] The delay power-off module 111 receives the initial reset signal POR_RST and performs a delay operation on the initial reset signal POR_RST to generate a delayed reset signal POR_RST_DLY.

[0044] In one example, the delay power-off module 111 is implemented by a D flip-flop. Of course, other module structures that can implement signal delay are also feasible, and no limitation is imposed thereon. In a specific implementation manner, the delay power-off module 111 includes N D flip-flops, where N is a natural number greater than 1; among them, the clock terminals of the N D flip-flops are all connected to the clock signal CLK, the output terminal of the previous D flip-flop is connected to the data terminal of the next D flip-flop, the data terminal of the first D flip-flop receives the initial reset signal POR_RST, and the output terminal of the Nth D flip-flop outputs the delayed reset signal POR_RST_DLY. Taking N equal to 3 as an example, the clock terminal CK of the first D flip-flop is connected to the clock signal CLK, the data terminal D of the first D flip-flop receives the initial reset signal POR_RST, the output terminal Q of the first D flip-flop is connected to the data terminal D of the second D flip-flop, the clock terminal CK of the second D flip-flop is connected to the clock signal CLK, the output terminal Q of the second D flip-flop is connected to the data terminal D of the third D flip-flop, the clock terminal CK of the third D flip-flop is connected to the clock signal CLK, and the output terminal Q of the third D flip-flop outputs the delayed reset signal POR_RST_DLY. It should be noted that the clock signal CLK is usually provided by the clock circuit 140 inside the memory chip 100.

[0045] In fact, in the case of a false reset, the initial reset signal POR_RST becomes valid, but the duration for which the initial reset signal POR_RST remains valid is not very long, usually within 600 ns. Therefore, when performing a delay operation on the initial reset signal POR_RST, the delay time should be ensured to be greater than 600 ns, and usually the designed delay time is greater than 1 μs to avoid the overlapping of the valid levels of the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY in the case of a false reset. In an application, the delay time is designed by setting the value of N, and usually the value of N is designed to be greater than or equal to 10 and less than or equal to 20, that is, 10 ≤ N ≤ 20. Herein, the initial reset signal POR_RST is active low, that is to say, the valid level of the initial reset signal POR_RST is low; the delayed reset signal POR_RST_DLY is also active low, that is to say, the valid level of the delayed reset signal POR_RST_DLY is also low.

[0046] The power-down control module 112 receives the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY, and generates a chip reset signal CHIP_RST based on the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY.

[0047] In an example, the power-down control module 112 performs a logical operation (such as a logical OR operation) on the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY to generate a valid chip reset signal CHIP_RST when both the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY are valid; since both the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY are active low, and the chip reset signal CHIP_RST is also active low, a low-level chip reset signal CHIP_RST is generated when both the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY are low. In a specific implementation manner, the power-down control module 112 is implemented by an OR gate, wherein the first input terminal of the OR gate receives the initial reset signal POR_RST, the second input terminal of the OR gate receives the delayed reset signal POR_RST_DLY, and the output terminal of the OR gate outputs the chip reset signal CHIP_RST; of course, other module structures capable of implementing the logical OR operation function (such as a combinational logic gate structure) are also feasible, and no limitation is imposed thereon.

[0048] Embodiment 2

[0049] As Figure 2As shown in the figure, this embodiment provides a memory chip 100 (for example, a NOR FLASH chip), which includes a power-down delay control circuit 110, a power-down detection circuit 120, and a control logic circuit 130; further, it further includes at least one of a clock circuit 140 and a power supply circuit 150.

[0050] The power-down detection circuit 120, after the memory chip 100 is powered on, monitors the value of the power supply voltage in real time, and generates an initial reset signal POR_RST based on the comparison result between the power supply voltage value and the power-down detection threshold. In one example, the power-down detection circuit 120 includes a sampling module 121 and a comparison module 122; wherein, the sampling module 121 samples the value of the power supply voltage and obtains a sampling value; the comparison module 122 is connected to the sampling module 121, compares the sampling value with the power-down detection threshold, and generates a valid initial reset signal POR_RST when the sampling value is less than the power-down detection threshold. In a specific implementation manner, the sampling module 121 is implemented by a sampling resistor. Of course, other module structures capable of realizing voltage sampling are also feasible, and no limitation is imposed thereon; the comparison module 122 is implemented by a comparator. Among them, the non-inverting input terminal of the comparator receives the sampling value, the inverting input terminal of the comparator receives the power-down detection threshold, and the output terminal of the comparator outputs the initial reset signal POR_RST.

[0051] The power-down delay control circuit 110 is connected to the power-down detection circuit 120, performs a delay operation on the initial reset signal POR_RST to generate a delayed reset signal POR_RST_DLY, and generates a chip reset signal CHIP_RST based on the initial reset signal POR_RST and the delayed reset signal POR_RST_DLY. Among them, the power-down delay control circuit 110 is implemented by the circuit structure described in Embodiment 1. For related content, see the above text and will not be elaborated here.

[0052] The control logic circuit 130 is respectively connected to the power-down detection circuit 120 and the power-down delay control circuit 110, makes a true reset judgment based on the initial reset signal POR_RST and the chip reset signal CHIP_RST, and performs a reset operation when it is determined to be a true reset, thereby completing the reset of the memory chip 100. In fact, the control logic circuit 130 will output logic control signals required for the operation of other circuits (such as a storage circuit) during normal operation. After reset, it no longer outputs relevant logic control signals or outputs invalid relevant logic control signals, thereby completing the reset of the memory chip 100.

[0053] A clock circuit 140, connected to the delay power-down control circuit 110, is used to provide a clock signal CLK as the sampling clock of the D flip-flop in the delay power-down module 111 of the delay power-down control circuit 110. In applications, the clock circuit 140 can be implemented using any existing known clock generation circuit, and there is no limitation thereto.

[0054] A power supply circuit 150, connected to the power-down detection circuit 120, is used to output a power supply voltage. In one example, the power supply circuit 150 receives an external supply voltage and processes the external supply voltage (e.g., filtering processing, level conversion processing, etc.) to generate a power supply voltage; further, the power supply circuit 150 also generates at least one internal supply voltage based on the power supply voltage to supply power to other circuits in the memory chip 100.

[0055] Of course, the memory chip 100 may further include a storage circuit (not shown in the figure), connected to the control logic circuit 130, and performs write operations, read operations, and erase operations on data based on relevant logic control signals.

[0056] Correspondingly, as Figure 3 shown, this embodiment also provides a reset method for the memory chip 100, including the following steps; wherein, the memory chip 100 is implemented using the structure described above.

[0057] Step S1, power on the memory chip 100. Powering on the memory chip 100 is well known to those skilled in the art, so it will not be elaborated here.

[0058] Step S2, determine whether the initial reset signal POR_RST is valid, that is, determine whether the initial reset signal POR_RST is at a low level.

[0059] If the initial reset signal POR_RST is invalid, that is, the initial reset signal POR_RST is at a high level, it indicates that the value of the power supply voltage remains above the power-down detection threshold. At this time, no reset occurs, and the memory chip 100 operates normally.

[0060] If the initial reset signal POR_RST is valid, that is, the initial reset signal POR_RST is at a low level, it indicates that the value of the power supply voltage is less than the power-down detection threshold. At this time, a reset occurs, and jump to step S3.

[0061] In this step, the initial reset signal POR_RST is obtained through the power-down detection circuit 120, and it is determined whether the initial reset signal POR_RST is valid through the control logic circuit 130.

[0062] Step S3, continue to determine whether the chip reset signal CHIP_RST is valid, that is, determine whether the chip reset signal CHIP_RST is at a low level, so as to determine whether the above reset is a false reset.

[0063] If the chip reset signal CHIP_RST is invalid, that is, the chip reset signal CHIP_RST is at a high level, it indicates that the reset that makes the initial reset signal POR_RST at a low level is a false reset (usually caused by a sudden drop in the power supply voltage). At this time, the above reset is determined as a false reset, and the memory chip 100 operates normally.

[0064] If the chip reset signal CHIP_RST is valid, that is, the chip reset signal CHIP_RST is at a low level, it indicates that the reset that makes the initial reset signal POR_RST at a low level is a true reset rather than a false reset. At this time, the above reset is determined as a true reset, and a reset operation is performed on the memory chip 100; actually, a reset operation is performed on the control logic circuit 130, so as to realize the reset of the memory chip 100.

[0065] In this step, the chip reset signal CHIP_RST is obtained through the delay power-off control circuit 110, and whether the chip reset signal CHIP_RST is valid is judged through the control logic circuit 130.

[0066] Next, please combine Figure 4 , to illustrate the process of applying the delay power-off control circuit 110 to the memory chip 100 and eliminating false resets.

[0067] The power supply voltage required for the normal operation of the memory chip 100 is 3.3V. During the operation process, for example, during the process of performing write, read, or erase operations on data, the power supply voltage fluctuates to 1.6V, but quickly returns to 3.3V; from Figure 4 It can be clearly seen that: by combining the initial reset signal POR_RST and the chip reset signal CHIP_RST to trigger a reset, false resets caused by power supply voltage jitter can be effectively filtered out, and normal reset can also be performed when the power supply voltage remains low subsequently.

[0068] In summary, for a delay power-off control circuit, a memory chip, and a reset method thereof according to the present invention, through the design of the delay power-off module and the power-off control module, the initial reset signal and the chip reset signal are combined to judge true and false resets and trigger chip reset during true reset, which can effectively eliminate false resets caused by transient voltage being too low in the power supply, and is beneficial to improving the reliability of the memory chip. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0069] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A delay power-down control circuit, applicable to a memory chip, characterized in that, Comprising: A power-down delay module, which receives an initial reset signal and performs a delay operation on the initial reset signal to generate a delayed reset signal; A power-down control module, which receives the initial reset signal and the delayed reset signal, and generates a chip reset signal based on the initial reset signal and the delayed reset signal.

2. The delay power-off control circuit according to claim 1, wherein The power-down delay module is implemented by a D flip-flop.

3. The delay power-off control circuit according to claim 2, wherein The power-down delay module includes N D flip-flops, where N is a natural number greater than 1; among them, the clock terminals of the N D flip-flops are all connected to a clock signal, the output terminal of the previous D flip-flop is connected to the data terminal of the next D flip-flop, the data terminal of the first D flip-flop receives the initial reset signal, and the output terminal of the Nth D flip-flop outputs the delayed reset signal.

4. The delay power-off control circuit according to claim 3, wherein The value of N is greater than or equal to 10 and less than or equal to 20.

5. The delay power-off control circuit according to claim 1, wherein The power-down control module performs a logical operation on the initial reset signal and the delayed reset signal to generate a valid chip reset signal when both the initial reset signal and the delayed reset signal are valid.

6. The power-down delay control circuit according to claim 5, wherein The initial reset signal, the delayed reset signal, and the chip reset signal are all active low, and the power-down control module is implemented by an OR gate.

7. A memory chip, characterized in that, Comprising: A power-down detection circuit, which, after the memory chip is powered on, monitors the value of the power supply voltage in real time, and generates an initial reset signal based on the comparison result between the power supply voltage value and a power-down detection threshold; The power-down delay control circuit according to any one of claims 1 to 6, connected to the power-down detection circuit; a control logic circuit, respectively connected to the power-down detection circuit and the power-down delay control circuit, makes a true reset judgment based on the initial reset signal and the chip reset signal, and performs a reset operation when it is determined to be a true reset.

8. The memory chip according to claim 7, characterized in that, It further includes a clock circuit, connected to the power-down delay control circuit, for providing a clock signal.

9. The memory chip according to claim 7 or 8, characterized in that, It further includes a power supply circuit, connected to the power-down detection circuit, for outputting a power supply voltage.

10. A reset method for a memory chip as described in any one of claims 7 to 9, characterized in that, Comprising: The memory chip is powered on; Judge whether the initial reset signal is valid; If the initial reset signal is invalid, the memory chip operates normally. If the initial reset signal is valid, continue to judge whether the chip reset signal is valid; If the chip reset signal is invalid and it is determined to be a false reset, the memory chip operates normally. If the chip reset signal is valid and it is determined to be a true reset, perform a reset operation on the memory chip.

Images