Memory device using data latch

Abstract

A memory device includes: a memory cell array configured to include first memory cells for storing user data and second memory cells for column repair of the first memory cells; a page buffer circuit configured to include a first page buffer connected to the first memory cell and a second page buffer connected to the second memory cell; and a page buffer latch input / output circuit configured to use at least one data latch of the second page buffer as an alternative to a buffer memory during a data latch use operation.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0001683, filed on January 4, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Background Art

[0003] Semiconductor memories can be mainly classified into volatile memories or non - volatile memories. Volatile memories (e.g., DRAM or SRAM) have fast read and write speeds, but the data stored in volatile memories disappears when the power is turned off. In contrast, non - volatile memories can retain data even when the power is turned off.

[0004] A representative example of non - volatile memory is flash memory. Flash memory can store multi - bit data of two or more bits in one memory cell. According to the threshold voltage distribution, flash memory storing multi - bit data can have one erase state and multiple programming states.

[0005] Flash memory can include multiple data latches in a page buffer to program multi - bit data. For example, when storing 3 - bit data in one memory cell of flash memory, the page buffer can include three data latches. When storing 4 - bit data, the page buffer can include four data latches.

[0006] Among the multiple data latches in flash memory, there may be data latches that are not frequently used. For example, flash memory can include a column repair unit for column repair when a main unit storing user data fails. If the column repair operation is not performed, multiple data latches in the page buffer connected to the column repair unit may not be used. Summary of the Invention

[0007] According to some embodiments of the present disclosure, there are provided a memory device that can use an unused data latch as an alternative to buffer memory, and a storage device including the memory device.

[0008] According to some embodiments, a memory device includes: a memory cell array configured to include a first memory cell for storing user data and a second memory cell for column repair of the first memory cell; a page buffer circuit configured to include a first page buffer connected to the first memory cell and a second page buffer connected to the second memory cell; and a page buffer latch input / output circuit configured to use at least one data latch of the second page buffer as an alternative to buffer memory during a data latch use operation.

[0009] According to some embodiments, a memory device includes: an array of memory cells configured to include a first memory cell for storing user data and a second memory cell for column repair of the first memory cell; a page buffer circuit configured to include a first page buffer connected to the first memory cell and a second page buffer connected to the second memory cell; and a page buffer latch input / output circuit configured to use at least one data latch of the first page buffer as an alternative to buffer memory when a failure occurs in the first memory cell.

[0010] According to some embodiments, a storage device includes: a memory device configured to include a first memory cell for storing user data, a second memory cell for column repair of the first memory cell, a second memory cell, a first page buffer connected to the first memory cell, and a second page buffer connected to the second memory cell; and a memory controller configured to control the memory device to use at least one data latch of the first page buffer or the second page buffer as an alternative to buffer memory during a data latch usage operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by referring to the following detailed description of examples of the present disclosure with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram showing an example of a storage device.

[0013] Figure 2 is a block diagram showing an example of a memory device.

[0014] Figure 3 is a block diagram showing an example of a page buffer latch input / output circuit.

[0015] Figure 4 is a diagram showing Figure 1 an example of the memory controller in

[0016] Figure 5 is a block diagram showing an example of an operation mode of a page buffer latch control module.

[0017] Figure 6 is a block diagram showing an example of a column repair operation mode of a page buffer latch control module.

[0018] Figure 7 is a block diagram showing an example of a data latch usage mode of a page buffer latch control module.

[0019] Figure 8It is a flowchart showing an example of an operation method of a page buffer latch control module.

[0020] Figure 9 It is a block diagram showing an example of a column repair page buffer unit of a page buffer latch control module.

[0021] Figure 10 It is a block diagram showing an example of a page buffer latch input / output circuit.

[0022] Figure 11 It is a block diagram showing an example of a data latch usage mode of a page buffer latch control module.

[0023] Figure 12 It is a flowchart showing an example of an operation method of a page buffer latch control module that controls a data latch usage operation of a memory device.

[0024] Figure 13 It is a block diagram showing an example of a faulty page buffer unit of a page buffer latch control module.

[0025] Figure 14 It is a block diagram showing an example of a data latch usage operation of a storage device including a flash memory.

[0026] Figure 15 It is a circuit diagram showing an example of a memory block of a memory cell array.

[0027] Figure 16 It is a circuit diagram showing an example of a cell string of a memory block.

[0028] Figure 17 It shows Figure 16 a diagram showing an example of a threshold voltage distribution of memory cells shown in

[0029] Figure 18 It is a circuit diagram showing an example of a page buffer.

[0030] Figure 19 It is a block diagram showing an example of a page buffer latch input / output circuit.

[0031] Figure 20 It is a block diagram showing an example of a device configuration in which data is provided to a host during a data latch usage operation.

[0032] Figure 21 It is a block diagram showing an example of implementing a storage device using a solid state drive (SSD). Detailed Description

[0033] Figure 1is a block diagram showing a storage device according to some embodiments of the present disclosure. The storage device 1000 may be a flash memory-based flash storage device. For example, the storage device 1000 may be implemented as a solid state drive (SSD), a universal flash storage (UFS), a memory card, etc.

[0034] Referring Figure 1 , the storage device 1000 may include a memory device 1100 and a memory controller 1200. The memory device 1100 may receive input / output signals IO from the memory controller 1200 via input / output lines, receive control signals CTRL via control lines, and receive an external power supply PWR via power lines. The storage device 1000 may store data in the memory device 1100 under the control of the memory controller 1200.

[0035] The memory device 1100 may also include a memory cell array 1110 and peripheral circuits 1115. The memory cell array 1110 may have a vertical 3D structure. The memory cell array 1110 may include a plurality of memory cells. Multiple-bit data may be stored in each memory cell.

[0036] In terms of the design layout structure, the memory cell array 1110 may be located (e.g., disposed) beside or above the peripheral circuits 1115. The structure in which the memory cell array 1110 is located on the peripheral circuits 1115 may be referred to as a cell on peripheral (COP) structure.

[0037] The memory cell array 1110 may be manufactured as a chip separate from the peripheral circuits 1115. The upper chip including the memory cell array 1110 and the lower chip including the peripheral circuits 1115 may also be connected to each other by bonding. This structure may be referred to as a chip to chip (C2C) structure.

[0038] The peripheral circuits 1115 may also include analog circuits and / or digital circuits for storing data in the memory cell array 1110 and / or reading data stored in the memory cell array 1110. The peripheral circuits 1115 may receive external power PWR via power lines and generate internal power at various levels.

[0039] The peripheral circuits 1115 may receive commands, addresses, and / or data from the memory controller 1200 via input / output lines. The peripheral circuits 1115 may also store data in the memory cell array 1110 according to the control signals CTRL. Optionally or additionally, the peripheral circuits 1115 may read data stored in the memory cell array 1110 and provide the read data to the memory controller 1200. The peripheral circuits 1115 may also include a page buffer latch input / output circuit 2000.

[0040] The memory controller 1200 may include a page buffer latch control module 1234 and a buffer memory 1300. The page buffer latch control module 1234 may control the data latch usage operation of the page buffer latch input / output circuit 2000. The page buffer latch control module 1234 may use the data latches in the peripheral circuit 1115 of the memory device 1100 like the buffer memory 1300 through the data latch usage operation.

[0041] According to some embodiments of the present disclosure, by using the data latches in the peripheral circuit 1115 as if they were the buffer memory 1300, the data storage capacity can be increased without increasing the storage space of the buffer memory 1300.

[0042] Figure 2 is a block diagram showing an example of a memory device (e.g., Figure 1 the memory device 1100 shown in Figure 2 . Referring to Figure 1 , the memory device 1100 may include a memory cell array 1110 and a peripheral circuit 1115 (refer to Figure 1 ). The peripheral circuit 1115 may include an address decoder 1120 (e.g., a circuit), a page buffer circuit 1130, a data input / output circuit 1140, a word line voltage generator 1150 (e.g., a circuit), and a control logic 1160 (e.g., a circuit).

[0043] The memory cell array 1110 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may include a plurality of pages. Each page may contain a plurality of memory cells. Each memory cell may store multiple bits of data (e.g., two or more bits). Each memory block may correspond to an erase unit, and each page may correspond to a read and / or write unit.

[0044] The memory cell array 1110 may be formed in a direction perpendicular to the substrate. The gate electrode layer and the insulating layer may be alternately deposited on the substrate. Each memory block (e.g., BLK1) may be connected to one or more string selection lines SSL, a plurality of word lines WL1 to WLm, and one or more ground selection lines GSL. WLk is the selected word line sWL, and the remaining word lines (WL1 to WLk-1, WLk+1 to WLm) are unselected word lines uWL.

[0045] The address decoder 1120 may be connected to the memory cell array 1110 through the selection lines SSL and GSL and the word lines WL1 to WLm. The address decoder 1120 may select the word lines during a programming or reading operation. The address decoder 1120 may receive the word line voltage VWL from the word line voltage generator 1150 and provide a programming voltage or a reading voltage to the selected word line.

[0046] The page buffer circuit 1130 can be connected to the memory cell array 1110 through bit lines BL1 to BLz. The page buffer circuit 1130 can temporarily store data to be stored in the memory cell array 1110 or data read from the memory cell array 1110. The page buffer circuit 1130 can include page buffers PB1 to PBz connected to the corresponding bit lines. Each page buffer can include a plurality of latches to store or read multi-bit data.

[0047] The input / output circuit 1140 can be internally connected to the page buffer circuit 1130 through data lines and externally connected to the memory controller 1200 through input / output lines IO1 to IOn (refer to Figure 1 ). The input / output circuit 1140 can receive programming data from the memory controller 1200 during a programming operation. In addition, the input / output circuit 1140 can provide data read from the memory cell array 1110 to the memory controller 1200 during a read operation.

[0048] The word line voltage generator 1150 can receive internal power from the control logic 1160 and generate a word line voltage VWL for reading or writing data. The word line voltage VWL can be provided to the selected word line (sWL) or the unselected word line (uWL) through the address decoder 1120.

[0049] The word line voltage generator 1150 can include a programming voltage generator 1151 and a pass voltage generator 1152. The programming voltage generator 1151 can generate a programming voltage Vpgm provided to the selected word line sWL during a programming operation. The pass voltage generator 1152 can generate a pass voltage Vpass provided to the selected word line sWL and the unselected word line uWL.

[0050] The word line voltage generator 1150 can include a read voltage generator 1153 and a read pass voltage generator 1154. The read voltage generator 1153 can generate a selected read voltage Vrd provided to the selected word line sWL during a read operation. The read pass voltage generator 1154 can generate a read pass voltage Vrdps provided to the unselected word line uWL. The read pass voltage Vrdps can be a voltage sufficient to turn on the memory cells connected to the unselected word line uWL during a read operation.

[0051] The control logic 1160 can use commands CMD, addresses ADDR, and control signals CTRL provided from the memory controller 1200 to control operations of the memory device 1100 such as reading, writing, and erasing. The address ADDR can include a block selection address for selecting a memory block, a row address for selecting a page, and a column address for selecting a memory cell.

[0052] Reference Figure 2 As shown in Figure 2 , the input / output circuit 1140 may include a page buffer latch input / output circuit 2000. The page buffer latch input / output circuit 2000 may receive control signals from the memory controller 1200 and perform data latch usage operations. The memory device 1100 may use the data latches of the page buffer circuit 1130 as a buffer memory 1300. Therefore, the memory device 1100 may increase the utilization rate of the data latches and effectively improve the storage capacity of the buffer memory 1300.

[0053] Figure 3 is a block diagram showing an example of a page buffer latch input / output circuit (e.g., Figure 2 the page buffer latch input / output circuit 2000 shown in Figure 2 ). Referring to Figure 3 Figure 3 , the memory device 1100 may include a memory cell array 1110, an address decoder 1120, a page buffer circuit 1130, a control logic 1160, and a page buffer latch input / output circuit 2000.

[0054] The memory cell array 1110 may be connected to the address decoder 1120 through the k-th word line (WLk). A column repair unit (CR unit) and main cells may be connected to the WLk. The main cells may be memory cells for storing user data. The column repair unit may be a memory cell for storing data to be stored in the main cells when the main cells fail. The memory device 1100 may store data in the column repair unit through a column repair operation without storing data in the failed cells.

[0055] The page buffer circuit 1130 may include a first page buffer to a z-th page buffer (PB1 to PBz). For example, the first page buffer PB1 may be a column repair page buffer connected to the column repair unit (CR unit). The z-th page buffer (PBz) may be a main page buffer connected to the main cells.

[0056] The first to z-th page buffers (PB1 to PBz) may each include a plurality of data latches. The number of data latches in each page buffer may vary depending on the number of data bits to be stored (e.g., depending on whether the memory cell array includes single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and / or quad-level cells (QLC)).

[0057] For example, a page buffer connected to a TLC memory cell storing 3 bits of data in one memory cell may include three or more data latches. A page buffer connected to a QLC memory cell storing 4 bits of data in one memory cell may include four or more data latches. In Figure 3In the example, the first page buffer PB1 may include data latches DL11 to DL14 from the 11th to the 14th. The z-th page buffer (PBz) may include data latches (DLz1 to DLz4) from the z1-th to the z4-th.

[0058] The data latch resources used as an alternative to or in addition to the memory buffer may vary according to the configuration of the page buffer connected to the corresponding unit. For example, in the case of QLC, the range of the number of data latches in the page buffer may depend on the implementation and be 4 to 6 or more. The number of data latches used as the memory buffer may be set to some or all according to the usage range.

[0059] The page buffer latch input / output circuit 2000 may perform data latch usage operations in response to control signals from the page buffer latch control module 1234. The page buffer latch input / output circuit 2000 may use the data latches in the page buffer of the page buffer circuit 1130 like the buffer memory 1300 through the data latch usage operations.

[0060] As an example, the page buffer latch input / output circuit 2000 may use the data latches of the column repair page buffer in the page buffer circuit 1130 like the buffer memory 1300. For example, instead of or in addition to the buffer memory 1300, the 11th to 14th data latches DL11 to DL14 of the first page buffer PB1 may be used.

[0061] The page buffer latch input / output circuit 2000 may include a column repair fuse circuit 2100, a column address comparator 2200 (e.g., a circuit), and a page buffer selector 2300 (e.g., a circuit). The column repair fuse circuit 2100 and the column address comparator 2200 may be used in general column repair operations (e.g., in addition to being used in data latch usage operations).

[0062] The column repair fuse circuit 2100 may store column repair address information. The column repair address information may include the address of a faulty memory cell (e.g., a main cell) and the address of a column repair cell (e.g., a CR cell). The column repair fuse circuit 2100 may provide the column repair address (CR_ADDR) to the column address comparator 2200 during column repair operations and / or data latch usage operations.

[0063] The column repair fuse circuit 2100 can generate a column repair enable signal (CR_EN) during the data latch usage operation. The column repair fuse circuit 2100 can use the column repair enable signal CR_EN to prevent the data stored in the data latches (e.g., DL11 to DL14) from being programmed into the column repair memory cells during the data latch usage operation.

[0064] The column address comparator 2200 can compare the column repair address (CR_ADDR) provided from the column repair fuse circuit 2100 with the address (ADDR) provided from the input / output circuit 1140 (see Figure 2 ). If they match, the column repair fuse circuit 2100 can provide a signal for selecting a column repair page buffer (e.g., PB1) to the page buffer selector 2300.

[0065] The page buffer selector 2300 can receive control signals from the page buffer latch control module 1234 (see Figure 1 ) and perform the data latch usage operation. The page buffer selector 2300 can receive a column address comparison signal from the column address comparator 2200, and select the column repair page buffer (e.g., PB1) and / or the main page buffer (e.g., PBz).

[0066] For example, the page buffer selector 2300 can compare the input address (ADDR) with the column repair address (CR_ADDR) stored in the column repair fuse circuit 2100, and when they match, can select the column repair page buffer (e.g., PB1). The page buffer selector 2300 can use the data latches DL11 to DL14 of the column repair page buffer (e.g., PB1) instead of the buffer memory 1300.

[0067] Figure 4 is a block diagram showing an example of a memory controller (e.g., the memory controller 1200 in Figure 1 ). Referring to Figure 4 , the memory controller 1200 can include a host interface 1201, a flash memory interface 1202, a control unit 1210, a working memory 1220, and an error correction code (ECC) circuit 1240. The working memory 1220 can drive the flash translation layer (FTL) 1230.

[0068] The memory controller 1200 may further include various components. For example, the memory controller 1200 may include a buffer memory for temporarily storing data generated by read or write operations of a memory device (e.g., flash memory) 1100. The memory controller 1200 may also include a buffer control module for controlling the buffer memory, a command generation module for generating commands (CMDs) for controlling memory operations according to requests from a host 1500, and / or other components.

[0069] The host interface 1201 may provide an interface between the host 1500 and the memory controller 1200. Standard interfaces may include various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), IEEE 1394, Universal Serial Bus (USB), Secure Digital Card (SD), Multimedia Card (MMC), Embedded Multimedia Card (eMMC), Universal Flash Storage (UFS), Compact Flash (CF), etc.

[0070] The flash interface 1202 may provide an interface between the memory device (e.g., flash memory) 1100 and the memory controller 1200. For example, write data or read data may be sent to and received from the memory device (e.g., flash memory) 1100 through the flash interface 1202. The flash interface 1202 may provide commands and addresses to the memory device (e.g., flash memory) 1100. The flash interface 1202 may provide the data read from the memory device (e.g., flash memory) 1100 to the memory controller 1200.

[0071] The control unit 1210 may include a central processing unit or a microprocessor, and may control the overall operation of the memory controller 1200. The control unit 1210 may drive the firmware loaded in the working memory 1220 to control the memory controller 1200.

[0072] The working memory 1220 may be implemented with various types of memories, such as DRAM, SRAM, or PRAM. The working memory 1220 may drive a flash translation layer (FTL) 1230 under the control of the control unit 1210.

[0073] The flash translation layer 1230 can be loaded from the flash memory into the working memory 1220 during the boot operation of the storage device. The flash translation layer 1230 can include an address mapping module 1231, a garbage collection module 1232, and a wear leveling module 1233 depending on the functions implemented by the firmware.

[0074] The address mapping module 1231 can perform address mapping operations on a page-by-page or block-by-block basis. The page address mapping operation is an operation that converts the logical page address received from the file system into a physical page address in the memory device (e.g., flash memory) 1100. For this purpose, a page-level address mapping table can be maintained in the working memory 1220. The page address mapping operation can provide excellent garbage collection performance, but a large address mapping table can be used.

[0075] The block address mapping operation is an operation that converts the logical block address received from the file system into a physical block address in the memory device (e.g., flash memory) 1100. Pages belonging to the same logical block can belong to the same physical block. For this purpose, the block address mapping operation can maintain a block-level address mapping table in the working memory 1220. The block address mapping operation can use a small address mapping table, but additional garbage collection operations can be performed.

[0076] The flash translation layer 1230 can perform a hybrid mapping operation that combines the advantages of the page address mapping operation and the block address mapping operation. The flash translation layer 1230 can perform the hybrid mapping operation based on a log buffer. The log buffer-based hybrid mapping operation uses very little memory space while providing excellent garbage collection performance.

[0077] The garbage collection module 1232 can perform garbage collection operations by referring to the address mapping table. The garbage collection module 1232 can use the address mapping table to protect one or more free blocks. The garbage collection module 1232 can use the address mapping table to move one or more valid data stored in the source block to the target block. The garbage collection module 1232 can create free blocks by erasing the source block from which all valid data has been moved.

[0078] The wear leveling module 1233 can manage the wear level of the storage cells of the memory device (e.g., flash memory) 1100. The storage cells may deteriorate due to write and erase operations, etc. The deteriorated storage cells may cause defects. The wear leveling module 1233 can prevent a specific cell area from wearing out faster than other cell areas by managing the program erase cycles of the storage cell array. The wear leveling module 1233 can control the address mapping module 1231 so that the programming and erase times are equally distributed to the cell areas of the storage cell array.

[0079] The page buffer latch control module 1234 can control the data latch usage operation of the page buffer latch input / output circuit 2000. The page buffer latch control module 1234 can use the data latch of the page buffer circuit 1130 like the buffer memory 1300 through the data latch usage operation. By using the data latch of the page buffer circuit 1130 like the buffer memory 1300, the effective buffer memory available to the memory controller 1200 can be increased.

[0080] The ECC circuit 1240 can generate an error correction code (ECC) to correct the faulty bits or error bits of the data received from the memory device (e.g., flash memory) 1100. The ECC circuit 1240 can perform error correction encoding on the data provided to the memory device (e.g., flash memory) 1100 to form the data with parity bits added. The parity bits can be stored in the memory device (e.g., flash memory) 1100.

[0081] The ECC circuit 1240 can perform error correction decoding on the data output from the memory device (e.g., flash memory) 1100. The ECC circuit 1240 can use parity to correct errors. The ECC circuit 1240 can use coding modulation such as low density parity check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, turbo code, Reed-Solomon code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM), and block coded modulation (BCM) to correct errors.

[0082] The ECC circuit 1240 can have an error correction allowable range. For example, the ECC circuit 1240 can correct up to 40 bits of errors for 2K-byte page data. In this case, the maximum allowable range for the ECC circuit 1240 to correct errors is 40 bits. For example, if more than 40 bits of errors occur, the ECC circuit 1240 may not correct the errors in the page. The page whose errors may not be corrected like this is called a defective page. The memory cell in which an error occurs in the defective page is called a defective cell.

[0083] Figure 5 is a block diagram showing an example of the operation mode of the page buffer latch control module (e.g., Figure 4 the page buffer latch control module 1234 shown in Figure 5 , the page buffer latch control module 1234 can execute the column repair operation mode or the data latch usage mode.

[0084] The page buffer latch control module 1234 may include a column repair operation mode unit 1235 and a data latch usage mode unit 1236. The column repair operation mode unit 1235 may provide a column repair operation mode signal (CROM) to the page buffer latch input / output circuit 2000 to perform a column repair operation. The data latch usage mode unit 1236 may provide a data latch usage mode signal (DLUM) to the page buffer latch input / output circuit 2000 to perform a data latch usage operation.

[0085] Figure 6 is a block diagram showing Figure 5 an example of the column repair operation mode of the page buffer latch control module shown. Refer to Figure 6 , the page buffer latch control module 1234 (see Figure 5 ) may provide a column repair operation mode signal (CROM) to the memory device 1100 to perform a column repair operation when a main unit fails.

[0086] The column repair fuse circuit 2100 may receive the column repair operation mode signal (CROM) and activate a column repair enable signal (CR_EN). The column repair enable signal (CR_EN) may be a signal for performing a column repair operation. The column repair enable signal (CR_EN) may be provided to an AND gate through an inverter (INV). The AND gate may receive a control signal (CONT) from the control logic 1160 and the inverted column repair enable signal to deactivate the data latch output signal (DLO).

[0087] For example, if the column repair enable signal CR_EN is 1, the inverter (INV) may output an inverted column repair enable signal. The inverted column repair enable signal may be 0. The AND gate may receive the control signal (CONT) 1 and the inverted column repair enable signal 0 to output the data latch output signal (DLO) 0.

[0088] The page buffer selector 2300 may receive the column repair operation mode signal (CROM) from the memory controller 1200 to perform a column repair operation. The page buffer selector 2300 may receive a column address comparison signal (CA_COM) from the column address comparator 2200 and provide data (DATA) to the first page buffer (PB1). Here, the first page buffer PB1 may be a column repair page buffer.

[0089] During a programming operation, the memory device 1100 may program data stored in data latches DL11 to DL14 of the first page buffer PB1 into a column repair unit (CR unit). Alternatively, the memory device 1100 may store the data programmed in the column repair unit (CR unit) in data latches DL11 to DL14 of the first page buffer PB1 during a read operation.

[0090] Figure 7 is a block diagram showing an example of a data latch usage pattern of a page buffer latch control module (e.g., Figure 5 the page buffer latch control module 1234 shown in ). Refer to Figure 7 , the page buffer latch control module 1234 (see Figure 5 ) may perform data latch usage operations regardless of column repair operations. The page buffer latch control module 1234 may provide a data latch usage pattern signal (DLUM) to the memory device 1100 to perform data latch usage operations.

[0091] The column repair fuse circuit 2100 may receive the data latch usage pattern signal (DLUM) and deactivate the column repair enable signal (CR_EN). For example, the column repair enable signal (CR_EN) may be 0. The column repair enable signal (CR_EN) may be provided to an AND gate through an inverter (INV). The AND gate may receive control signal (CONT) 1 and the inverted column repair enable signal 1 to activate the data latch output signal (DLO). The data latch output signal (DLO) may be 1.

[0092] The page buffer selector 2300 may receive the data latch usage pattern signal (DLUM) from the memory controller 1200 and perform data latch usage operations. The page buffer selector 2300 may receive a column address comparison signal (CA_COM) from the column address comparator 2200 and provide data (DATA) to the first page buffer (PB1). The first page buffer PB1 may be a column repair page buffer.

[0093] The memory device 1100 may use the data latches DL11 to DL14 of the first page buffer PB1 instead of or in addition to the buffer memory 1300 (e.g., as if it were the buffer memory 1300) to perform programming operations and / or read operations. The memory device 1100 may store data to be stored in the buffer memory 1300 in the data latches of the column repair page buffer.

[0094] In traditional operations, the column repair page buffer can only be used when the main unit fails. Therefore, when there is no failure, the column repair page buffer can be unused. According to some implemented storage devices 1000 (see Figure 1 ), additional data storage space can be ensured by using the data latch of the column repair page buffer that is originally only used during column repair operations, as if the data latch were the buffer memory 1300.

[0095] Figure 8 is a flowchart showing an example of an operation method of a page buffer latch control module (e.g., Figure 5 's page buffer latch control module 1234). The page buffer latch control module 1234 can control the data latch usage operation of the memory device 1100. The memory controller 1200 can receive a data write request from the host and provide a data latch usage mode signal (DLUM) to the memory device 1100. The memory device 1100 can receive the data latch usage mode signal (DLUM) and perform a data latch usage operation.

[0096] In operation S110, the page buffer latch control module 1234 can receive a data write request from the host. Here, the data can be data that is frequently reused (e.g., hot data) or dedicated data for managing the memory device 1100 (e.g., parameters or metadata). The page buffer latch control module 1234 can determine whether the data requested to be written by the host is dedicated data, and if it is predetermined dedicated data, the next operation can be performed.

[0097] For example, the page buffer latch control module 1234 can write and / or read data N times or more at the same address during a predetermined time period. At this time, the page buffer latch control module 1234 can determine that this data is dedicated data (e.g., hot data) and perform a data latch usage operation.

[0098] In operation S120, the page buffer latch control module 1234 can determine whether the data is to be stored in the buffer memory 1300. If the page buffer latch control module 1234 determines not to store the data in the buffer memory 1300 (No), operation S125 can be performed. In operation S125, the page buffer latch control module 1234 can store the data in the storage cell array 1110 of the memory device 1100 (e.g., flash memory). If the page buffer latch control module 1234 determines to store the data in the buffer memory 1300 (Yes), operation S130 can be performed.

[0099] In operation S130, the page buffer latch control module 1234 may check the free space of the buffer memory 1300. When a write request is received from the host, the page buffer latch control module 1234 may check the total storage space, the currently used storage space, and / or the unused storage space of the buffer memory 1300. The page buffer latch control module 1234 may calculate the free space of the buffer memory 1300 according to a predetermined algorithm.

[0100] In operation S140, the page buffer latch control module 1234 may determine whether the free space of the buffer memory 1300 calculated in operation S130 is greater than the size of the data requested to be written by the host. If the free space is greater than the data size (yes), the page buffer latch control module 1234 may control the data to be stored in the buffer memory 1300 (S165). If the free space of the buffer memory 1300 is less than or equal to the data size (no), the page buffer latch control module 1234 may perform operation S150.

[0101] In operation S150, the page buffer latch control module 1234 may check the data latch status of the column repair page buffer (CR P / B). The column repair page buffer (CR P / B) may include a plurality of page buffers. The plurality of page buffers may be divided into page buffers that perform column repair operations and page buffers that do not perform column repair operations.

[0102] The data to be stored in the main unit may be stored in the storage unit connected to the page buffer that performs the column repair operation. The data may not be stored in the storage unit connected to the page buffer that has not yet performed the column repair operation. As an example, the page buffer latch control module 1234 may check the data latch status of the page buffer that has not yet performed the column repair operation.

[0103] In operation S160, the page buffer latch control module 1234 may determine whether the data latch space is greater than the data size. If the data latch space is less than or equal to the data size (no), the page buffer latch control module 1234 may control the data to be stored in the unused storage space of the buffer memory 1300 (S165). If the data latch space is greater than the data size (yes), the page buffer latch control module 1234 may perform operation S170.

[0104] In operation S170, the page buffer latch control module 1234 may control data to be stored in the data latches of the column-repaired page buffer (CR P / B). As previously described, the column-repaired page buffer (CR P / B) may be a page buffer for which a column repair operation has not been performed yet. Each page buffer may include a plurality of data latches. For example, one page buffer may include four data latches.

[0105] The page buffer latch control module 1234 may store data in the data latches of the column-repaired page buffer (CRP / B) in a predetermined unit. For example, the page buffer latch control module 1234 may store data in the I / O unit. The I / O unit of the memory device 1100 may be 8 bits or 16 bits.

[0106] Figure 9 is a block diagram showing the column-repaired page buffer unit of a memory device (e.g., the memory device 1100). The column-repaired page buffer unit may be used to perform the data latch usage operation of the page buffer latch control module 1234. For example, the data latch usage operation may be performed in units of 8 bits or 16 bits.

[0107] Referring to Figure 9 , the column-repaired page buffer unit may be the first to the mth page buffers (PB1 to PBm). The first page buffer (PB1) may include the 11th to the 14th data latches (DL11 to DL14). The mth page buffer (PBm) may contain the m1th to the m4th data latches (DLm1 to DLm4).

[0108] When the data latch usage operation is performed in units of 8 bits, data may be stored in the data latches of the first page buffer PB1 and the second page buffer PB2 simultaneously. When the data latch usage operation is performed in units of 16 bits, data may be stored in the data latches of the first to the fourth page buffers (PB1 to PB4) simultaneously.

[0109] The page buffer latch control module 1234 may control the data latch usage operation of the page buffer latch input / output circuit 2000 based on the column-repaired page buffer unit. The page buffer latch control module 1234 may use the data latches of the page buffer circuit 1130 through the data latch usage operation as if it were the buffer memory 1300. By using the data latches of the page buffer circuit 1130 as if it were the buffer memory 1300, the availability of the buffer memory 1300 can be increased.

[0110] Figure 10 is a diagram showing the page buffer latch input / output circuit (e.g., Figure 3Block diagram of an example of the page buffer latch input / output circuit shown. Refer to Figure 10 , the memory device 1100 may include a memory cell array 1110, an address decoder 1120, a page buffer circuit 1130, control logic 1160, and a page buffer latch input / output circuit 2000.

[0111] The memory device 1100 can store data in a column repair unit (CR unit) through a column repair operation without storing the data in the faulty cell. The memory device 1100 may not use the page buffer connected to the faulty cell. Hereinafter, the page buffer connected to the faulty cell will be referred to as a faulty page buffer. The memory device 1100 can use the data latch of the faulty page buffer of the page buffer circuit 1130 (e.g., PBz) through the page buffer latch input / output circuit 2000 as an alternative to (or in addition to) the buffer memory 1300.

[0112] The page buffer circuit 1130 may include a first page buffer to a z-th page buffer (PB1 to PBz). The first page buffer PB1 may be a column repair page buffer connected to the column repair unit (CR unit). The z-th page buffer (PBz) may be a page buffer connected to the faulty main unit.

[0113] The page buffer latch input / output circuit 2000 can use the data latch of the faulty page buffer (e.g., PBz) of the page buffer circuit 1130 like the buffer memory 1300 through the data latch usage operation. For example, instead of or in addition to the buffer memory 1300, the z1-th to z4-th data latches (DLz1 to DLz4) of the z-th page buffer (PBz) can be used.

[0114] The page buffer latch input / output circuit 2000 may include a column repair fuse circuit 2100, a column address comparator 2200, and a page buffer selector 2300. Here, the column repair fuse circuit 2100 and the column address comparator 2200 can be used in general column repair operations other than the data latch usage operation.

[0115] The column repair fuse circuit 2100 can store column repair address information. The column repair address information may include the address of the faulty cell (main unit) (F_ADDR) and the column repair address (CR_ADDR). The column repair fuse circuit 2100 can provide the faulty cell address (F_ADDR) to the column address comparator 2200 during the data latch usage operation.

[0116] Column repair fuse circuit 2100 can generate a column repair enable signal (CR_EN) during the data latch usage operation. Column repair fuse circuit 2100 can use the column repair enable signal CR_EN to prevent data stored in data latches (e.g., DLz1 to DLz4) from being programmed into a faulty cell (master cell) during the data latch usage operation.

[0117] Column address comparator 2200 can compare the faulty cell address (F_ADDR) provided from column repair fuse circuit 2100 with the address (ADDR) provided from input / output circuit 1140 (see Figure 2 ). If they match, then column repair fuse circuit 2100 can provide a signal for selecting a faulty page buffer (e.g., PBz) to page buffer selector 2300.

[0118] Page buffer selector 2300 can receive a column address comparison signal from column address comparator 2200 and select a faulty page buffer (e.g., PBz). Page buffer selector 2300 can store data in data latches (DLz1 to DLz4) of the faulty page buffer (e.g., PBz). Page buffer latch input / output circuit 2000 can use the data latches of the faulty page buffer (e.g., PBz) like buffer memory 1300.

[0119] Figure 11 is a block diagram showing an example of the data latch usage mode of a page buffer latch control module (e.g., Figure 5 the page buffer latch control module shown). Refer to Figure 11 , page buffer latch control module 1234 (see Figure 5 ) can perform a data latch usage operation regardless of the column repair operation. Page buffer latch control module 1234 can provide a data latch usage mode signal (DLUM) to memory device 1100 to perform a data latch usage operation.

[0120] Column repair fuse circuit 2100 can receive a data latch usage mode signal (DLUM) and generate a column repair enable signal (CR_EN)0. The column repair enable signal (CR_EN) can be provided to an AND gate through an inverter (INV). The AND gate can receive a control signal (CONT)1 from control logic 1160 and a inverted column repair enable signal 1 from the inverter (INV), and activate a data latch output signal (DLO).

[0121] The page buffer selector 2300 may receive a data latch usage mode signal (DLUM) from the memory controller 1200 and perform a data latch usage operation. The page buffer selector 2300 may receive a column address comparison signal (CA_COM) from the column address comparator 2200 and provide data to the z-th page buffer (PBz). Here, the z-th page buffer (PBz) may be a defective page buffer.

[0122] The memory device 1100 may use the data latches DLz1 to DLz4 of the z-th page buffer PBz as if it were the buffer memory 1300, for example, to perform a programming operation and / or a read operation. The memory device 1100 may store the data to be stored in the buffer memory 1300 in the data latches of the defective page buffer.

[0123] The defective page buffer may not be used for normal purposes because data is not stored in defective cells. Thus, the memory device 1100 may use the data latches of the defective page buffer as an alternative to the buffer memory 1300 through the page buffer latch input / output circuit 2000. Thus, the storage device 1000 according to some embodiments (see Figure 1 ) may ensure additional data storage space by using the data latches of the unused defective page buffer as an alternative to the buffer memory 1300.

[0124] Figure 12 is a flowchart explaining an operation method of a page buffer latch control module that controls a data latch usage operation of a memory device such as Figure 11 shown. The memory controller 1200 may receive a data write request from a host and provide a data latch usage mode signal (DLUM) to the memory device 1100. The memory device 1100 may receive the data latch usage mode signal (DLUM) and perform a data latch usage operation.

[0125] In operation S210, the page buffer latch control module 1234 may receive a data write request from a host. Here, the data may be dedicated data, such as frequently reused data (e.g., hot data). The page buffer latch control module 1234 may determine whether the data requested to be written by the host is dedicated data, and if it is predetermined dedicated data, may perform the next operation.

[0126] In operation S220, the page buffer latch control module 1234 may determine whether data is to be stored in the buffer memory 1300. If the page buffer latch control module 1234 determines that the data will not be stored in the buffer memory 1300 (No), the page buffer latch control module 1234 may store the data in the memory cell array 1110 of the memory device 1100 (S225). If the page buffer latch control module 1234 determines that the data will be stored in the buffer memory 1300 (Yes), operation S230 may be performed.

[0127] In operation S230, the page buffer latch control module 1234 may check the free space of the buffer memory 1300. When the page buffer latch control module 1234 receives a write request from the host, it may check the total storage space, the currently used storage space, and the unused storage space of the buffer memory 1300. The page buffer latch control module 1234 may calculate the free space of the buffer memory 1300 according to a predetermined algorithm.

[0128] In operation S240, the page buffer latch control module 1234 may determine whether the free space of the buffer memory 1300 calculated in operation S230 is greater than the size of the data requested to be written by the host. If the free space is greater than the data size (Yes), the page buffer latch control module 1234 may control the data to be stored in the buffer memory 1300 (S265). If the free space of the buffer memory 1300 is less than or equal to the data size (No), the page buffer latch control module 1234 may perform operation S250.

[0129] In operation S250, the page buffer latch control module 1234 may check the data latch status of the faulty page buffer. The faulty page buffer may include multiple page buffers. The page buffer latch control module 1234 may check the data latch status of each of the multiple page buffers.

[0130] In operation S260, the page buffer latch control module 1234 may determine whether the data latch space is greater than the data size. If the data latch space is less than or equal to the data size (No), the page buffer latch control module 1234 may control the data to be stored in the unused storage space of the buffer memory 1300 (S265). If the data latch space is greater than the data size (Yes), the page buffer latch control module 1234 may perform operation S270.

[0131] In operation S270, the page buffer latch control module 1234 may control data to be stored in the data latches of the faulty page buffer (faulty P / B). Each page buffer may include a plurality of data latches. For example, one page buffer may include four data latches. The page buffer latch control module 1234 may store data in the data latches of the faulty page buffer in a predetermined unit.

[0132] Figure 13 is a block diagram showing an example of a faulty page buffer unit of a memory device (e.g., memory device 1100). The data latch usage operation of the page buffer latch control module 1234 may be performed using the faulty page buffer unit. For example, the data latch usage operation may be performed in units of 8 bits or 16 bits.

[0133] Reference Figure 13 , the faulty page buffer unit may be the r-th to z-th page buffers (PBr to PBz). The r-th page buffer PBr may include the r1-th to r4-th data latches (DLr1 to DLr4). And the z-th page buffer PBz may include the z1-th to z4-th data latches (DLz1 to DLz4).

[0134] When the data latch usage operation is performed in units of 8 bits, data may be simultaneously stored in the data latches of the r-th page buffer and the r+1-th page buffer (PBr, PBr+1). When the data latch usage operation is performed in units of 16 bits, data may be simultaneously stored in the data latches of the r-th to r+3-th page buffers (PBr to PBr+3).

[0135] The page buffer latch control module 1234 may control the data latch usage operation of the page buffer latch input / output circuit 2000 based on the faulty page buffer unit. The page buffer latch control module 1234 may use the data latches of the page buffer circuit 1130 like a buffer memory 1300 through the data latch usage operation. By using the data latches of the page buffer circuit 1130 like a buffer memory 1300, the availability of the buffer memory 1300 can be increased.

[0136] Figure 14 is a block diagram showing the data latch usage operation of a storage device including a flash memory according to some embodiments of the present invention. Reference Figure 14 , the storage device 3000 may include a flash memory 3100 and a memory controller 3200.

[0137] The flash memory 3100 may include a memory cell array 3110 and a peripheral circuit 3115. The memory cell array 3110 may include a plurality of memory blocks BLK1 to BLKn. The peripheral circuit 3115 may receive external power (PWR) through a power line and generate internal power at various levels. The peripheral circuit 3115 may also include a page buffer latch input / output circuit 2000.

[0138] The memory controller 3200 may include a page buffer latch control module 1234 and a buffer memory 3300. The page buffer latch control module 1234 may control the data latch usage operation of the page buffer latch input / output circuit 2000. The page buffer latch control module 1234 may use the data latches in the peripheral circuit 3115 of the flash memory 3100 like the buffer memory 3300 through the data latch usage operation.

[0139] Figure 15 is a circuit diagram showing an example of a memory block BLK1 of a memory cell array such as Figure 2 or Figure 14 the memory cell array shown. Referring to Figure 15 , in the memory block BLK1, a plurality of cell strings STR11 to STR8z may be formed between bit lines BL1 to BLz and a common source line CSL. Each cell string includes a string select transistor SST, a plurality of memory cells MC1 to MCm, and a ground select transistor GST.

[0140] The string select transistor SST may be connected to string select lines SSL1 to SSL8. The ground select transistor GST may be connected to ground select lines GSL1 to GSL8. The string select transistor SST may be connected to bit lines BL1 to BLz, and the ground select transistor GST may be connected to the common source line CSL.

[0141] The first word lines WL1 to the m-th word lines WLm may be connected to the plurality of memory cells MC1 to MCm in a row direction. The first to the z-th bit lines BL1 to BLz may be connected to the plurality of memory cells MC1 to MCm in a column direction. The first to the z-th page buffers PB1 to PBz may be connected to the first to the z-th bit lines BL1 to BLz.

[0142] The first word line WL1 can be placed above the first to eighth ground selection lines GSL1 to GSL8. The first memory cell MC1 placed at the same height from the substrate can be connected to the first word line WL1. The m-th word line WLm can be located below the first to eighth string selection lines SSL1 to SSL8. The m-th memory cell MCm placed at the same height from the substrate can be connected to the m-th word line WLm. In a similar manner, the second to (m - 1)-th memory cells MC2 to MCm - 1 placed at the same height from the substrate can be respectively connected to the second to (m - 1)-th word lines WL2 to WLm - 1.

[0143] Figure 16 is a circuit diagram showing the cell string selected from the cell strings of the memory block BLK1 shown by the first string selection line SSL1. The 11th to 1z-th cell strings STR11 to STR1z can be selected by the first string selection line SSL1. The 11th to 1z-th cell strings STR11 to STR1z can be respectively connected to the first to z-th bit lines BL1 to BLz. The first to z-th page buffers PB1 to PBz can be respectively connected to the first to z-th bit lines BL1 to BLz. Figure 15 The 11th cell string STR11 can be connected to the first bit line BL1 and the common source line CSL. The 11th cell string STR11 can include a string selection transistor SST selected by the first string selection line SSL1, the first to m-th memory cells MC1 to MCm connected to the first to m-th word lines WL1 to WLm, and a ground selection transistor GST selected by the first ground selection line GSL1. The 12th cell string STR12 can be connected to the second bit line BL2 and the common source line CSL. The 1z-th cell string STR1z can be connected to the z-th bit line BLz and the common source line CSL.

[0144] The first word line WL1 and the m-th word line WLm can be edge word lines (edge WL). The second word line WL2 and the (m - 1)-th word line WLm - 1 can be edge adjacent word lines. The k-th word line WLk can be the selected word line sWL. The (k - 1)-th word line WLk - 1 and the (k + 1)-th word line WLk + 1 can be adjacent word lines adjacent to the selected word line. If the k-th word line WLk is the selected word line sWL, the remaining word lines WL1 to WLk - 1 and WLk + 1 to WLm can be unselected word lines uWL.

[0145]

[0146] ​The first storage cell MC1 and the m-th storage cell MCm may be edge storage cells. The second storage cell MC2 and the (m-1)-th storage cell MCm-1 may be edge-adjacent storage cells. The k-th storage cell MCk may be the selected storage cell sMC. The (k-1)-th storage cell MCk-1 and the (k+1)-th storage cell MCk+1 may be storage cells adjacent to the selected storage cell (adjacent MC). If the k-th storage cell MCk is the selected storage cell sMC, the remaining storage cells MC1 to MCk-1 and MCk+1 to MCm may be unselected storage cells uMC.

[0147] A set of storage cells selected by one string select line and connected to one word line may be a page. For example, the storage cells selected by the first string select line SSL1 and connected to the k-th word line WLk may be a page. For example, eight pages may be configured on the k-th word line WLk. Among these eight pages, the page connected to the first string select line SSL1 is the selected page, and the pages connected to the second to eighth string select lines SSL2 to SSL8 are unselected pages.

[0148] Among the storage cells selected by the first string select line SSL1 and connected to the k-th word line WLk, the storage cells connected to the first page buffer PB1 may be column repair units (CR units). The storage cells connected to the z-th page buffer (PBz) may be main units.

[0149] Figure 17 is a diagram showing an example of the threshold voltage distribution of storage cells (such as Figure 16 the storage cells shown in). The horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of storage cells.

[0150] Figure 17 shows an example of storing 3-bit data in one storage cell. The 3-bit storage cell may have one of eight states (E0, P1 to P7) according to the threshold voltage distribution. E0 represents the erased state, and P1 to P7 represent the programmed states.

[0151] During a read operation, the select read voltages Vrd1 to Vrd7 may be provided to the selected word line sWL, and the pass voltage Vps and / or the read pass voltage Vrdps may be provided to the unselected word line uWL. The pass voltage Vps and / or the read pass voltage Vrdps may be voltages sufficient to turn on the storage cell. For example, the pass voltage Vps may be provided to the adjacent word lines WLk±1, and the read pass voltage Vrdps may be provided to the unselected word lines other than the adjacent word lines.

[0152] The first selected read voltage Vrd1 may be a voltage level between the erased state E0 and the first programmed state P1. The second selected read voltage Vrd2 may be a voltage level between the first programmed state P1 and the second programmed state P2. In this way, the seventh selected read voltage Vrd7 may be a voltage level between the sixth programmed state P6 and the seventh programmed state P7.

[0153] When the first selected read voltage Vrd1 is applied, the memory cells in the erased state E0 may be on-cells, and the memory cells in the first to seventh programmed states P1 to P7 may be off-cells. When the second selected read voltage Vrd2 is applied, the memory cells in the erased state E0 and the first programmed state P1 may be on-cells, and the memory cells in the second to seventh programmed states P2 to P7 may be off-cells. In this way, when the seventh selected read voltage Vrd7 is applied, the memory cells in the erased state E0 and the first to sixth programmed states P1 to P6 may be on-cells, and the memory cells in the seventh programmed state P7 may be off-cells.

[0154] During a read operation, the k-th word line WLk may be selected. A power supply voltage may be applied to the string select line SSL1 and the ground select line GSL1, and the string select transistor SST and the ground select transistor GST may be turned on. In addition, a selected read voltage Vrd may be provided to the selected word line sWL, and a read pass voltage Vrdps and / or a pass voltage Vps may be provided to the unselected word lines uWL.

[0155] When the read operation of the k-th word line WLk is repeatedly executed, a high voltage read pass voltage Vrdps may be repeatedly provided to the remaining word lines. At this time, read interference may occur in the remaining word lines, and thus the threshold voltage may be distorted. When a selected read voltage is provided, the memory cells connected to the k-th word line WLk may be off-cells. For example, when the threshold voltage of the k-th memory cell is higher than the selected read voltage, the k-th memory cell may be an off-cell. When the k-th memory cell is an off-cell, the channel may be separated at the k-th memory cell. For example, the lower channel of the k-th memory cell may receive a ground voltage from the common source line CSL, and the upper channel of the k-th memory cell may have a negative channel voltage.

[0156] A channel voltage difference may occur between the lower channel and the upper channel inserted between the k-th memory cells. Due to the channel voltage difference, hot carrier injection (HCI) may occur in the adjacent memory cells MCk+1 and / or MCk-1. For this reason, the threshold voltage of the memory cells connected to the adjacent word lines WLk+1 and / or WLk-1 may be distorted. For example, the threshold voltage of the memory cells in the erased state E0 may rise to enter the programmed state.

[0157] In the flash memory 3100, during the process of reading data stored in the memory cells, cell degradation may occur due to read interference. If a high-voltage read pass voltage is repeatedly applied to unselected word lines, the memory cells may be stressed. The threshold voltage of the stressed memory cells may increase. Therefore, read failures may occur during the read operation.

[0158] The buffer memory of the mobile device may be insufficient. For example, the flash memory 3100 can provide hot data frequently accessed in a mobile device with insufficient buffer memory to the host without degrading the memory cells. The storage device 3000 does not perform operations of programming or reading the memory cells during the data latch usage operation. Therefore, the storage device 3000 can not only reduce cell degradation (such as that of the buffer memory 3300), but also provide the data stored in the data latch to the host at high speed.

[0159] Figure 18 is a circuit diagram showing Figure 16 the first page buffer PB1 shown. Refer to Figure 18 , the first page buffer PB1 is connected to the first bit line BL1. The fifth memory cell MC5 of the selected memory cell sMC can be connected to the first bit line BL1. The fifth word line WL5 of the selected word line sWL can be connected to the fifth memory cell MC5. The first bit line BL1 can be connected to the common source line CSL through the fifth memory cell MC5.

[0160] The first NMOS transistor NM1 can be included between the first bit line BL1 and the first node N1. The first NMOS transistor NM1 can be a bit line selection transistor driven by a bit line selection signal BLSLT. The bit line selection transistor can be implemented as a high-voltage transistor. The bit line selection transistor can be disposed in a high-voltage region.

[0161] The second NMOS transistor NM2 can be included between the first node N1 and the second node N2. The second NMOS transistor NM2 can be a bit line cut-off transistor driven by a bit line cut-off signal BLSHF. The third NMOS transistor NM3 can be included between the second node N2 and the third node N3. The third NMOS transistor NM3 can be a bit line clamping transistor driven by a bit line clamping control signal BLCLAMP. The fourth NMOS transistor NM4 can be included between the second node N2 and the sense node SO. The fourth NMOS transistor NM4 can be a bit line connection transistor driven by a bit line connection control signal CLBLK.

[0162] The first PMOS transistor PM1 may be included between the sense node SO and the power terminal. The first PMOS transistor PM1 may be a precharge load transistor driven by a load signal LOAD. The second PMOS transistor PM2 may be included between the sense node SO and the third node NM3. The second PMOS transistor PM2 may be a bit line setup transistor driven by a bit line setup signal BLSETUP. The third PMOS transistor PM3 may be included between the third node NM3 and the power terminal. The third PMOS transistor PM3 may be a precharge transistor driven by an inverted latch node Lat_nS.

[0163] A sense latch SL, a force latch FL, a most significant bit latch ML, and a least significant bit latch LL may be connected to the sense node SO. The sense latch SL may store the data stored in the selected memory cell sMC or the sensing result of the threshold voltage of the selected memory cell sMC during a read or program verification operation. In addition, the sense latch SL may be used to apply a program bit line voltage or a program inhibit voltage to the first bit line BL1 during a program operation. The force latch FL may be used to improve the threshold voltage distribution during a program operation. The most significant bit latch ML and the least significant bit latch LL may be used to store data input from the outside during a program operation.

[0164] The sense latch SL may include a latch LAT connected between a latch node Lat_S and an inverted latch node Lat_nS. The latch LAT may include a first inverter INV1 and a second inverter INV2. The input terminal of the first inverter INV1 and the output terminal of the second inverter INV2 may be connected to the inverted latch node Lat_nS. The output terminal of the first inverter INV1 and the input terminal of the second inverter INV2 may be connected to the latch node Lat_S.

[0165] The inverted latch node Lat_nS may be connected to the gate terminal of the third PMOS transistor PM3. When the inverted latch node Lat_nS is at a low level, the third PMOS transistor PM3 may be turned on, and the third node N3 may become the supply voltage level. When the inverted latch node Lat_nS is at a high level, the power terminal and the third node N3 may be disconnected.

[0166] The fifth NMOS transistor NM5 may be included between the latch node Lat_S and the fourth node N4. The fifth NMOS transistor NM5 may be used to reset the latch node Lat_S in response to a latch reset signal RST_S. The latch reset signal RST_S may be provided from the control logic 1160. The sixth NMOS transistor NM6 may be included between the inverted latch node Lat_nS and the fifth node N5. The sixth NMOS transistor NM6 may be used to set the latch node Lat_S in response to a latch set signal SET_S. The latch set signal SET_S may be provided from the control logic 1160.

[0167] The seventh NMOS transistor NM7 may be included between the fifth node N5 and the ground terminal. The seventh NMOS transistor NM7 may adjust the voltage level of the fifth node N5 in response to a refresh signal RFSH. The refresh signal RFSH may be provided from the control logic 1160. The eighth NMOS transistor NM8 may be included between the fourth node N4 and the ground terminal. The eighth NMOS transistor NM8 may adjust the voltage level of the fourth node N4 in response to the voltage level of the sense node SO.

[0168] Figure 19 is a block diagram showing an example of a page buffer latch input / output circuit (e.g., Figure 14 the page buffer latch input / output circuit shown). Referring to Figure 19 , the flash memory 3100 may include a memory cell array 3110, an address decoder 3120, a page buffer circuit 3130, a control logic 3160, and a page buffer latch input / output circuit 2000. The memory cell array 3110 may be connected to the address decoder 3120 through the k-th word line (WLk). A column repair unit (CR unit) and a main unit may be connected to the k-th word line (WLk).

[0169] The column repair page buffer (CR P / B) may include a plurality of page buffers. The plurality of page buffers may be divided into page buffers that perform column repair operations and page buffers that do not perform column repair operations.

[0170] Data to be stored in the main unit may be stored in the memory cells connected to the page buffers for which column repair operations have been performed. Data may not be stored in the memory cells connected to the page buffers for which column repair operations have not been performed. The flash memory 3100 may perform data latch usage operations using the data latches of the page buffers for which column repair operations have not been performed.

[0171] Additionally, the flash memory 3100 generally does not use the page buffers connected to the faulty cells ("faulty page buffers"). The flash memory 3100 can use the data latches of the faulty page buffers as an alternative to the buffer memory 3300 through the page buffer latch input / output circuit 2000.

[0172] The page buffer circuit 3130 can include a first page buffer to a z-th page buffer (PB1 to PBz). The first page buffer PB1 can be a column repair page buffer connected to a column repair unit (CR unit). The z-th page buffer (PBz) can be a faulty page buffer connected to a faulty master unit.

[0173] The page buffer latch input / output circuit 2000 can use the data latches of the column repair page buffer (e.g., PB1) and the faulty page buffer (e.g., PBz) of the page buffer circuit 3130 like the buffer memory 3300 through the data latches. For example, the 11th to 14th data latches (DL11 to DL14) of the first page buffer PB1 and the z1th to z4th data latches (DLz1 to DLz4) of the z-th page buffer PBz can be used as an alternative to the buffer memory 3300.

[0174] The page buffer latch control module 1234 can control the data latch usage operation of the page buffer latch input / output circuit 2000 based on the faulty page buffer unit and / or based on the column repair page buffer unit. The page buffer latch control module 1234 can use the data latches of the page buffer circuit 3130 like the buffer memory 3300 through the data latch usage operation. By using the data latches of the page buffer circuit 3130 like the buffer memory 3300, the availability of the buffer memory 3300 can be increased.

[0175] Figure 20 is a block diagram showing an example of a configuration in which data is provided to a host during a data latch usage operation (e.g., Figure 19 the operations shown in).

[0176] The storage device 3000 can store the original data in the data latches (e.g., DL11 to DL14, DLz1 to DLz4) during the data latch usage operation. Here, the original data can be data provided from the host or data on which ECC or a randomizer has been performed. Error-free data can be stored in the data latches of the page buffer circuit 3130 because it passes through the ECC or the randomizer.

[0177] The storage device 3000 can output the data stored in the data latch of the page buffer circuit 3130 to the host through the page buffer latch input / output circuit 2000 during the data latch usage operation without performing a separate read operation. The data output from the page buffer latch input / output circuit 2000 can be raw data that has not been programmed into the memory cells of the flash memory 3100 / has not been read from the memory cells of the flash memory 3100. Therefore, the memory controller 3200 may not perform an ECC operation.

[0178] When outputting data (DOUT) from the page buffer latch input / output circuit 2000, the page buffer latch control module 1234 can provide an ECC_OFF signal to the ECC circuit 3400. The ECC circuit 3400 can receive the ECC_OFF signal and not perform an ECC operation. The output data (DOUT) can be directly provided to the host.

[0179] Figure 21 is a block diagram showing an example of implementing a storage device using a solid state drive (SSD). Refer to Figure 21 , the SSD 4000 can include a plurality of flash memories 4101 to 4104 and an SSD controller 4200.

[0180] The first flash memory 4101 and the second flash memory 4102 can be connected to the SSD controller 4200 through the first channel CH1. The third flash memory 4103 and the fourth flash memory 4104 can be connected to the SSD controller 4200 through the second channel CH2. The number of channels connected to the SSD controller 4200 can be two or more. The number of flash memories connected to one channel can be two or more.

[0181] The SSD controller 4200 can include a host interface 4201, a flash interface 4202, a buffer interface 4203, a control unit 4210, and a working memory 4220. The SSD controller 4200 can be connected to the host 1500 through the host interface 4201. Depending on the request of the host 1500, the SSD controller 4200 can write data into the corresponding flash memory or can read data from the corresponding flash memory.

[0182] The SSD controller 4200 can be connected to a plurality of flash memories 4101 to 4104 through the flash interface 4202, and can be connected to the buffer memory 1300 through the buffer interface 4203. The flash interface 4202 can provide the data temporarily stored in the buffer memory 1300 to the flash memory through the channels CH1 and CH2. The flash interface 4202 can transfer the data read from the flash memories 4101 to 4104 to the buffer memory 1300.

[0183] The control unit 4210 can analyze and process signals received from the host 1500. The control unit 4210 can control the host 1500 or the flash memories 4101 to 4104 through the host interface 4201 or the flash interface 4202. The control unit 4210 can control the operations of the flash memories 4101 to 4104 by using the firmware for driving the SSD 4000.

[0184] The SSD controller 4200 can manage data to be stored in the flash memories 4101 to 4104. In the event of a sudden power failure, the SSD controller 4200 can back up the data stored in the working memory 4220 or the buffer memory 1300 to the flash memories 4101 to 4104.

[0185] The SSD controller 4200 can be configured to use the data latches of the flash memories 4101 to 4104 as described in reference Figures 1 to 20 as mentioned.

[0186] Although this disclosure contains many specific implementation details, these should not be construed as limitations on the scope that may be claimed. Certain features described in the context of separate embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although the features may be described above as acting in certain combinations, in some cases one or more features from the combination may be removed from the combination, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0187] Although the present disclosure has been described with reference to various examples, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: A memory cell array, which includes a first memory cell for storing user data and a second memory cell for performing column repair on the first memory cell; A page buffer circuit, which includes a first page buffer connected to the first memory cell and a second page buffer connected to the second memory cell; And A page buffer latch input / output circuit, which is configured to use at least one data latch of the second page buffer as an alternative to buffer memory during a data latch usage operation.

2. The memory device according to claim 1, wherein the page buffer latch input / output circuit includes: A column repair fuse circuit, which is configured to store address information of the first memory cell and the second memory cell; A column address comparator, which is configured to compare the address of the first memory cell with an input address and generate an address comparison signal based on the result of the comparison; And A page buffer selector, which is configured to select the second page buffer based on the address comparison signal.

3. The memory device according to claim 2, wherein, The page buffer selector is configured to store data in at least one data latch of the second page buffer during the data latch usage operation.

4. The memory device according to claim 3, wherein, The column repair fuse circuit is configured to control the second page buffer such that data is not stored in the second memory cell during the data latch usage operation.

5. The memory device according to claim 1, wherein, The page buffer latch input / output circuit is configured to receive a data latch usage mode signal from a memory controller and perform the data latch usage operation based on the data latch usage mode signal.

6. The memory device according to claim 1, wherein, The page buffer latch input / output circuit is configured to perform the data latch usage operation using a plurality of page buffers as a unit, and the plurality of page buffers includes the second page buffer.

7. The memory device according to claim 1, wherein, The first memory cell and the second memory cell are flash memory cells.

8. The memory device according to claim 7, wherein, The first memory cell and the second memory cell each store multi-bit data, and each of the first and second page buffers includes a plurality of data latches for storing the multi-bit data.

9. A memory device, comprising: A memory cell array, which includes a first memory cell for storing user data and a second memory cell for performing column repair on the first memory cell; A page buffer circuit, which includes a first page buffer connected to the first memory cell and a second page buffer connected to the second memory cell; And A page buffer latch input / output circuit, which is configured to use at least one data latch of the first page buffer as an alternative to buffer memory during a data latch usage operation when the first memory cell fails.

10. The memory device according to claim 9, wherein, The page buffer latch input / output circuit includes: A column repair fuse circuit, which is configured to store address information of the first memory cell and the second memory cell; A column address comparator, which is configured to compare the address of the first memory cell with an input address and generate an address comparison signal based on the comparison; and A page buffer selector configured to select the second page buffer based on the address comparison signal during the data latch usage operation.

11. The memory device according to claim 10, wherein, The page buffer selector is configured to store data in at least one data latch of the first page buffer during the data latch usage operation.

12. The memory device according to claim 11, wherein, The column repair fuse circuit is configured to control the first page buffer such that data is not stored in the first memory cell during the data latch usage operation.

13. The memory device according to claim 9, wherein, The page buffer latch input / output circuit is configured to perform the data latch usage operation using a plurality of page buffers as a unit, the plurality of page buffers including the first page buffer.

14. A storage device, comprising: A memory device including a first memory cell for storing user data, a second memory cell for performing column repair on the first memory cell, a first page buffer connected to the first memory cell, and a second page buffer connected to the second memory cell; And A memory controller configured to control the memory device to use at least one data latch of the first page buffer or the second page buffer as an alternative to the buffer memory of the memory controller during a data latch usage operation.

15. The storage device according to claim 14, wherein, The memory device includes: A column repair fuse circuit configured to store address information of the first memory cell and the second memory cell; A column address comparator configured to compare the address of the first memory cell with an input address and generate an address comparison signal based on the comparison; and A page buffer selector configured to select the second page buffer based on the address comparison signal.

16. The storage device according to claim 15, wherein, The page buffer selector is configured to store data in at least one data latch of the first page buffer or the second page buffer during the data latch usage operation.

17. The storage device according to claim 16, wherein, The column repair fuse circuit is configured to control the first page buffer or the second page buffer such that data is not stored in the first memory cell or the second memory cell during the data latch usage operation.

18. The storage device according to claim 15, wherein, The page buffer selector is configured to perform the data latch usage operation using a plurality of page buffers as a unit, the plurality of page buffers including the first page buffer.

19. The storage device according to claim 14, wherein, The memory controller includes a page buffer latch control module, and wherein the page buffer latch control module is configured to control the memory device to perform the data latch usage operation.

20. The storage device according to claim 19, wherein, The page buffer latch control module is configured to provide data from the at least one data latch of the first page buffer or the second page buffer used as an alternative to the buffer memory to a host without performing an error correction code (ECC) operation.

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