Electronic device and 3D chip packaging structure thereof

Abstract

The invention discloses an electronic device which comprises a plurality of circuit units and a compensation circuit. The plurality of circuit units are connected in parallel with each other and are electrically connected with the power supply end to receive the power supply voltage. The compensation circuit is electrically connected with the plurality of circuit units and outputs compensation voltage to the electrically connected circuit units, and at least one of the circuit units is far away from the power supply end.

Description

Technical Field

[0001] This application relates to a semiconductor device and a semiconductor package structure, particularly to an electronic device and its 3D chip package structure. Background Art

[0002] As the user's demand for the data volume and computing power of electronic products is increasing, and in order to meet the requirement of thin, light, short, and small for electronic products, semiconductor devices continue to develop in the direction of smaller volume, lower power consumption, and higher bandwidth.

[0003] However, with the increase in data volume and computing power, the number of electronic components and circuits required inside the semiconductor device also increases accordingly, and the number of pins required for the semiconductor device also increases significantly. In order to meet the requirement of reducing the volume of the semiconductor device, the number of pins of the semiconductor device needs to be minimized as much as possible. In the case of reducing the number of pins, it may lead to the occurrence of unstable power supply in the internal circuit of the semiconductor device.

[0004] Therefore, how to propose a semiconductor device with stable power supply is one of the problems urgently to be solved in this field. Summary of the Invention

[0005] In order to solve the above technical problems, this application proposes an electronic device and its 3D chip package structure, which can compensate the power supply voltage inside the electronic device, so that the internal circuit of the electronic device can operate normally under a stable power supply voltage, achieving the purpose of enabling the integrated circuit chip to stably provide the power supply voltage.

[0006] In order to achieve the above purpose, this application proposes an electronic device, which includes a plurality of circuit units and a compensation circuit. The plurality of circuit units are connected in parallel with each other and are electrically connected to a power supply terminal to receive a power supply voltage. The compensation circuit is electrically connected to the plurality of circuit units and outputs a compensation voltage to the plurality of electrically connected circuit units, and at least one of the plurality of circuit units is far from the power supply terminal.

[0007] In order to achieve the above purpose, this application proposes a 3D chip package structure, which includes the aforementioned electronic device. The electronic device includes a memory crystal layer and a connection layer. The memory crystal layer includes at least one memory partition. The connection layer is located on one side of the memory crystal layer and is configured with at least one connection pad. Among them, at least one connection clearance area and at least one connection area are defined in the connection layer corresponding to at least one memory partition. At least one connection clearance area is adjacent to at least one connection area, and the area of at least one connection clearance area is equal to or greater than that of at least one connection area. At least one connection pad is only configured in at least one connection area.

[0008] Based on the above, an embodiment of the electronic device and its 3D chip packaging structure according to the present application includes a compensation circuit, and the compensation circuit is used to output a compensation voltage to the circuit unit to compensate for the power supply voltage that decays due to being far from the power supply end, so that the circuit unit can operate normally with sufficient power supply voltage, achieving the purpose of enabling the integrated circuit chip to stably provide the power supply voltage. Description of the Drawings

[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions thereof are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0010] Figure 1 It is a schematic diagram of an embodiment of an electronic device according to an embodiment of the present application.

[0011] Figure 2 It is a schematic diagram of an embodiment of an electronic device according to an embodiment of the present application.

[0012] Figure 3 It is a schematic diagram of an embodiment of a 3D chip packaging structure according to an embodiment of the present application. Detailed Embodiments

[0013] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0014] Please refer to Figure 1 , Figure 1 It is a schematic diagram of an embodiment of an electronic device according to the present application. In this embodiment, the electronic device takes a memory device as an example, and the circuit unit takes a storage unit as an example. The memory device 10 includes a memory crystal layer 11 and a connection layer 12, and the connection layer 12 is located on one side of the memory crystal layer 11. The memory crystal layer 11 includes at least one memory partition 111 and at least one compensation circuit 112, and at least one memory partition 111 is electrically connected to at least one compensation circuit 112. In this embodiment, a plurality of memory partitions 111 (111a, 111b) are taken as an example, and the present application is not limited thereto.

[0015] The connection layer 12 is used to configure at least one connection pad 121. At least one connection pad 121 is electrically connected to the corresponding memory partition 111, and at least one connection pad 121 is in contact connection with the corresponding conductive column 20. In this embodiment, a plurality of connection pads 121 are taken as an example, but the present application is not limited thereto.

[0016] Further, the connection layer 12 is defined with at least one connection clearance area 13 and at least one connection area 14. The at least one connection clearance area 13 and the at least one connection area 14 are arranged adjacent to each other. In this embodiment, at least one connection pad 121 is only arranged in the at least one connection area 14. That is, at least one connection pad 121 is not arranged in the at least one connection clearance area 13.

[0017] In one embodiment, at least one connection pad 121 can be implemented by HBL and HBC.

[0018] In this embodiment, the memory device 10 is implemented as a High Bandwidth Memory (HBM).

[0019] Further, at least one conductive pillar 20 is only arranged corresponding to the at least one connection area 14. That is, at least one conductive pillar 20 is not arranged in the at least one connection clearance area 13. As shown in Figure 1 the figure, a plurality of conductive pillars 20 are only arranged corresponding to the connection area 14 on the left and right sides of the figure corresponding to the memory device 10. In this embodiment, each conductive pillar 20 is in contact connection with the connection pad 121 arranged corresponding to the at least one connection area 14. Therefore, in this embodiment, the number of at least one conductive pillar 20 corresponds to the number of at least one connection pad 121. That is, the number of at least one conductive pillar 20 is the same as the number of at least one connection pad 121. In this embodiment, a plurality of conductive pillars 20 are electrically connected to an external circuit to individually receive a power supply voltage, a compensation power supply voltage, or a ground connection from the external circuit. In one embodiment, at least one conductive pillar 20 can be implemented by a multi-layer metal layer, and the present application is not limited thereto.

[0020] Further, taking the memory partition 111a as an example to illustrate the architecture of each memory partition 111. The memory partition 111a includes a plurality of memory cells 1111. The plurality of memory cells 1111 are connected in parallel with each other, and one end of the plurality of memory cells 1111 is electrically connected to the corresponding power supply terminal VDD1 to receive a power supply voltage, and the other end of the plurality of memory cells 1111 is electrically connected to the corresponding ground terminal GND1 to be grounded. Among them, the power supply terminal VDD1 is electrically connected to the corresponding connection pad 121 (such as Figure 1 the connection pad 121 in the left connection area 14) to receive the power supply voltage from the external circuit. The ground terminal GND1 is electrically connected to the corresponding other connection pad 121 (such as Figure 1 the other connection pad 121 in the left connection area 14) to be grounded through the corresponding connection pad 121. The architecture of the memory partition 111b is the same as that of the memory partition 111a, and the power supply terminal VDD2 is electrically connected to the corresponding connection pad 121 (such as Figure 1electrically connected to another connection pad 121) in the right connection area 14, receives the power supply voltage from an external circuit, and the ground terminal GND2 is electrically connected to the corresponding another connection pad 121 (such as Figure 1 electrically connected to another connection pad 121) in the right connection area 14, so as to be grounded through the corresponding connection pad 121, and thus will not be elaborated herein.

[0021] Further, one end of the compensation circuit 112a is electrically connected to the compensation power supply terminal VDDa1, the other end of the compensation circuit 112a is electrically connected to one end of the memory cell 1111 in the memory partition 111a, and outputs a compensation voltage to the electrically connected one end of the memory cell 1111. Among them, the compensation power supply terminal VDDa1 is electrically connected to the corresponding connection pad 121 (such as Figure 1 electrically connected to another connection pad 121) in the left connection area 14 of the middle, so as to receive the compensation power supply voltage from an external circuit. Similarly, one end of the compensation circuit 112b is electrically connected to the compensation power supply terminal VDDa2, the other end of the compensation circuit 112b is electrically connected to one end of the memory cell 1111 in the memory partition 111b, and outputs a compensation voltage to the electrically connected memory cell 1111. Among them, the compensation power supply terminal VDDa2 is electrically connected to the corresponding connection pad 121 (such as Figure 1 electrically connected to another connection pad 121) in the right connection area 14 of the middle, so as to receive the compensation power supply voltage from an external circuit.

[0022] Since the power supply voltage is only provided to the power supply terminal VDD1 through the corresponding connection pad 121, the position of the power supply terminal VDD1 will be limited by the position of the connection pad 121, that is, when the input ports (or pins) of the power supply voltage are limited, a plurality of memory cells 1111 need to be supplied with the power supply voltage through the same power supply terminal VDD1. However, the power supply voltage will attenuate during the transmission process due to the trace length or manufacturing defects, resulting in that the memory cells 1111 far from the power supply terminal VDD1 (such as the memory cell 1111a) cannot perform read and write operations with sufficient power supply voltage, and are more likely to cause errors in judging the read data due to the attenuation of the power supply voltage compared with other memory cells 1111. Therefore, in this application, a compensation circuit 112 is configured in the electronic device, and the compensation circuit 112 provides a compensation voltage to the memory cell 1111 to compensate for the attenuated power supply voltage, so that the memory cells 1111 electrically connected to the same power supply terminal VDD1 can all perform corresponding read and write operations with sufficient power supply voltage, avoiding the occurrence of errors in judging the read data.

[0023] In this embodiment, the voltage value of the compensation power supply voltage is greater than the voltage value of the compensation voltage, and the voltage value of the power supply voltage is the same as the voltage value of the compensation voltage.

[0024] In this embodiment, a compensation circuit 112 is electrically connected to the memory partition 111a as an example for illustration. However, the number of compensation circuits 112 can be increased according to the number of memory cells 1111 in the memory partition 111a and / or the power supply voltage requirement, and this application is not limited to this example.

[0025] In one embodiment, the compensation circuit 112 is a low-dropout regulator (LDO).

[0026] Please refer to Figure 2 , Figure 2 FIG. is a schematic diagram of another embodiment of an electronic device according to the present application. In this embodiment, the electronic device takes a logic circuit device as an example, and the circuit unit takes a circuit component as an example.

[0027] The logic circuit device 30 includes a plurality of circuit components 32, a compensation circuit 33, and a plurality of connection pads 40.

[0028] One end of the plurality of circuit components 32 is electrically connected to the power supply terminal VDD3, the other end of the plurality of circuit components 32 is electrically connected to the ground terminal GND3, and the plurality of circuit components 32 are connected in parallel to each other. Among them, the power supply terminal VDD3 is electrically connected to the corresponding connection pad 40 to receive the power supply voltage from an external circuit, and the ground terminal GND3 is electrically connected to the corresponding other connection pad 40 to be grounded through the corresponding connection pad 40.

[0029] One end of the compensation circuit 33 is electrically connected to the compensation power supply terminal VDDa3, the other end of the compensation circuit 33 is electrically connected to one end of the circuit component 32 of the plurality of circuit components 32, and a compensation voltage is output to the electrically connected circuit component 32. Among them, the compensation power supply terminal VDDa3 is electrically connected to the corresponding connection pad 40 for receiving the compensation power supply voltage from an external circuit.

[0030] In this embodiment, the voltage value of the compensation power supply voltage is greater than the voltage value of the compensation voltage, and the voltage value of the power supply voltage is the same as the voltage value of the compensation voltage.

[0031] In this embodiment, a compensation circuit 33 is taken as an example for illustration. However, the number of compensation circuits 33 can be increased according to the number of circuit components 32 and / or the power supply voltage requirement, and this application is not limited to this example.

[0032] In one embodiment, the compensation circuit 33 is a low-dropout regulator (LDO).

[0033] In one embodiment, the circuit component 32 can be a circuit component such as a controller circuit or a processor circuit, and this application is not limited thereto.

[0034] In this embodiment, the logic circuit device 30 is an integrated circuit device encapsulated by a wire bonding process.

[0035] Therefore, when the input ports (or pins) of the power supply voltage are limited, the power supply voltage will attenuate during transmission due to the trace length or manufacturing defects, resulting in that the circuit components 32 (such as circuit component 32a) far from the power supply terminal VDD3 cannot operate with sufficient power supply voltage and are more likely to malfunction due to unstable power supply voltage compared with other circuit components 32. Therefore, in this application, a compensation circuit 33 is configured in the electronic device, and a compensation voltage is provided to the circuit components 32 to compensate for the attenuated power supply voltage, so that each circuit component 32 can operate with sufficient power supply voltage and avoid the occurrence of abnormal operation.

[0036] Next, please refer to Figure 3 , Figure 3 which is a schematic diagram of an embodiment of the 3D chip packaging structure of this application. The 3D chip packaging structure 1 includes a memory device 10, a logic circuit device 30, and a substrate 50. The memory device 10 is connected to one side of the logic circuit device 30 through at least one conductive pillar 20, and the substrate 50 is connected to the other side of the logic circuit device 30 through a plurality of connection pads 40. Therefore, the logic circuit device 30 is located between the memory device 10 and the substrate 50.

[0037] In one embodiment, the memory device 10 can be implemented by Figure 1 the embodiment of Figure 2 , and this application is not limited thereto.

[0038] In this embodiment, the connection area 14 corresponding to a memory partition 111 can be adjacent to one side of the memory partition 111. As Figure 3 shown, the connection areas 14 of the memory partition 111a are respectively arranged on the left and right sides of the figure corresponding to the memory partition 111a.

[0039] In this embodiment, a plurality of conductive pillars 20 are only arranged on the left and right sides of the figure corresponding to the memory partition 111a (111b) corresponding to the connection area 14.

[0040] In one embodiment, the memory device 10 can receive the power supply voltage, compensation power supply voltage provided by the logic circuit device 30 or be grounded through the logic circuit device 30 through a plurality of conductive pillars 20.

[0041] The logic circuit device 30 is disposed on one side of the memory device 10 and is coupled to the memory device 10 through a plurality of conductive pillars 20. The logic circuit device 30 includes at least one circuit component 32. In one embodiment, the logic circuit device 30 may further include at least one memory controller 31. At least one memory controller 31 is electrically connected to a corresponding conductive pillar 20. Further, at least one memory controller 31 may be disposed corresponding to at least one connection clearance area 13 and / or at least one connection area 14 of the connection layer 12. For example, as Figure 3 shown, taking a plurality of memory controllers 31 as an example, the plurality of memory controllers 31 may be disposed on at least one side of the logic circuit device 30 corresponding to the connection area 14 of the memory partition 111a. In other embodiments, the plurality of memory controllers 31 may be disposed corresponding to the connection clearance area 13 of the memory partition 111a and away from the side of the logic circuit device 30. In an embodiment where the plurality of memory controllers 31 may be disposed corresponding to the connection area 14 of the memory partition 111a, the plurality of memory controllers 31 may be in contact connection with corresponding conductive pillars 20. In an embodiment where the plurality of memory controllers 31 may be disposed corresponding to the connection clearance area 13 of the memory partition 111a, the plurality of memory controllers 31 may be electrically connected to the conductive pillars 20 through a metal wiring layer (not shown) of the logic circuit device 30.

[0042] Further, at least one circuit component 32 of the logic circuit device 30 is disposed corresponding to at least one connection clearance area 13. The vertical projection of at least one circuit component 32 overlaps with the vertical projection of at least one connection clearance area 13, and the vertical projection of at least one circuit component 32 does not overlap with the vertical projection of at least one connection area 14. For example, Figure 3 the circuit component 32b shown is disposed corresponding to the connection clearance area 13 of the memory partition 111a, and the vertical projection of the circuit component 32b overlaps with the vertical projection of the connection clearance area 13 of the memory partition 111a. In this embodiment, at least one circuit component 32 is implemented by silicon intellectual property (IP) components.

[0043] In one embodiment (as Figure 2 shown), the logic circuit device 30 may be connected to the other side of the substrate 50 through a plurality of connection pads 40 to receive a power supply voltage, a compensation power supply voltage provided by the substrate 50 or be grounded through the substrate 50 through the plurality of connection pads 40.

[0044] In this embodiment, the 3D chip packaging structure 1 is a system on a chip (SoC) implemented by wafer stacking (3D Wafer on Wafer, WoW).

[0045] Since the embodiment of the 3D chip packaging structure 1 provided by the present application includes a connection clearance area 13 and a connection area 14, and the connection pads 121 and the conductive columns 20 are arranged corresponding to the connection area 14, the conductive columns 20 are centrally arranged in the connection area 14 to form the connection clearance area 13. The circuit component 32 does not need to change and / or divide its circuit design according to the distribution position of the conductive columns 20, but can be directly applied to the integrated circuit design in the 3D chip packaging structure 1 with the original circuit design architecture corresponding to the connection clearance area 13. Therefore, the difficulty of circuit design can be effectively simplified, and the overall design cost of the integrated circuit chip can be reduced with the existing quantified circuit components 32, achieving the purpose of improving the design convenience of the integrated circuit chip.

[0046] In summary, the electronic device and the embodiment of its 3D chip packaging structure of the present application include a compensation circuit, and the compensation circuit is used to output a compensation voltage to the circuit unit to compensate for the power supply voltage that decays due to being far from the power supply end, so that the circuit units connected to the same power supply end can operate normally with sufficient power supply voltage, achieving the purpose of enabling the integrated circuit chip to stably provide the power supply voltage. At the same time, the 3D chip packaging structure provided by the present application forms a connection clearance area without arranging conductive columns by arranging the connection pads in a predefined connection area, so that the circuit units of the logic circuit device can be directly applied to the 3D chip packaging structure corresponding to the connection clearance area without changing its internal design, simplifying the difficulty of circuit design, and reducing the overall design cost of the integrated circuit chip with the existing circuit units. Therefore, the present application can achieve the purpose of improving the design convenience of the integrated circuit chip.

[0047] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0048] The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, all of which belong to the protection scope of the present application.

Claims

1. An electronic device, characterized in that, Comprising: A plurality of circuit units, the plurality of circuit units being connected in parallel with each other and electrically connected to a power supply terminal to receive a power supply voltage; And A compensation circuit, electrically connected to the plurality of circuit units and outputting a compensation voltage to the plurality of electrically connected circuit units, at least one of the plurality of circuit units being away from the power supply terminal.

2. The electronic device according to claim 1, wherein Wherein, The compensation circuit is a low dropout linear regulator circuit.

3. The electronic device according to claim 1, wherein Wherein, The voltage value of the power supply voltage is the same as the voltage value of the compensation voltage.

4. The electronic device according to claim 1, characterized in that, Wherein, The electronic device is a logic circuit device, and the plurality of circuit units are circuit components.

5. The electronic device according to claim 1, wherein Wherein, The electronic device is a memory device, and the plurality of circuit units are memory cells.

6. A 3D chip packaging structure, characterized in that, Comprising: The electronic device according to claim 1, comprising: A memory crystal layer including at least one memory partition; and A connection layer located on one side of the memory crystal layer and configured with at least one connection pad; Wherein, at least one connection clearance area and at least one connection area are defined in the connection layer corresponding to the at least one memory partition, the at least one connection clearance area is adjacent to the at least one connection area, the area of the at least one connection clearance area is equal to or greater than that of the at least one connection area, and the at least one connection pad is only configured in the at least one connection area.

7. The 3D chip packaging structure according to claim 6, wherein Wherein, The memory device further includes at least one conductive pillar, and the at least one conductive pillar is connected to the at least one connection pad and is configured corresponding to the at least one connection area.

8. The 3D chip package structure according to claim 6, wherein The at least one connection area is adjacent to one side edge of the at least one memory partition.

9. The 3D chip packaging structure according to claim 7, wherein, The at least one conductive pillar is electrically connected to the power supply terminal.

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