Distributed bonding packaging method for improving wafer stacking yield

Abstract

The invention relates to the technical field of chip packaging, in particular to a distributed bonding packaging method for improving the wafer stacking yield. Comprising the following steps: S1, stripping Fail Die on a first wafer; s2, a second wafer and a Good Die are provided, and the Good Die is mixed and bonded to the second wafer; s3, carrying out hybrid bonding on the first wafer and the second wafer, wherein the Good Die is located in the Fail Die region stripped from the first wafer; s4, thinning the back surface of the first wafer until the Good Die region is exposed; s5, etching the silicon layer of the first wafer, and exposing the TSV structure in the first wafer; s6, after cleaning, filling is conducted through a PECVD technology; and S7, through CMP polishing and cleaning, Cu is exposed. Compared with the prior art, a distributed bonding mode of bonding the good die with the wafer of which the fail die is excavated is adopted, so that the overall yield of wafer-level bonding is improved. Compared with the bonding after the wafer is directly repaired, the distributed bonding has the advantage that the steps of glue pasting Die for repairing the wafer and subsequent coplanar adjustment are omitted.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and specifically relates to a distributed bonding packaging method for improving the yield of wafer stacking. Background Art

[0002] In the current packaging field, especially in the packaging field of memory chips, in consideration of expanding the storage capacity of a single package, a stacking form is generally considered. With the continuous improvement of the integration degree, that is, the distance between the chip pads (Pads) is getting smaller and smaller, simple bump bonding stacking can no longer meet the process requirements. Therefore, the later development will focus on bump-free bonding. In the case of too low production capacity in the Die to wafer mode, the high-production-capacity wafer-level bonding mode will be vigorously promoted. However, for wafer-level stacking, after multiple wafer-level stackings, fail dies will appear on the wafer surface, resulting in an exponential decrease in the yield of the wafer, which does not meet the requirement of high yield of the wafer itself. Summary of the Invention

[0003] The present invention aims to overcome the deficiencies of the prior art and provides a distributed bonding packaging method for improving the yield of wafer stacking.

[0004] To achieve the above object, a distributed bonding packaging method for improving the yield of wafer stacking is designed, including the following steps: S1, stripping the Fail Dies on the first wafer; S2, providing a second wafer and Good Dies, and hybrid bonding the Good Dies to the second wafer; S3, hybrid bonding the first wafer and the second wafer, with the Good Dies located within the area of the Fail Dies stripped on the first wafer; S4, thinning the back surface of the first wafer until the Good Die area is exposed; S5, etching the silicon layer of the first wafer and exposing the TSV structure inside the first wafer; S6, after cleaning, filling through the PECVD process; S7, polishing and cleaning through CMP and exposing Cu.

[0005] The specific method of the step S1 includes the following steps: S11, excavating the scribe lane outside the Fail Dies to a specified depth; S12, attaching a film layer to the front surface of the first wafer; S13, using the infrared laser penetration characteristic on the back surface of the first wafer to focus to a specified depth for lateral surface ablation to form a modified layer in the back Fail Die area; S14, using ultrasonic vibration to break the modified layer; S15, tearing off the film layer, thereby stripping the Fail Dies.

[0006] In step S13, the specified depth of infrared laser focusing is from the back surface of the first wafer to the bottom of the groove dug in step S11.

[0007] In step S13, during laser ablation, an infrared band of 1000 - 1500 um is selected, the spot size is controlled within 1 - 3 um, the energy is 1 - 3 W, and the step overlap is 50% - 80% for X - Y direction scanning.

[0008] The depth of the groove dug in step S11 is greater than the thickness of the filled Die in step S6.

[0009] The depth of the groove dug in step S11 is 50 - 100 um.

[0010] In step S2, the bonding position of the Good Die matches the position of the Fail Die area peeled from the first wafer.

[0011] In step S6, TEOS liquid source is used for CVD growth.

[0012] It further includes the following steps: S8, repeat steps S1 to S7 to complete multi - layer stacking; S9, perform BVR and bump manufacturing processes on the bottom wafer; S10, dicing to form a particle stacking structure.

[0013] Compared with the prior art, the present invention uses a distributed bonding method of first bonding the good die, and then bonding it with the wafer from which the fail die has been dug out, which improves the overall yield of wafer - level bonding. This distributed bonding, compared with the bonding after directly repairing the wafer, omits the steps of gluing the Die on the repaired wafer and subsequent coplanarity adjustment. In addition, without the introduction of organic adhesives, it reduces the surface abnormalities caused by residual glue sticking to the grinding wheel during subsequent thinning and planarization, making the subsequent bonding process easier to perform. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic flow diagram of the present invention.

[0015] Figure 2 It is a schematic diagram of the BVR process in step S9 of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention will be further described below with reference to the accompanying drawings.

[0017] As Figure 1 shown, the distributed bonding and packaging method for improving the yield of wafer stacking in this embodiment includes the following steps: S1. Debond the Fail Die 3 on the first wafer 1; S2. Provide the second wafer 2 and Good Die 4, and hybrid bond the Good Die 4 to the second wafer 2; S3. Hybrid bond the first wafer 1 and the second wafer 2, with the Good Die 4 located within the area of the removed Fail Die 3 on the first wafer 1; S4. Thinning the backside of the first wafer 1 until the Good Die 4 area is exposed; S5. Etch the silicon layer 1-1 of the first wafer 1 by dry etching to expose the TSV structure 1-2 inside the first wafer 1; S6. After cleaning, perform filling by PECVD process; S7. Clean by CMP polishing to expose Cu. At this time, one layer of wafer-level bonding process is completed; S8. Repeat steps S1 to S7 to complete multi-layer stacking; S9. Perform BVR and bump manufacturing processes on the bottom wafer; S10. Dicing to form a particle stacking structure.

[0018] The specific method of step S1 includes the following steps: S11. Excavate the scribe lane outside the Fail Die 3 to a specified depth; S12. Attach the film layer 5 on the front side of the first wafer 1; S13. Use the infrared laser penetration characteristic on the backside of the first wafer 1 to focus to a specified depth for lateral surface ablation to form a modified layer in the backside Fail Die 3 area; S14. Make the modified layer rupture by ultrasonic vibration; S15. Tear off the film layer 5 to debond the Fail Die 3.

[0019] The specified depth of infrared laser focusing in step S13 is from the backside of the first wafer 1 to the bottom of the excavation groove in step S11. In this embodiment, the thickness of the first wafer is 780um, the depth of the excavation groove is 100um, and the specified depth of infrared laser focusing is 680um.

[0020] In step S13, during laser ablation, select the infrared band of 1000~1500um, control the spot size at 1~3um, the energy at 1~3W, and the step overlap at 50%~80% for X-Y direction scanning. By laser ablation technology, shorten the longitudinal crack and expand the transverse crack.

[0021] The depth of excavation in step S11 is greater than the thickness of the filled Die in step S6. Specifically in use, the depth of excavation is 50-100um.

[0022] In step S2, the bonding position of the Good Die 4 matches the position of the removed Fail Die 3 area on the first wafer 1 to ensure that...

[0023] In step S6, use TEOS liquid source for CVD growth to ensure filling performance.

[0024] In step S2, the bonding surfaces of the Good Die 4 and the second wafer 2 are basically defect-free, making them easy to bond and the process difficultly low. In step S3, the surface of the first wafer 1 from which the Fail Die has been removed is relatively easy to clean, and the surface of the wafer after Die to Wafer is basically defect-free, making it easy to bond and the process difficultly low. By replacing the single bonding after the complex steps of repairing the wafer with two bonding methods, the present invention reduces the process difficulty.

[0025] As Figure 2 shown, in the BVR process in step S9, specifically, first, the back surface of the bottommost wafer is physically thinned without exposing the TSVs inside the wafer, then it is chemically thinned by dry etching to expose the TSVs, then a PECVD dielectric layer thin film is deposited on it, and finally it is polished by CMP to expose the Cu. The whole process is the BVR (Backside Via Reveal) process, which facilitates the formation of electrical connections with the bumps.

Claims

1. A distributed bonding and packaging method for improving the yield of wafer stacking, characterized in that: The steps include the following: S1. Strip the Fail Die (3) on the first wafer (1). S2. Provide the second wafer (2) and Good Die (4), and hybrid bond the Good Die (4) to the second wafer (2). S3. Hybrid bond the first wafer (1) and the second wafer (2), with the Good Die (4) located within the area of the stripped Fail Die (3) on the first wafer (1). S4. Thinning the back surface of the first wafer (1) until the Good Die (4) area is exposed. S5. Etch the silicon layer (1-1) of the first wafer (1) to expose the TSV structure (1-2) inside the first wafer (1). S6. After cleaning, perform filling through the PECVD process. S7. Clean through CMP polishing to expose Cu (6).

2. The distributed bonding and packaging method for improving the yield of wafer stacking according to claim 1, wherein: The specific method of step S1 includes the following steps: S11. Excavate the scribe lane outside the Fail Die (3) to a specified depth; S12. Attach a film layer to the front surface of the first wafer (1); S13. Use the infrared laser penetration characteristic on the back surface of the first wafer (1) to focus to a specified depth for lateral surface ablation to form a modified layer in the back Fail Die (3) area; S14. Use ultrasonic vibration to rupture the modified layer; S15. Tear off the film layer to strip the Fail Die (3).

3. The distributed bonding and packaging method for improving the yield of wafer stacking according to claim 1, characterized in that: In step S13, the specified depth of infrared laser focusing is from the back surface of the first wafer (1) to the bottom of the groove excavated in step S11.

4. A distributed bonding and packaging method for improving the yield of wafer stacking according to claim 1, characterized in that: In step S13, during laser ablation, select the infrared band of 1000 - 1500um, control the spot size at 1 - 3um, the energy at 1 - 3W, and the step overlap at 50% - 80% for X-Y direction scanning.

5. A distributed bonding and packaging method for improving the yield of wafer stacking, characterized in that: The depth excavated in step S11 is greater than the thickness of the filled Die in step S6.

6. A distributed bonding and packaging method for improving the yield of wafer stacking, as described in claim 1, wherein: The depth excavated in step S11 is 50 - 100um.

7. A distributed bonding and packaging method for improving the yield of wafer stacking according to claim 1, characterized in that: In step S2, the bonding position of the Good Die (4) matches the position of the stripped Fail Die (3) area on the first wafer (1).

8. A distributed bonding and packaging method for improving the yield of wafer stacking according to claim 1, characterized in that: In step S6, use TEOS liquid source for CVD growth.

9. A distributed bonding and packaging method for improving the yield of wafer stacking according to claim 1, characterized in that: It further includes the following steps: S8. Repeat steps S1 to S7 to complete multi-layer stacking. S9. Perform BVR and bump manufacturing processes on the bottom wafer. S10. Dicing to form a particle stacking structure.

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