A miniaturized and high-precision power supply circuit

Abstract

The present invention provides a control signal generation circuit, an integrated circuit control chip, and a miniaturized, high-precision power supply circuit. The control signal generation circuit includes an interconnected phase control circuit and a signal output circuit, both of which are connected to a power supply voltage VDD and ground. The phase control circuit outputs a logic signal SP, and the signal output circuit receives a first input signal S1. The signal output circuit includes multiple interconnected signal output modules, one of which outputs a first control signal SO1 based on the first input signal S1, and the other signal output modules output control signals with the same frequency but different phases as the first control signal SO1 based on the logic signal SP and the first input signal S1. The signal output circuit of the present invention can simultaneously output multiple control signals with the same frequency but different phases, reducing circuit size and improving control precision.

Description

Technical Field

[0001] The present invention relates to the technical field of battery power supply circuits, and in particular to a miniaturized and high-precision power supply circuit. Background Art

[0002] The battery-powered circuit in the prior art generally includes an integrated circuit control chip and an external power circuit, wherein the integrated circuit control chip contains multiple control circuits. In order to achieve parallel processing of some control circuits, these control circuits usually need to receive control signals with the same frequency but different phases respectively. The prior art generally sets up multiple independent control signal generation circuits in the integrated circuit control chip to generate multiple control signals with the same frequency but different phases respectively. However, this method not only increases the overall volume of the circuit, but also because each control signal generation circuit operates independently, the frequency and phase of each output control signal have a large deviation compared to the design value, thereby reducing the control accuracy of the integrated circuit control chip and the output accuracy of the battery-powered circuit. Summary of the Invention

[0003] The purpose of the present invention is to solve the problems in existing battery-powered circuits, such as the need to set up multiple independent control signal generation circuits, which leads to an increase in circuit volume and large errors in control signal frequency and phase, thereby affecting the control accuracy of the integrated circuit control chip and the output accuracy of the battery-powered circuit.

[0004] According to a first aspect of the present invention, a control signal generating circuit is provided, comprising a phase control circuit and a signal output circuit connected to each other, wherein the phase control circuit and the signal output circuit are both connected to a power supply voltage VDD and to ground, the phase control circuit outputs a logic signal SP, and the signal output circuit is connected to a first input signal S1;

[0005] The signal output circuit includes multiple signal output modules connected to each other, one of the multiple signal output modules outputs a first control signal SO1 based on the first input signal S1, and the other signal output modules output control signals with the same frequency but different phases as the first control signal SO1 based on the logic signal SP and the first input signal S1.

[0006] In a possible implementation, the control signals output by other signal output modules have the same frequency but different phases.

[0007] In a possible implementation, the signal output circuit includes a first signal output module;

[0008] In the first signal output module, the power supply voltage VDD is connected to ground in sequence through the first switch tube M1, the second switch tube M2, and the first controllable current source G1, and the first input signal S1 is connected to the control terminals of the first switch tube M1 and the second switch tube M2. The power supply voltage VDD is also connected to ground in sequence through the first switch tube M1 and the first capacitor C1. A first node A between the first switch tube M1 and the second switch tube M2 is connected to the input terminal of the first inverter A1, and the first inverter A1 outputs the first control signal SO1. The positive control terminal of the first controllable current source G1 is connected to the phase control circuit, and the negative control terminal of the first controllable current source G1 is grounded.

[0009] In a possible implementation, the first signal output module further includes:

[0010] The second inverter A2 has an input terminal connected to the output terminal of the first inverter A1 and an output terminal that outputs a second control signal SO2.

[0011] In a possible implementation, the signal output circuit further includes a second signal output module, and the second signal output module includes a first logic unit;

[0012] In the second signal output module, the power supply voltage VDD is connected to ground in sequence through the third switch M3, the fourth switch M4, and the second controllable current source G2. The first input signal S1 is connected to the control terminals of the third switch M3 and the fourth switch M4 through the third inverter A3. The positive control terminal of the second controllable current source G2 is connected to the positive control terminal of the first controllable current source G1, and the negative control terminal of the second controllable current source G2 is connected to ground. The power supply voltage VDD is also connected to ground in sequence through the third switch M3 and the second capacitor C2. The first terminal of the first logic unit is connected to the current output terminal of the third switch M3, and the second terminal of the first logic unit is connected to the logic signal SP. The first logic unit outputs a third control signal SO3 based on the logic signal SP and the first input signal S1.

[0013] In one possible implementation, the first logic unit includes:

[0014] a fourth inverter A4, whose input terminal serves as a first terminal of the first logic unit;

[0015] a first OR gate A5, wherein a first input terminal of the first OR gate A5 is connected to an output terminal of the fourth inverter A4;

[0016] a first NAND gate A6, wherein a first input terminal of the first NAND gate A6 is connected to the second input terminal of the first OR gate A5 and serves as a second terminal of the first logic unit, and a second input terminal of the first NAND gate A6 is connected to a third node C between the fourth inverter A4 and the first OR gate A5;

[0017] A first AND gate A7, wherein a first input terminal of the first AND gate A7 is connected to the output terminal of the first OR gate A5, a second input terminal of the first AND gate A7 is connected to the output terminal of the first NAND gate A6, and an output terminal of the first AND gate A7 outputs a third control signal SO3.

[0018] In a possible implementation, the signal output circuit further includes a third signal output module, and the third signal output module includes a second logic unit;

[0019] In the third signal output module, the power supply voltage VDD is grounded in sequence through the fifth switch M5, the sixth switch M6, and the third controllable current source G3. The positive control terminal of the third controllable current source G3 is connected to the positive control terminal of the second controllable current source G2, and the negative control terminal of the third controllable current source G3 is grounded. The first input signal S1 is connected to a fourth node D between the control terminals of the fifth switch M5 and the sixth switch M6 via a third inverter A3. The first terminal of the second logic unit is connected to the current output terminal of the fifth switch M5, and the second terminal of the second logic unit is connected to the logic signal SP. The second logic unit outputs a fourth control signal SO4 based on the logic signal SP and the first input signal S1.

[0020] In one possible implementation, the second logic unit includes:

[0021] a fifth inverter A8, whose input terminal serves as a first terminal of the second logic unit;

[0022] a second OR gate A9, wherein a first input terminal of the second OR gate A9 is connected to the output terminal of the fifth inverter A8;

[0023] a sixth inverter A10, having an input end serving as the second end of the second logic unit and an output end connected to the second input end of the second OR gate A9;

[0024] a second NAND gate A11, wherein a first input terminal of the second NAND gate A11 is connected to the output terminal of the sixth inverter A10, and a second input terminal of the second NAND gate A11 is connected to a fifth node E between the fifth inverter A8 and the second OR gate A9;

[0025] A second AND gate A12, wherein a first input terminal of the second AND gate A12 is connected to the output terminal of the second OR gate A9, a second input terminal of the second AND gate A12 is connected to the output terminal of the second NAND gate A11, and an output terminal of the second AND gate A12 outputs a fourth control signal SO4.

[0026] In one possible implementation, in the phase control circuit, the power supply voltage VDD is grounded sequentially through the fourth controllable current source G4 and the seventh switch tube M7, the power supply voltage VDD is further grounded sequentially through the first resistor R1, the eighth switch tube M8, the ninth switch tube M9, and the second resistor R2, the power supply voltage VDD is further grounded sequentially through the fifth controllable current source G5 and the second resistor R2, and the power supply voltage VDD is further grounded sequentially through the sixth controllable current source G6 and the seventh controllable current source G7; a sixth node F between the eighth switch tube M8 and the ninth switch tube M9 is connected to the second input signal S2, the control end of the eighth switch tube M8 is connected to the control end of the ninth switch tube M9, and both are connected to the first controllable current source G5 and the second resistor R2. A seventh node G is connected between the fourth controllable current source G4 and the seventh switch tube M7; the positive control terminals of the fifth controllable current source G5 and the sixth controllable current source G6 are both connected to the power supply voltage VDD, the negative control terminal of the fifth controllable current source G5 is connected to the negative control terminal of the sixth controllable current source G6, and both are connected to the current input terminal of the eighth switch tube M8; an eighth node H between the sixth controllable current source G6 and the seventh controllable current source G7 outputs a logic signal SP; the negative control terminal of the seventh controllable current source G7 is grounded, the positive control terminal of the seventh controllable current source G7 is connected to the positive control terminal of the first controllable current source G1, and both are connected to the current output terminal of the ninth switch tube M9.

[0027] In one possible implementation, in the phase control circuit, the power supply voltage VDD is further connected to ground via the third resistor R3 and the first current source B1 in sequence, the power supply voltage VDD is further connected to ground via the eighth controllable current source G8, the tenth switch tube M10, and the fourth resistor R4 in sequence, and the power supply voltage VDD is further connected to ground via the eighth controllable current source G8, the eleventh switch tube M11, and the ninth controllable current source G9 in sequence; the control terminal of the eleventh switch tube M11 is grounded via the first voltage source E1; and the control terminal of the seventh switch tube M7 is connected to the eleventh switch tube M11. 1; the positive control terminal of the ninth controllable current source G9 is connected to the current output terminal of the tenth switch tube M10, and the negative control terminal of the ninth controllable current source G9 is grounded; the positive control terminals of the eighth controllable current source G8 and the fourth controllable current source G4 are both connected to the power supply voltage VDD, the negative control terminal of the eighth controllable current source G8 is connected to the negative control terminal of the fourth controllable current source G4, and are both connected between the third resistor R3 and the first current source B1; the control terminal of the tenth switch tube M10 is connected to the second input signal S2.

[0028] In a possible implementation, the current coefficient of the seventh controllable current source G7 is less than 1;

[0029] The current coefficients of the first controllable current source G1 , the second controllable current source G2 , the third controllable current source G3 , the fifth controllable current source G5 , the sixth controllable current source G6 and the ninth controllable current source G9 are all equal to 1.

[0030] In a possible implementation, the second input signal S2 includes a first sub-signal S21 and a second sub-signal S22 . The voltage of the first sub-signal S21 is lower than the first voltage V1 , and the voltage of the second sub-signal S22 is higher than the first voltage V1 .

[0031] According to a second aspect of the present invention, an integrated circuit control chip is provided, comprising a control signal generating circuit as described above and a plurality of control circuits, wherein the control signal generating circuit is connected to each control circuit and is used to output control signals with the same frequency but different phases to the control circuits.

[0032] According to a third aspect of the present invention, there is provided a miniaturized and high-precision power supply circuit, comprising the integrated circuit control chip as described above and an external power circuit.

[0033] According to the present invention, through the coordinated operation of the phase control circuit and the signal output circuit, one of the multiple signal output modules generates a first control signal SO1 based solely on the first input signal S1. The other signal output modules, in turn, combine the first input signal S1 with the logic signal SP to output control signals with the same frequency but different phases as the first control signal SO1. Compared to prior art solutions that employ multiple independent control signal generation circuits, the present invention utilizes only one control signal generation circuit, capable of simultaneously outputting multiple control signals with the same frequency but different phases. This reduces circuit size and improves control precision.

[0034] Furthermore, the control signal generation circuit of the present invention can simultaneously output multiple control signals with the same frequency but different phases, and can adjust the phase difference by adjusting the magnitude of the external control current IL. At the same time, regardless of which sub-signal input circuit the second input signal S2 is fed into, multiple control signals with the same frequency but different phases can be simultaneously output. Therefore, the second input signal S2 can also be used to multiplex with other control signals. In addition, depending on the actual needs of the chip, the control signal generation circuit can flexibly configure different numbers of signal output modules, thereby reducing circuit size, improving applicability, and ensuring that the frequency and phase of the control signal meet design requirements.

[0035] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 shows a topological structure diagram of a control signal generating circuit according to an embodiment of the present invention;

[0037] Figure 2 shows a topological structure diagram of a control signal generating circuit according to another embodiment of the present invention;

[0038] Figure 3 shows a waveform diagram of a first input signal S1 according to one embodiment of the present invention;

[0039] Figure 4 shows a waveform comparison diagram of the first control signal SO1 and the first input signal S1 according to one embodiment of the present invention;

[0040] Figure 5 shows a topological structure diagram of a control signal generating circuit according to yet another embodiment of the present application;

[0041] Figure 6 shows a waveform comparison diagram of the second control signal SO2 and the first input signal S1 according to one embodiment of the present invention;

[0042] Figure 7 shows a topological structure diagram of a control signal generating circuit according to yet another embodiment of the present invention;

[0043] Figure 8 FIG2 shows a waveform comparison diagram of the third control signal SO3 and the third node C and the first input signal S1 according to an embodiment of the present invention;

[0044] Figure 9 1 shows a waveform comparison diagram of the third control signal SO3 and the third node C and the first input signal S1 according to another embodiment of the present invention;

[0045] Figure 10 1 shows a waveform comparison diagram of the fourth control signal SO4 and the fifth node E and the first input signal S1 according to an embodiment of the present invention;

[0046] Figure 11 1 shows a waveform comparison diagram of the fourth control signal SO4 and the fifth node E and the first input signal S1 according to another embodiment of the present invention;

[0047] Figure 12 A structural block diagram of an integrated circuit control chip according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0049] As used herein, the terms "comprise," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0050] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0051] Figure 1 FIG. 1 shows a topological structure diagram of a control signal generating circuit according to an embodiment of the present invention. Figure 1 As shown, the control signal generation circuit includes a phase control circuit 100 and a signal output circuit 200, which are both connected to a power supply voltage VDD and grounded. The phase control circuit 100 outputs a logic signal SP, and the signal output circuit 200 receives a first input signal S1. The signal output circuit 200 includes multiple interconnected signal output modules. One of the multiple signal output modules outputs a first control signal SO1 based on the first input signal S1, and the other signal output modules output control signals with the same frequency but different phases as the first control signal SO1 based on the logic signal SP and the first input signal S1.

[0052] According to the solution of the embodiment of the present invention, through the coordinated operation of the phase control circuit 100 and the signal output circuit 200, one of the multiple signal output modules generates a first control signal SO1 based solely on the first input signal S1. The other signal output modules, in combination with the first input signal S1 and the logic signal SP, output control signals having the same frequency but different phases as the first control signal SO1. Compared to the prior art solution that uses multiple independent control signal generation circuits, the solution of the present invention only provides a single control signal generation circuit, capable of simultaneously outputting multiple control signals having the same frequency but different phases, thereby reducing circuit size and improving control precision.

[0053] In one embodiment, the number of other signal output modules may be, for example, two, three or more. Figure 1 In the illustrated embodiment, the plurality of signal output modules include a first signal output module 210, a second signal output module 220, ..., and an Nth signal output module 2N0, where N is greater than or equal to 2. The first signal output module 210 outputs a first control signal SO1. The other signal output modules output control signals having the same frequency as the first control signal SO1 but a different phase.

[0054] In one embodiment, the control signals output by other signal output modules have the same frequency but different phases. In this embodiment, other modules can output control signals with the same frequency but different phases based on the logic signal SP and the first input signal S1 according to the requirements of the control circuit.

[0055] Figure 2 FIG. 2 shows a topological structure diagram of a control signal generating circuit according to another embodiment of the present invention. Figure 2 As shown, in the phase control circuit 100, the power supply voltage VDD is connected to ground sequentially through the fourth controllable current source G4 and the seventh switch M7. The power supply voltage VDD is also connected to ground sequentially through the first resistor R1, the eighth switch M8, the ninth switch M9, and the second resistor R2. The power supply voltage VDD is also connected to ground sequentially through the fifth controllable current source G5 and the second resistor R2. The power supply voltage VDD is also connected to ground sequentially through the sixth controllable current source G6 and the seventh controllable current source G7. A sixth node F between the eighth switch M8 and the ninth switch M9 is connected to the second input signal S2. The control terminal of the eighth switch M8 is connected to the control terminal of the ninth switch M9, and both are connected to the seventh node G between the fourth controllable current source G4 and the seventh switch M7. The positive control terminals of the fifth controllable current source G5 and the sixth controllable current source G6 are both connected to the power supply voltage VDD. The negative control terminal of the fifth controllable current source G5 is connected to the negative control terminal of the sixth controllable current source G6, and both are connected to the current input terminal of the eighth switch M8. An eighth node H between the sixth controllable current source G6 and the seventh controllable current source G7 outputs a logic signal SP. A negative control terminal of the seventh controllable current source G7 is grounded, and a positive control terminal of the seventh controllable current source G7 is connected to the positive control terminal of the first controllable current source G1, and both are connected to the current output terminal of the ninth switch tube M9.

[0056] In one embodiment, in the phase control circuit 100, the power supply voltage VDD is further connected to ground sequentially through the third resistor R3 and the first current source B1. The power supply voltage VDD is further connected to ground sequentially through the eighth controllable current source G8, the tenth switch M10, and the fourth resistor R4. The power supply voltage VDD is further connected to ground sequentially through the eighth controllable current source G8, the eleventh switch M11, and the ninth controllable current source G9. The control terminal of the eleventh switch M11 is grounded via the first voltage source E1. The control terminal of the seventh switch M7 is connected to the current output terminal of the eleventh switch M11. The positive control terminal of the ninth controllable current source G9 is connected to the current output terminal of the tenth switch M10. The negative control terminal of the ninth controllable current source G9 is grounded. The positive control terminals of the eighth controllable current source G8 and the fourth controllable current source G4 are both connected to the power supply voltage VDD, the negative control terminal of the eighth controllable current source G8 is connected to the negative control terminal of the fourth controllable current source G4, and are both connected between the third resistor R3 and the first current source B1, and the control terminal of the tenth switch tube M10 is connected to the second input signal S2.

[0057] In one embodiment, the current coefficient of the seventh controllable current source G7 is less than 1, and the current coefficients of the fifth controllable current source G5 , the sixth controllable current source G6 , and the ninth controllable current source G9 are all equal to 1.

[0058] In some embodiments, the second input signal S2 is divided into a first sub-signal S21 and a second sub-signal S22. When the voltage of the first sub-signal S21 is lower than the first voltage V1 generated by the first voltage source E1, the input end of the second input signal S2 extracts a control current IL from the sixth node F. When the voltage of the second sub-signal S22 is higher than the first voltage V1 generated by the first voltage source E1, the input end of the second input signal S2 injects a control current IL into the sixth node F.

[0059] In the above embodiment, the operating principle of the phase control circuit 100 is as follows: After the phase control circuit 100 is powered on, when the first sub-signal S21 of the second input signal S2 is input into the circuit, the first current source B1 generates a first current, and the first voltage source E1 generates a first voltage V1. The first current flows through the third resistor R3, generating a voltage drop across it, causing the eighth controllable current source G8 and the fourth controllable current source G4 to generate current. At this time, the eighth controllable current source G8 raises the voltage at the current input terminals of the tenth and eleventh switching transistors M10 and M11, turning them on. At this time, current flows through the fourth resistor R4, generating a voltage drop across it, causing current to flow through the ninth controllable current source G9. Since the current coefficient of the ninth controllable current source G9 is equal to 1, the current flowing through the ninth controllable current source G9 is equal to the current flowing through the fourth resistor R4. Furthermore, because the voltage of the first sub-signal S21 is lower than the first voltage V1, the current flowing through the tenth switching transistor M10 is greater than the current flowing through the eleventh switching transistor M11. The current flowing through the tenth switch M10 is equal to the current flowing through the fourth resistor R4 and the ninth controllable current source G9. Therefore, the current flowing through the ninth controllable current source G9 is greater than the current flowing through the eleventh switch M11. This lowers the voltage at the control terminal of the seventh switch M7, turning it off. Consequently, the voltage at the seventh node G is raised by the fourth controllable current source G4. At this point, the eighth switch M8 turns on, and the ninth switch M9 turns off. Furthermore, after the first sub-signal S21 is input into the circuit, the second input signal terminal draws control current IL from the sixth node F. Furthermore, since the current coefficients of the fifth and sixth controllable current sources G5 and G6 are equal to 1, the current flowing through the first resistor R1 is equal to the current generated by the fifth and sixth controllable current sources G5 and G6, i.e., equal to control current IL. At this time, the current generated by the fifth controllable current source G5 flows into the second resistor R2. Simultaneously, because the current coefficient of the seventh controllable current source G7 is less than 1, the current generated by the seventh controllable current source G7 is less than the current flowing through the second resistor R2, that is, less than the control current IL. From the above analysis, it can be seen that the current generated by the seventh controllable current source G7 is less than the current generated by the sixth controllable current source G6. Therefore, the logic signal SP is at a high level.

[0060] When the second sub-signal S22 of the second input signal S2 is input into the circuit, because its voltage is higher than the first voltage V1, the current flowing through the tenth switch M10 is less than the current flowing through the eleventh switch M11. The current flowing through the tenth switch M10 is equal to the current flowing through the fourth resistor R4, and therefore equal to the current flowing through the ninth controllable current source G9. Therefore, the current flowing through the ninth controllable current source G9 is less than the current flowing through the eleventh switch M11. Therefore, the voltage at the control terminal of the seventh switch M7 is pulled high, turning on the seventh switch M7. This pulls down the voltage at the seventh node G, turning off the eighth switch M8 and turning on the ninth switch M9. Furthermore, after the second sub-signal S22 is input into the circuit, the second input signal terminal injects a control current IL into the sixth node F. Therefore, this control current IL flows through the ninth switch M9 into the second resistor R2, generating a pull-down current in the seventh controllable current source G7. At the same time, since the eighth switch tube M8 is turned off, no current flows through the first resistor R1 , that is, no current is generated in the sixth controllable current source G6 , so that the logic signal SP is at a low level.

[0061] According to the working principle of the phase control circuit 100 , when the first sub-signal S21 of the second input signal S2 is input into the circuit, the logic signal SP is at a high level; and when the second sub-signal S22 of the second input signal S2 is input into the circuit, the logic signal SP is at a low level.

[0062] In one embodiment, see Figure 2 The signal output circuit 200 includes a first signal output module 210. In the first signal output module 210, the power supply voltage VDD is connected to ground sequentially through the first switch M1, the second switch M2, and the first controllable current source G1. A first input signal S1 is connected to the control terminals of the first and second switch M1 and M2. The power supply voltage VDD is also connected to ground sequentially through the first switch M1 and the first capacitor C1. A first node A between the first and second switch M1 and M2 is connected to the input terminal of a first inverter A1, which outputs a first control signal SO1. The positive control terminal of the first controllable current source G1 is connected to the phase control circuit, and the negative control terminal of the first controllable current source G1 is grounded.

[0063] In one embodiment, the current coefficient of the first controllable current source G1 is equal to 1.

[0064] In one embodiment, the first input signal S1 is a periodic signal. Figure 3 A waveform diagram of the first input signal S1 is shown.

[0065] In the above embodiment, the working principle of the first signal output module 210 is as follows: the first switch tube M1 and the second switch tube M2 are both connected to the periodic first input signal S1. When the first input signal S1 is at a low level, the first switch tube M1 is turned on and the second switch tube M2 is turned off. At this time, the terminal voltage of the first capacitor C1 is instantly pulled up to the power supply voltage VDD, and the first control signal SO1 instantly outputs a low level. When the first input signal S1 switches from a low level to a high level, the first switch tube M1 is turned off and the second switch tube M2 is turned on. At this time, the first capacitor C1 is discharged through the second switch tube M2 and the first controllable current source G1. From the analysis of the working principle of the above-mentioned phase control circuit 100, it can be seen that the current flowing through the second resistor R2 is equal to the control current IL, and since the current coefficient of the first controllable current source G1 is equal to 1, the current flowing through the first controllable current source G is equal to the current flowing through the second resistor R2, that is, equal to the control current IL. Therefore, at this time, the discharge current of the first capacitor C1 is the control current IL. According to the capacitor charging and discharging formula It can be seen that the time it takes for the terminal voltage of the first capacitor C1 to discharge from the power supply voltage VDD to the flip threshold voltage VT of the first inverter A1 is That is, when the first input signal S1 switches from a low level to a high level, after time t1, the terminal voltage of the first capacitor C1 drops below the flip threshold voltage VT of the first inverter A1, and the first inverter A1 outputs a high level. At this time, the first control signal SO1 switches from a low level to a high level. When the first input signal S1 switches from a high level back to a low level, the first switch M1 turns on again and the second switch M2 turns off. The terminal voltage of the first capacitor C1 is instantly pulled up to the power supply voltage VDD again, and the first control signal SO1 is now instantaneously output at a low level again.

[0066] From the above analysis, it can be seen that the waveform comparison between the first control signal SO1 and the first input signal S1 is as follows: Figure 4 See Figure 4 The first control signal SO1 output by the first signal output module 210 has the same frequency as the first input signal S1, but has a rising edge phase lag, and the lag phase time is Therefore, at this time, by adjusting the magnitude of the external control current IL, the lag phase of the first control signal SO1 output by the first signal output module 210 can be adjusted.

[0067] Figure 5 FIG1 shows a topological structure diagram of a control signal generating circuit according to another embodiment of the present application. Figure 5The first signal output module 210 further includes a second inverter A2, the input end of which is connected to the output end of the first inverter A1, and the output end of the second inverter A2 outputs the second control signal SO2. Therefore, the second control signal SO2 output by the second inverter A2 is inversely proportional to the first control signal SO1. From the above analysis, it can be seen that the waveform comparison between the second control signal SO2 and the first input signal S1 is as follows: Figure 6 See Figure 6 The second control signal SO2 output by the first signal output module 210 is a control signal having the same frequency as the first input signal S1 and an opposite phase, and the phase of the falling edge lags behind the phase of the rising edge of the first input signal S1. The delayed phase time Therefore, at this time, by adjusting the magnitude of the external control current IL, the lag phase of the second control signal SO2 output by the first signal output module 210 can be adjusted.

[0068] In one embodiment, see Figure 2 or Figure 5 The signal output circuit 200 also includes a second signal output module 220, which includes a first logic unit. In the second signal output module 220, the power supply voltage VDD is connected to ground sequentially through the third switch M3, the fourth switch M4, and the second controllable current source G2. The first input signal S1 is connected to the control terminals of the third switch M3 and the fourth switch M4 via the third inverter A3. The connection node between the third inverter A3 and the control terminals of the third switch M3 and the fourth switch M4 is a second node B. The positive control terminal of the second controllable current source G2 is connected to the positive control terminal of the first controllable current source G1, and the negative control terminal of the second controllable current source G2 is grounded. The power supply voltage VDD is also connected to ground sequentially through the third switch M3 and the second capacitor C2. The first terminal of the first logic unit is connected to the current output terminal of the third switch M3, and the second terminal of the first logic unit is connected to the logic signal SP. The first logic unit outputs a third control signal SO3 based on the logic signal SP and the first input signal S1.

[0069] In one embodiment, the current coefficient of the second controllable current source G2 is equal to 1.

[0070] Figure 7 FIG1 shows a topological structure diagram of a control signal generating circuit according to another embodiment of the present invention. Figure 7The first logic unit includes a fourth inverter A4, a first OR gate A5, a first NAND gate A6, and a first AND gate A7. The input of the fourth inverter A4 serves as the first end of the first logic unit. The first input of the first OR gate A5 is connected to the output of the fourth inverter A4. The first input of the first NAND gate A6 is connected to the second input of the first OR gate A5 and serves as the second end of the first logic unit. The second input of the first NAND gate A6 is connected to a third node C between the fourth inverter A4 and the first OR gate A5. The first input of the first AND gate A7 is connected to the output of the first OR gate A5, the second input of the first AND gate A7 is connected to the output of the first NAND gate A6, and the output of the first AND gate A7 outputs the third control signal SO3.

[0071] In this embodiment, the operating principle of the second signal output module 220 is as follows: the second node B is connected to the first input signal S1 through the third inverter A3, and the signal at the second node B is in phase with the first input signal S1. Therefore, when the first input signal S1 is high, the second node B is low. At this time, the third switch M3 is turned on and the fourth switch M4 is turned off. The terminal voltage of the second capacitor C2 is instantly pulled up to the power supply voltage VDD, and the voltage of the third node C is instantly pulled down to a low level. When the first input signal S1 switches from a high level to a low level, the second node B switches from a low level to a high level. At this time, the third switch M3 is turned off and the fourth switch M4 is turned on. The second capacitor C2 is discharged through the fourth switch M4 and the second controllable current source G2. Based on the operating principle of the phase control circuit 100 described above, it can be seen that the current flowing through the second resistor R2 is equal to the control current IL. Since the current coefficient of the second controllable current source G2 is equal to 1, the current flowing through the second controllable current source G2 is also equal to the control current IL. Therefore, at this time, the discharge current of the second capacitor C2 is also the control current IL. According to the capacitor charging and discharging formula It can be seen that the time required for the terminal voltage of the second capacitor C2 to discharge from the power supply voltage VDD to the flip threshold voltage VT of the fourth inverter A4 is That is, when the first input signal S1 switches from a high level to a low level, after time t2, the voltage across the second capacitor C2 drops below the flip threshold voltage VT of the fourth inverter A4, causing the fourth inverter A4 to output a high level. At this point, the voltage at the third node C switches from a low level to a high level. When the first input signal S1 switches from a low level back to a high level, the third switch M3 turns on again, while the fourth switch M4 turns off. The voltage across the second capacitor C2 is instantly pulled up to the power supply voltage VDD again, causing the voltage at the third node C to instantly switch to a low level again.

[0072] At the same time, the second signal output module 220 receives the logic signal SP via the first OR gate A5 and the first NAND gate A6. Based on the operating principle of the phase control module described above, when the first sub-signal S21 of the second input signal S2 is input into the circuit, the logic signal SP is at a high level. At this point, the signal level at the first input of the first OR gate A5 is at the level of the third node C, and the signal level at the second input of the first OR gate A5 is at the level of the logic signal SP. Since the logic signal SP is at a high level, the first OR gate A5 necessarily outputs a high-level signal. The signal level at the third input of the first NAND gate A6 is at the level of the logic signal SP, and the signal level at the fourth input of the first NAND gate A6 is at the level of the third node C. Therefore, the output signal of the first NAND gate A6 is in phase with the signal at the third node C. Furthermore, since the output signal of the first OR gate A5 is output to the fifth input terminal of the first AND gate A7, the output signal of the first NAND gate A6 is output to the sixth input terminal of the first AND gate A7, and the signal output by the first OR gate A5 is a high-level signal, the output signal of the first AND gate A7 is in phase with the output signal of the first NAND gate A6, that is, in phase opposite to the signal at the third node C. In other words, when the first sub-signal S21 of the second input signal S2 is input into the circuit, the third control signal SO3 output by the second signal output module 220 is in phase opposite to the signal at the third node C.

[0073] According to the above analysis, when the first sub-signal S21 of the second input signal S2 is input into the circuit, the waveform comparison between the third control signal SO3 and the third node C and the first input signal S1 is as follows: Figure 8 See Figure 8 The third control signal SO3 output by the second signal output module 220 is a control signal with the same frequency as the first input signal S1, but with a falling edge phase lag, and the lag phase time is Therefore, at this time, by adjusting the magnitude of the external control current IL, the lag phase of the third control signal SO3 output by the second signal output module 220 can be adjusted.

[0074] When the second sub-signal S22 of the second input signal S2 is input into the circuit, the logic signal SP is at a low level. At this point, the first NAND gate A6 necessarily outputs a high-level signal, and the output signal of the first OR gate A5 is in phase with the signal at the third node C. The first OR gate A5 outputs a signal to the fifth input terminal of the first AND gate A7, and the first NAND gate A6 outputs a signal to the sixth input terminal of the first AND gate A7. The signal of the first NAND gate A6 is a high-level signal. Therefore, the output signal of the first AND gate A7 is in phase with the output signal of the first OR gate A5, that is, in phase with the signal at the third node C. That is, when the second sub-signal S22 of the second input signal S2 is input into the circuit, the third control signal SO3 output by the second signal output module 220 is in phase with the signal at the third node C.

[0075] According to the above analysis, when the second sub-signal S22 of the second input signal S2 is input into the circuit, the waveform comparison of the third control signal SO3 and the third node C with the first input signal S1 is as follows: Figure 9 See Figure 9 The third control signal SO3 output by the second signal output module 220 has the same frequency as the first input signal S1, but has an opposite phase, and the phase of the rising edge lags behind the phase of the falling edge of the first input signal S1. The lag phase time is Therefore, at this time, by adjusting the magnitude of the external control current IL, the lag phase of the third control signal SO3 output by the second signal output module 220 can be adjusted.

[0076] In one embodiment, see Figure 2 or Figure 5 The signal output circuit 200 also includes a third signal output module 230, which includes a second logic unit. In the third signal output module 230, the power supply voltage VDD is connected to ground sequentially through the fifth switch M5, the sixth switch M6, and the third controllable current source G3. The positive control terminal of the third controllable current source G3 is connected to the positive control terminal of the second controllable current source G2, and the negative control terminal of the third controllable current source G3 is grounded. The first input signal S1 is connected to the control terminals of the fifth switch M5 and the sixth switch M6 via a third inverter A3. The connection node between the third inverter A3 and the control terminals of the fifth switch M5 and the sixth switch M6 is a fourth node D. The first terminal of the second logic unit is connected to the current output terminal of the fifth switch M5, and the second terminal of the second logic unit is connected to the logic signal SP. The second logic unit outputs a fourth control signal SO4 based on the logic signal SP and the first input signal S1.

[0077] In one embodiment, the current coefficient of the third controllable current source G3 is equal to 1.

[0078] In one embodiment, see Figure 7The second logic unit includes a fifth inverter A8, a second OR gate A9, a sixth inverter A10, a second NAND gate A11, and a second AND gate A12. The input of the fifth inverter A8 serves as the first terminal of the second logic unit. The first input of the second OR gate A9 is connected to the output of the fifth inverter A8. The input of the sixth inverter A10 serves as the second terminal of the second logic unit, and the output is connected to the second input of the second OR gate A9. The first input of the second NAND gate A11 is connected to the output of the sixth inverter A10, and the second input of the second NAND gate A11 is connected to a fifth node E between the fifth inverter A8 and the second OR gate A9. The first input of the second AND gate A12 is connected to the output of the second OR gate A9, the second input of the second AND gate A12 is connected to the output of the second NAND gate A11, and the output of the second AND gate A12 outputs the fourth control signal SO4.

[0079] In this embodiment, the operating principle of the third signal output module 230 is as follows: the fourth node D is connected to the second node B, and the signal at the fourth node D is in phase with the signal at the second node B, i.e., in phase opposition with the first input signal S1. Therefore, when the first input signal S1 is high, the fourth node D is low. At this time, the fifth switch M5 is turned on, the sixth switch M6 is turned off, and the terminal voltage of the third capacitor C3 is instantly pulled up to the power supply voltage VDD, and the voltage of the fifth node E is instantly pulled down to a low level. When the first input signal S1 switches from a high level to a low level, the fourth node D switches from a low level to a high level. At this time, the fifth switch M5 is turned off, the sixth switch M6 is turned on, and the third capacitor C3 is discharged through the sixth switch M6 and the third controllable current source G3. Based on the operating principle of the phase control circuit 100 described above, it can be seen that the current flowing through the second resistor R2 is equal to the control current IL. Since the current coefficient of the third controllable current source G3 is equal to 1, the current flowing through the third controllable current source G3 is also equal to the control current IL. Therefore, at this time, the discharge current of the third capacitor C3 is also the control current IL. According to the capacitor charge and discharge formula It can be seen that the time it takes for the terminal voltage of the third capacitor C3 to discharge from the power supply voltage VDD to the flip threshold voltage VT of the fifth inverter A8 is That is, when the first input signal S1 switches from a high level to a low level, after time t3, the voltage across the third capacitor C3 drops below the flip threshold voltage VT of the fifth inverter A8, causing the fifth inverter A8 to output a high level. At this point, the voltage at the fifth node E switches from a low level to a high level. When the first input signal S1 switches from a low level back to a high level, the fifth switch M5 turns on again, and the sixth switch M6 turns off. The voltage across the third capacitor C3 is then instantly pulled up to the power supply voltage VDD, causing the voltage at the fifth node E to again instantly switch to a low level.

[0080] At the same time, the third signal output module 230 receives the logic signal SP through the sixth inverter A10. Analysis of the operating principle of the phase control module indicates that when the first sub-signal S21 of the second input signal S2 is input into the circuit, the logic signal SP is at a high level. At this point, the signal output by the sixth inverter A10 is at a low level. That is, the signals at the ninth input terminal of the second NAND gate A11 and the eighth input terminal of the second OR gate A9 are at a low level. Therefore, the second NAND gate A11 necessarily outputs a high-level signal. Furthermore, since the signal level at the seventh input terminal of the second OR gate A9 is at the level of the fifth node E, the output signal of the second OR gate A9 is in phase with the signal at the fifth node E. Furthermore, since the output signal of the second OR gate A9 is output to the eleventh input terminal of the second AND gate A12, and the output signal of the second NAND gate A11 is output to the twelfth input terminal of the second AND gate A12, and the signal output by the second NAND gate A11 is a high-level signal, the output signal of the second AND gate A12 is in phase with the output signal of the second OR gate A9, that is, with the signal at the fifth node E. That is, when the first sub-signal S21 of the second input signal S2 is input into the circuit, the fourth control signal SO4 output by the third signal output module 230 is in phase with the signal at the fifth node E.

[0081] According to the above analysis, when the first sub-signal S21 of the second input signal S2 is input into the circuit, the waveform comparison between the fourth control signal SO4 and the fifth node E and the first input signal S1 is as follows: Figure 10 See Figure 10 The fourth control signal SO4 output by the third signal output module 230 is a control signal with the same frequency and opposite phase as the first input signal S1, and the phase of the rising edge lags behind the phase of the falling edge of the first input signal S1. The lag phase time is Therefore, at this time, by adjusting the magnitude of the external control current IL, the lag phase of the fourth control signal SO4 output by the third signal output module 230 can be adjusted.

[0082] When the second sub-signal S22 of the second input signal S2 is input into the circuit, the logic signal SP is at a low level, and the signal output by the sixth inverter A10 is at a high level. At this point, the second OR gate A9 necessarily outputs a high-level signal, and the output signal of the second NAND gate A11 is in phase with the signal at the fifth node E. The second OR gate A9 outputs a signal to the eleventh input terminal of the second AND gate A12, and the second NAND gate A11 outputs a signal to the twelfth input terminal of the second AND gate A12. The output signal of the second OR gate A9 is a high-level signal. Therefore, the output signal of the second AND gate A12 is in phase with the output signal of the second NAND gate A11, i.e., in phase with the signal at the fifth node E. That is, when the second sub-signal S22 of the second input signal S2 is input into the circuit, the fourth control signal SO4 output by the third signal output module 230 is in phase with the signal at the fifth node E.

[0083] According to the above analysis, when the second sub-signal S22 of the second input signal S2 is input into the circuit, the waveform comparison between the fourth control signal SO4 and the fifth node E and the first input signal S1 is as follows: Figure 11 See Figure 11 The fourth control signal SO4 output by the third signal output module 230 is a control signal with the same frequency as the first input signal S1, but with a falling edge phase lag, and the lag phase time is Therefore, at this time, by adjusting the magnitude of the external control current IL, the lag phase of the fourth control signal SO4 output by the third signal output module 230 can be adjusted.

[0084] According to the above embodiment, the control signal generation circuit of the present invention can simultaneously output multiple control signals with the same frequency but different phases, and can adjust the phase difference by adjusting the magnitude of the external control current IL. Furthermore, regardless of which sub-signal input circuit the second input signal S2 is fed into, it can simultaneously output multiple control signals with the same frequency but different phases. Therefore, the second input signal S2 can also be multiplexed with other control signals. Furthermore, depending on the actual needs of the chip, the control signal generation circuit can flexibly configure different numbers of signal output modules, thereby reducing circuit size, improving applicability, and ensuring that the frequency and phase of the control signal meet design requirements.

[0085] Figure 12 FIG1 shows a block diagram of an integrated circuit control chip according to an embodiment of the present invention. Figure 12 The integrated circuit control chip includes the aforementioned control signal generation circuit and multiple control circuits. The control signal generation circuit is connected to each control circuit and is configured to output control signals with the same frequency but different phases to the multiple control circuits. This integrated circuit control chip, with only one control signal generation circuit, can simultaneously control multiple control circuits, thereby reducing the size of the integrated circuit control chip and improving its control accuracy.

[0086] The present invention also provides a miniaturized, high-precision battery-powered circuit, comprising the aforementioned integrated circuit control chip and an external power circuit. The miniaturized, high-precision battery-powered circuit includes the aforementioned integrated circuit control chip, thereby reducing the size of the battery-powered circuit and improving its output precision.

[0087] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A control signal generating circuit, characterized in that: It includes a phase control circuit and a signal output circuit connected to each other, wherein the phase control circuit and the signal output circuit are both connected to the power supply voltage VDD and are both grounded, the phase control circuit outputs a logic signal SP, and the signal output circuit is connected to the first input signal S1; The signal output circuit includes a plurality of signal output modules connected to each other, wherein one of the plurality of signal output modules outputs a first control signal SO1 according to the first input signal S1, and the other signal output modules output control signals having the same frequency but a different phase as the first control signal SO1 according to the logic signal SP and the first input signal S1; The control signals output by other signal output modules have the same frequency but different phases; The signal output circuit includes a first signal output module; In the first signal output module, the power supply voltage VDD is connected to ground in sequence through the first switch tube M1, the second switch tube M2, and the first controllable current source G1, and the first input signal S1 is connected to the control terminals of the first switch tube M1 and the second switch tube M2. The power supply voltage VDD is also connected to ground in sequence through the first switch tube M1 and the first capacitor C1. A first node A between the first switch tube M1 and the second switch tube M2 is connected to the input terminal of the first inverter A1, and the first inverter A1 outputs the first control signal SO1. The positive control terminal of the first controllable current source G1 is connected to the phase control circuit, and the negative control terminal of the first controllable current source G1 is grounded.

2. The control signal generating circuit according to claim 1, wherein: The first signal output module further includes: The second inverter A2 has an input terminal connected to the output terminal of the first inverter A1 and an output terminal that outputs a second control signal SO2.

3. The control signal generating circuit according to claim 2, wherein: The signal output circuit further includes a second signal output module, and the second signal output module includes a first logic unit; In the second signal output module, the power supply voltage VDD is connected to ground in sequence through the third switch M3, the fourth switch M4, and the second controllable current source G2. The first input signal S1 is connected to the control terminals of the third switch M3 and the fourth switch M4 through the third inverter A3. The positive control terminal of the second controllable current source G2 is connected to the positive control terminal of the first controllable current source G1, and the negative control terminal of the second controllable current source G2 is connected to ground. The power supply voltage VDD is also connected to ground in sequence through the third switch M3 and the second capacitor C2. The first terminal of the first logic unit is connected to the current output terminal of the third switch M3, and the second terminal of the first logic unit is connected to the logic signal SP. The first logic unit outputs a third control signal SO3 based on the logic signal SP and the first input signal S1.

4. The control signal generating circuit according to claim 3, wherein: The first logic unit includes: a fourth inverter A4, whose input terminal serves as a first terminal of the first logic unit; a first OR gate A5, wherein a first input terminal of the first OR gate A5 is connected to an output terminal of the fourth inverter A4; a first NAND gate A6, wherein a first input terminal of the first NAND gate A6 is connected to the second input terminal of the first OR gate A5 and serves as a second terminal of the first logic unit, and a second input terminal of the first NAND gate A6 is connected to a third node C between the fourth inverter A4 and the first OR gate A5; A first AND gate A7, wherein a first input terminal of the first AND gate A7 is connected to the output terminal of the first OR gate A5, a second input terminal of the first AND gate A7 is connected to the output terminal of the first NAND gate A6, and an output terminal of the first AND gate A7 outputs a third control signal SO3.

5. The control signal generating circuit according to claim 4, wherein: The signal output circuit further includes a third signal output module, and the third signal output module includes a second logic unit; In the third signal output module, the power supply voltage VDD is grounded in sequence through the fifth switch M5, the sixth switch M6, and the third controllable current source G3. The positive control terminal of the third controllable current source G3 is connected to the positive control terminal of the second controllable current source G2, and the negative control terminal of the third controllable current source G3 is grounded. The first input signal S1 is connected to the control terminals of the fifth switch M5 and the sixth switch M6 via the third inverter A3. The first terminal of the second logic unit is connected to the current output terminal of the fifth switch M5, and the second terminal of the second logic unit is connected to the logic signal SP. The second logic unit outputs the fourth control signal SO4 based on the logic signal SP and the first input signal S1.

6. The control signal generating circuit according to claim 5, wherein: The second logic unit includes: a fifth inverter A8, whose input terminal serves as a first terminal of the second logic unit; a second OR gate A9, wherein a first input terminal of the second OR gate A9 is connected to the output terminal of the fifth inverter A8; a sixth inverter A10, having an input end serving as the second end of the second logic unit and an output end connected to the second input end of the second OR gate A9; a second NAND gate A11, wherein a first input terminal of the second NAND gate A11 is connected to the output terminal of the sixth inverter A10, and a second input terminal of the second NAND gate A11 is connected to a fifth node E between the fifth inverter A8 and the second OR gate A9; A second AND gate A12, wherein a first input terminal of the second AND gate A12 is connected to the output terminal of the second OR gate A9, a second input terminal of the second AND gate A12 is connected to the output terminal of the second NAND gate A11, and an output terminal of the second AND gate A12 outputs a fourth control signal SO4.

7. The control signal generating circuit according to claim 6, wherein: In the phase control circuit, the power supply voltage VDD is grounded sequentially through the fourth controllable current source G4 and the seventh switch tube M7. The power supply voltage VDD is also grounded sequentially through the first resistor R1, the eighth switch tube M8, the ninth switch tube M9, and the second resistor R2. The power supply voltage VDD is also grounded sequentially through the fifth controllable current source G5 and the second resistor R2. The power supply voltage VDD is also grounded sequentially through the sixth controllable current source G6 and the seventh controllable current source G7. A sixth node F between the eighth switch tube M8 and the ninth switch tube M9 is connected to the second input signal S2. The control terminal of the eighth switch tube M8 is connected to the control terminal of the ninth switch tube M9, and both are connected to the fourth controllable current source. A seventh node G between G4 and the seventh switch tube M7; the positive control terminals of the fifth controllable current source G5 and the sixth controllable current source G6 are both connected to the power supply voltage VDD, the negative control terminal of the fifth controllable current source G5 is connected to the negative control terminal of the sixth controllable current source G6, and both are connected to the current input terminal of the eighth switch tube M8; an eighth node H between the sixth controllable current source G6 and the seventh controllable current source G7 outputs a logic signal SP; the negative control terminal of the seventh controllable current source G7 is grounded, the positive control terminal of the seventh controllable current source G7 is connected to the positive control terminal of the first controllable current source G1, and both are connected to the current output terminal of the ninth switch tube M9.

8. The control signal generating circuit according to claim 7, wherein: In the phase control circuit, the power supply voltage VDD is further connected to ground via the third resistor R3 and the first current source B1 in sequence. The power supply voltage VDD is further connected to ground via the eighth controllable current source G8, the tenth switch tube M10, and the fourth resistor R4 in sequence. The power supply voltage VDD is further connected to ground via the eighth controllable current source G8, the eleventh switch tube M11, and the ninth controllable current source G9 in sequence. The control terminal of the eleventh switch tube M11 is connected to ground via the first voltage source E1. The control terminal of the seventh switch tube M7 is connected to the current output terminal of the eleventh switch tube M11. end; the positive control end of the ninth controllable current source G9 is connected to the current output end of the tenth switch tube M10, and the negative control end of the ninth controllable current source G9 is grounded; the positive control ends of the eighth controllable current source G8 and the fourth controllable current source G4 are both connected to the power supply voltage VDD, the negative control end of the eighth controllable current source G8 is connected to the negative control end of the fourth controllable current source G4, and are both connected between the third resistor R3 and the first current source B1; the control end of the tenth switch tube M10 is connected to the second input signal S2.

9. The control signal generating circuit according to claim 8, wherein: The current coefficient of the seventh controllable current source G7 is less than 1; The current coefficients of the first controllable current source G1 , the second controllable current source G2 , the third controllable current source G3 , the fifth controllable current source G5 , the sixth controllable current source G6 and the ninth controllable current source G9 are all equal to 1.

10. The control signal generating circuit according to claim 9, wherein: The second input signal S2 includes a first sub-signal S21 and a second sub-signal S22 . The voltage of the first sub-signal S21 is lower than the first voltage V1 , and the voltage of the second sub-signal S22 is higher than the first voltage V1 .

11. An integrated circuit control chip, characterized in that: The method comprises a control signal generating circuit according to any one of claims 1 to 10 and a plurality of control circuits, wherein the control signal generating circuit is connected to each control circuit and is used to output control signals with the same frequency but different phases to the control circuits.

12. A miniaturized high-precision power supply circuit, characterized in that: The invention comprises an integrated circuit control chip as claimed in claim 11 and an external power circuit.

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