QC-LDPC coding method based on FPGA resource optimization

Abstract

The invention belongs to the technical field of communication, and particularly relates to a QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) coding method based on FPGA (Field Programmable Gate Array) resource optimization, which comprises the following steps of: determining a basis matrix, a lifting factor and a generation submatrix according to the code length and the code rate of an input information sequence, and storing the information into a storage unit; a control signal is generated through the register unit, so that correct alignment of data on a time sequence is ensured, and the data can be accurately transmitted to the calculation unit; in the calculation unit, input serial data is subjected to serial-to-parallel conversion and is subjected to block processing according to the line number of the generated sub-matrixes, and each data block is matched with the generated sub-matrixes; and performing parallel multiplication operation on the data subjected to serial-parallel conversion and block processing and the generated sub-matrix to complete the encoding process. According to the method, the sub-matrixes are stored and generated according to the interval Z, so that occupation of BRAM resources in the FPGA during processing of the long code length sequence is effectively reduced, and therefore, the coding efficiency and the resource utilization rate of the system are remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and particularly relates to a QC-LDPC encoding method based on FPGA resource optimization. Background Art

[0002] With the progress of satellite communication technologies, LDPC codes have become one of the most promising encoding schemes at present and have been widely applied in international standards. Especially in the fields of deep space communication and low-earth orbit satellite communication, the advantages of quasi-cyclic LDPC codes are more prominent. Traditional LDPC encoder designs usually focus on optimization methods based on parity-check matrices, especially when using large-scale sparse matrices. However, these methods often face high computational complexity and resource consumption during hardware implementation, especially in applications oriented to high throughput and low latency, where traditional methods are difficult to meet the strict requirements for hardware resources and processing speed. With the increasing demands for data transmission rate and communication reliability in fields such as satellite communication, deep space exploration, and 5G, how to design an efficient, scalable, and resource-optimized LDPC encoder has become an urgent challenge to be solved.

[0003] Especially on an FPGA-based hardware platform, traditional parity-check matrix-based LDPC encoders often cannot fully utilize the parallel computing advantages of FPGAs, and when facing large-scale encoding, the hardware resource consumption is too large, resulting in low flexibility and efficiency in their applications. At the same time, quasi-cyclic LDPC codes (QC-LDPC codes) have become the mainstream choice in modern encoder designs due to their characteristics of being able to effectively utilize hardware resources. However, although QC-LDPC codes have good hardware implementation advantages, there are still many challenges in their design and implementation processes. Especially on an FPGA platform with limited resources, how to optimize resource utilization, improve throughput, and reduce power consumption remains an urgent problem to be solved in the design process.

[0004] However, although QC-LDPC encoders based on generator matrices have certain advantages in hardware implementation, there are still multiple challenges in terms of resource optimization. First of all, how to design a flexible hardware architecture that takes into account the adaptability of multiple code rates and ensures high efficiency under different transmission conditions is a problem that needs in-depth study. Secondly, since the resources of FPGAs are limited, how to maximize the utilization of FPGA computing resources while ensuring high throughput and avoid waste of hardware resources is another major challenge in the design. Finally, how to effectively manage power consumption to ensure that the encoder can operate stably under high-load working conditions and meet the high requirements for energy efficiency in scenarios such as satellite communication and deep space exploration is also an important consideration in the design. Summary of the Invention

[0005] To solve the above technical problems, the present invention provides a QC-LDPC encoding method based on FPGA resource optimization, including:

[0006] S1: Determine the base matrix BG1 or BG2, the lifting factor Z, and the generating sub-matrix P according to the code length and code rate of the input information sequence din;

[0007] The code lengths of the input information sequence din include: 256, 512, 1024, 2048, 4096, 8192, and the code rates include: 1 / 3, 1 / 2, 2 / 3, 3 / 4, 5 / 6;

[0008] S2: Combine the value of the lifting factor Z, send part of the generating sub-matrix P information into the ROM unit of the FPGA, and at the same time generate corresponding control signals in combination with the register unit, and reconstruct the P matrix according to the cyclic characteristics of the generating sub-matrix;

[0009] The control signals include: enable signal en, address signal addr, and storage end signal end;

[0010] S3: Perform serial-to-parallel conversion on the din data, divide it into blocks every Z, and match the matrix size of the generating sub-matrix in combination with the control signals;

[0011] S4: Perform multiplication operation on the serial-to-parallel converted din data and the generating sub-matrix P, and finally output the encoded sequence.

[0012] Advantages of the present invention:

[0013] By combining code rate matching and the quasi-cyclic characteristics of QC-LDPC, the present invention optimizes the FPGA resource configuration, especially reduces the use of BRAM resources, thereby improving the calculation efficiency of the encoder, reducing the hardware resource consumption, and ensuring the requirements of high throughput and low power consumption. Description of the Drawings

[0014] Figure 1 It is the FPGA block diagram of a QC-LDPC encoding method based on FPGA resource optimization of the present invention;

[0015] Figure 2 It is the schematic diagram of the encoding parameter matching unit of a QC-LDPC encoding method based on FPGA resource optimization of the present invention;

[0016] Figure 3 It is the BG1 matrix size diagram of a QC-LDPC encoding method based on FPGA resource optimization of the present invention;

[0017] Figure 4 It is the BG2 matrix size diagram of a QC-LDPC encoding method based on FPGA resource optimization of the present invention;

[0018] Figure 5 Schematic diagram of the storage unit structure of a QC-LDPC encoding method based on FPGA resource optimization according to the present invention;

[0019] Figure 6 Signal timing diagram of the storage unit of a QC-LDPC encoding method based on FPGA resource optimization according to the present invention. Detailed implementation manners

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] A QC-LDPC encoding method based on FPGA resource optimization, as Figure 1 shown, aims to optimize the FPGA resource configuration, especially reduce the use of BRAM resources, by combining code rate matching and the quasi-cyclic characteristics of QC-LDPC. First, the input information sequence is processed through dynamic code rate matching and the calculation of the lifting factor Z to generate the corresponding code rate and matrix information, and this information is stored in the storage unit of the FPGA. Subsequently, control signals are generated through the register unit to ensure correct data alignment in terms of timing, guaranteeing that the data can be accurately transmitted to the calculation unit. In the calculation unit, the input serial data is subjected to serial-to-parallel conversion and block processing according to the number of rows of the generator sub-matrix, and each data block is matched with the generator sub-matrix to ensure efficient parallel computing in the FPGA. Finally, the data after serial-to-parallel conversion and block processing is subjected to parallel multiplication operation with the generator sub-matrix, and the encoding result is obtained through bitwise AND (AND) and bitwise XOR (XOR) operations to complete the encoding process.

[0022] The specific steps are as follows:

[0023] Step 1: The input bit stream din is first processed by the code rate matching unit to determine the required encoding parameters, such as code rate, lifting factor Z, base matrix, and generator matrix, etc. The core of this process is to construct the corresponding matrix according to the quasi-cyclic characteristics of the generator matrix to ensure the efficiency of the encoding process. The calculation of the lifting factor Z provides key parameters for subsequent matrix operations and the construction of the generator sub-matrix, ensuring the correct processing and transmission of data in the subsequent steps. Finally, the processed input data din will be transmitted to the calculation unit to enter the subsequent encoding process.

[0024] Step 2: The matrix information obtained through rate matching will be stored in the storage unit of the FPGA and combined with the register unit to generate necessary control signals. Using these control signals, the system can reconstruct the parity-check matrix according to the quasi-cyclic characteristics of the generated matrix. This reconstruction process ensures that the matrix structure can adapt to the parallel computing mode, thereby improving the hardware processing efficiency. In addition, in this way, the storage and control of the matrix can achieve efficient data transmission, ensuring the smooth progress of subsequent encoding calculations.

[0025] Step 3: In this process, the input serial data din will be converted into a parallel data stream and divided into blocks according to the number of rows of the generated sub-matrix. The size of each data block matches the number of rows of the generated sub-matrix. By combining the control signals, the system can accurately determine the structure of each data block and the corresponding generated sub-matrix, thus ensuring that the data block can be correctly docked with the matrix for subsequent encoding operations.

[0026] Step 4: The data after block processing will perform a parallel matrix multiplication operation with the generated sub-matrix. Through this operation, the input data sequence is encoded into the final output codeword.

[0027] The specific content of Step 1 is as follows:

[0028] Step 1-1: The input bitstream din and the matching code rate determine the encoding parameters as Figure 2 shown, determine the BG graph type, and the sizes of BG1 and BG2 are respectively as Figure 3 , Figure 4 shown, as well as the encoding parameters. At the same time, the H matrix is decomposed into two parts: H mxn = [H mxk | H mxm , where H mxk , H mxm are respectively represented as H s and H p . The generated sub-matrix P can be obtained as: P = (H p -1 · H s ) T , where H represents the base matrix, H s , H p are respectively the first and second sub-matrices of the H matrix, P represents the generated sub-matrix, H p -1 represents the first inverse sub-matrix of the H matrix, and T represents the matrix transpose.

[0029] The specific content of Step 2 is as follows:

[0030] Step 2-1: Through the timing control signal, ensure that each unit inside the FPGA (such as ROM, computing unit, and storage unit) performs data operations in the correct order.

[0031] The function of the control signal is to indicate the timing of each data storage or reading operation, ensuring that each operation unit performs an operation in each clock cycle, thereby avoiding data conflicts or losses in parallel operations. Accurate timing control enables coordination between modules within the FPGA to ensure that data can be smoothly and accurately transferred from the ROM to the computing unit. The storage unit interface is shown in Table 1:

[0032] Table 1. Storage unit interface description

[0033]

[0034] Step 2-2: In FPGA, the storage and operation of the generated sub-matrix need to be synchronized. By controlling the address line and counter, ensure that the generated sub-matrix can be read and stored in the correct order in each clock cycle. Every Z clock cycles, the address line will increment by one, pointing to the next storage location, and store the elements or part of the generated sub-matrix to the specified location. The storage unit structure is as follows Figure 5 As shown, the internal signal timing diagram is as follows Figure 6 The control signal works together with the counter to ensure that the increment of the address line complies with the law of circular shift, thereby ensuring that the data of the sub-matrix is ​​correctly stored and read in a predetermined order.

[0035] The step three is specifically as follows:

[0036] Step 3-1: Read the input bit stream (din) from the testbench (TB) file. The read data is usually a serial bit stream, which is stored in an array form through file input and output (I / O) operations. Assume that the input serial data is a bit array:

[0037] din=[d1,d2,d3,…,d lxm ]

[0038] Among them, d lxm Represents the lxmth codeword.

[0039] The size of the generated submatrix is ​​m×n, where m represents the number of rows and n represents the number of columns. The input serial data din is divided into multiple blocks of size m:

[0040] d block =[d1,d2,…,dm],[dm+1,dm+2,…,d2m],…,[d(l-1)m+1

[0041] ,d(l-1)m+2,…,dlm]

[0042] Wherein, l is the total number of blocks, and each data block contains m bits of data.

[0043] Step Three - Two: To ensure the data correctness during matrix operations, especially the order during multiplication, the input bit array will be flipped. This is because in the parallel computing of FPGA, some hardware modules require data to be read starting from the rightmost (least significant bit) or from the most significant bit. The bit - flipping operation will ensure the alignment of the subsequent matrix multiplication order. After the flipping operation, din:

[0044] din rev =[d lxm ,d lxm-1 ,…,d1]

[0045] Step Three - Three: After bit - flipping, the flipped data needs to be divided into blocks according to the number of rows m of the generated sub - matrix. The divided data d block As shown in formula (13). At this time, through the control signal, the system matches each data block with the structure of the generated sub - matrix. The structure of the generated sub - matrix will affect how the data blocks are mapped in the hardware. Each data block is matched one - by - one with the rows of the generated matrix to ensure that they can be docked with the rows of the generated matrix, thus preparing for the subsequent parallel multiplication operation. Specifically, the control signal will ensure that each data block corresponds to each row of the generated sub - matrix, thereby realizing parallel computing.

[0046] The specific content of Step Four is as follows:

[0047] Step Four - One: After serial - to - parallel conversion, the input data din is divided into multiple data blocks and organized according to the structure of the generated sub - matrix. Each element of each data block will perform a bit - by - bit AND operation with the elements of the corresponding row of the generated sub - matrix, and then perform an XOR operation. Specifically, each bit in the data block will perform a bit - by - bit AND operation with the corresponding bit in the generated sub - matrix, and the obtained results are then merged through the XOR operation. The register interface of the calculation process is shown in Table 2:

[0048] Table 2. Description of the calculation register interface

[0049]

[0050] Step 4-2: Output codeword construction. The main register variables used are din_temp, mem_datta, and sum. The specific process is as follows: First, store the din information bits read from the tb file into the array din_temp, then send them to the serial-to-parallel conversion module, and then flip the information bits and store them in din_temp. Finally, perform an exclusive OR operation on the data in din_temp and the sum data to obtain the output codeword. After multiplying the codeword after serial-to-parallel conversion by the generating submatrix P, and then concatenating the input codeword din on the left, the output codeword can be obtained. The I / O interfaces of the FPGA top-level module are shown in Table 3:

[0051] Table 3. Description of the I / O Interfaces of the Top-Level Module

[0052] signal input / output description sys_clk input system clock rst_n input reset signal, active low din input input data stream dout output output data stream

[0053] The output codeword c = s·G:

[0054]

[0055] where s is the input codeword and G is the generating matrix:

[0056] G = [I k | P]

[0057] where P is the generating submatrix with a size of m×n, and the output codeword is obtained:

[0058] c = s·G = s·[I|P] = [s|s·P]

[0059] According to the above formula, it can be seen that: when the codeword after serial-to-parallel conversion is multiplied by the generating submatrix P, and then the input codeword din is concatenated on the left, the output codeword can be obtained.

[0060] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A QC-LDPC encoding method based on FPGA resource optimization, characterized in that it includes: S1: Determine the base matrix BG1 or BG2, the lifting factor Z, and the generating sub-matrix P according to the code length and code rate of the input information sequence din; The code lengths of the input information sequence din include: 256, 512, 1024, 2048, 4096, 8192, and the code rates include: 1 / 3, 1 / 2, 2 / 3, 3 / 4, 5 / 6; S2: Combine the value of the lifting factor Z, send part of the generating sub-matrix P information to the ROM unit of the FPGA, and at the same time generate corresponding control signals in combination with the register unit, and reconstruct the P matrix according to the cyclic characteristics of the generating sub-matrix; The control signals include: enable signal en, address signal addr, and storage end signal end; S3: Perform serial-to-parallel conversion on the din data, divide it into blocks every Z, and match the matrix size of the generating sub-matrix in combination with the control signal; S4: Perform a multiplication operation on the serial-to-parallel converted din data and the generating sub-matrix P, and finally output the encoded sequence.

2. The QC-LDPC encoding method based on FPGA resource optimization according to claim 1, characterized in that determining the base matrix BG1 or BG2, the lifting factor Z, and the generating sub-matrix P according to the code length and code rate of the input information sequence din includes: S11: When the input information sequence din is greater than 3824 bits, the system will add 24-bit CRC check bits to the input data; if din is less than or equal to 3824 bits, only 16-bit CRC check bits will be added, and the length of the intermediate sequence after verification is denoted as dsum; S12: Determine the base matrix information. The base matrix BG1 satisfies any one of the conditions: (1) dsum is less than or equal to 292; (2) dsum is less than or equal to 3824 and the code rate is less than or equal to 0.67; (3) the code rate is less than or equal to 0.25; otherwise, it is determined as BG2; Determine the value of the lifting factor Z according to dsum = 22 * Z(BG1) or dsum = 10 * Z(BG2), and at the same time, assign the dsum length to the input information sequence din; S13: Replace each element in the determined base matrix BG information with an identity matrix of size ZxZ to obtain the parity-check matrix H; S14: Decompose the H matrix into two parts to obtain the generating sub-matrix P.

3. The QC-LDPC encoding method based on FPGA resource optimization according to claim 2, characterized in that decomposing the H matrix into two parts to obtain the generating sub-matrix P includes: H = [H S |H P ​ P = (H p -1 ·H s ) T Among them, H represents the base matrix, H s , H p respectively represent the first and second sub-matrices of the H matrix, P represents the generating sub-matrix, H p -1 represents the first inverse sub-matrix of the H matrix, and T represents the matrix transpose.

4. The QC-LDPC encoding method based on FPGA resource optimization according to claim 1, characterized in that combining the value of the lifting factor Z, sending part of the generating sub-matrix P information to the ROM unit of the FPGA, and at the same time generating corresponding control signals in combination with the register unit, and reconstructing the P matrix according to the cyclic characteristics of the generating sub-matrix includes: S21: Feed the generated sub - matrix P into the ROM unit of the FPGA at an interval of Z. When storing each column of data in the matrix, it will be sequentially allocated to the internal ROM of the FPGA, and the storage address of each column will increase by addr + 1 as Z increases, so as to ensure that each column of data can be successfully stored in the corresponding storage location according to the matrix structure. Among them, the address line during the storage process also increases at an interval of Z, so that the corresponding memory address can be correctly accessed each time data is stored; S22: Set the control signals including: enable signal en, address signal addr, storage end signal end. After the enable signal en is pulled high, the counter cnt starts to count. Use the counter cnt to perform cyclic reconstruction on the column information of the matrix. The counter cnt will automatically increment at each interval of Z, update the data storage address addr of the current matrix column, and ensure that these data can be successfully read and written during the storage process; The counter is used to help the system dynamically adjust the storage location and ensure that the matrix column information can be stored and reconstructed in the correct order according to the lifting factor Z; S23: During the process of storing the matrix information, the control signals inside the FPGA and the counter work synchronously to achieve timing alignment. This means that at each interval of Z, the control signals will coordinate each operation module to ensure that the data is transmitted in the correct order, and ensure that the data can be accurately transmitted from the RAM to the computing unit during each access process; in addition, the counter will assist in updating the storage address to ensure that the order and timing of the data are consistent during each operation, and avoid data errors caused by timing mismatches; S24: Reconstruct the parity - check matrix based on the lifting factor Z to meet the requirements of QC - LDPC coding. During this process, the column information of the parity - check matrix is gradually updated and adjusted at an interval of Z, so that the matrix can correctly reflect its structural characteristics at each interval of Z, and at the same time can also meet the requirements of QC - LDPC coding.

5. A QC - LDPC coding method based on FPGA resource optimization according to claim 1, characterized in that the din data is subjected to serial - to - parallel conversion, and is divided into blocks every Z, and the matrix size of the generated sub - matrix is generated by combining with the control signal matching, including: S31: Perform serial - to - parallel conversion on the input din data. The input serial data is parallelized through the control signal to meet the row width required for generating the matrix; S32: After the P - matrix information is stored in the ROM, the storage end signal end is pulled high, the counter cnt is set to 0, the P - matrix is cyclically shifted to the right at each clock, and the counter cnt is controlled to increment by 1. When the counter cnt is Z, start shifting to read the next P - matrix information. According to the block - division situation of each data block, determine the size of the generated matrix, and ensure that the number of rows and columns of the matrix is consistent with the requirements of subsequent matrix multiplication operations.

6. A QC-LDPC encoding method based on FPGA resource optimization according to claim 1, characterized in that the din data after serial-to-parallel conversion is multiplied by the generated sub-matrix P, and the finally encoded sequence is output, including: S41: After serial-to-parallel conversion, the input data din is divided into multiple data blocks and multiplied by the generated sub-matrix. Each element of each data block is bitwise ANDed with each column in the parity-check matrix to ensure that each input bit is combined with the bits in the corresponding column of the matrix according to the logical "AND" relationship. After the bitwise AND operation is completed, the result is further bitwise XORed, and the results of multiple bitwise AND operations are integrated to form the final encoded output; The bitwise XOR operation ensures that the combination of each bit conforms to the generation rule of the QC-LDPC encoding.

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