Stepped double-layer heterojunction diode and preparation method and application thereof

Abstract

The invention discloses a stepped double-layer heterojunction diode. The stepped double-layer heterojunction diode comprises the following structures from top to bottom: a multi-layer structure, a substrate and a cathode, wherein the multilayer structure sequentially comprises an anode, a second Cu2O layer, a first Cu2O layer and a Ga2O3 drift layer from top to bottom, and the diameters of the anode, the second Cu2O layer, the first Cu2O layer and the Ga2O3 drift layer are gradually increased. The second Cu2O layers with different diameters in the stepped structure of the device can transfer the position where a peak electric field of the device appears, and secondly, since the hole concentration of the first Cu2O layer is smaller than that of the second Cu2O layer, the peak electric field can be transferred from the edge of an anode to the edge of the second Cu2O layer with higher hole concentration, and the peak electric field can be transferred to the edge of the second Cu2O layer with higher hole concentration. Therefore, the peak electric field appears in the body of the device, so that the voltage-withstanding characteristic of the device is remarkably improved. Meanwhile, a heterojunction depletion layer is widened, the breakdown voltage characteristic of the device is greatly improved, reverse leakage current is reduced, and the electrical performance of the device is integrally improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a stepped double heterojunction diode, a preparation method thereof, and an application thereof. Background Art

[0002] With the continuous development of semiconductor devices and application technologies towards high efficiency and low power consumption, currently, the first-generation traditional semiconductor material silicon (Si) has approached the limit of its material performance. The second-generation semiconductor materials gallium arsenide (GaAs) and indium phosphide (InP) continue to heat up in the field of optical communication. The third-generation semiconductor materials silicon carbide (SiC) and gallium nitride (GaN) have gradually achieved commercialization. Future power devices will develop towards higher power figure of merit (PFOM), higher breakdown voltage, and lower resistance. The fourth-generation semiconductor material gallium oxide (Ga2O3) has a wider bandgap (4.2 eV - 4.9 eV), higher breakdown field strength (8 MV / cm), higher Baliga figure of merit (3444 Ω·cm 2 / V2), lower production cost, and stable physical and chemical properties compared to SiC (3.3 eV) and GaN (3.4 eV). These advantages make it an excellent candidate material for preparing the next-generation high-efficiency and low-energy-consuming power electronic devices, and it has broad development prospects in the fields of power devices, optoelectronic devices, etc.

[0003] Gallium oxide has a total of 5 different crystal orientation structures, namely α, β, γ, δ, and ε. Among them, β-Ga2O3 is the most stable crystal orientation and is also the most widely studied one. Currently, the main challenges faced by β-Ga2O3 are the difficulties in preparing p-type gallium oxide and its relatively low thermal conductivity. The problem of difficult p-type preparation of gallium oxide is the key to improving the electrical performance of devices. Currently, the main way to solve the problem of the absence of p-type gallium oxide is to select p-type oxide semiconductors for heterostructure construction, but problems such as the deposition quality and reliability of p-type oxides still need to be solved, and currently, there is no effective solution for p-type gallium oxide.

[0004] Chinese patent document with publication number CN116344626A discloses a trench gallium oxide heterojunction diode with an inclined plane terminal. This technical solution improves the peak electric field at the interface of the NiO and gallium oxide heterojunction, suppresses the peak electric field at the mesa of the NiO and gallium oxide heterojunction, and improves the electric field distribution in the drift region. It greatly improves the electrical performance of the gallium oxide heterojunction diode. In addition, the angle of the inclined plane terminal has a great influence on the device performance and still needs further exploration. However, in the above patent, p-type NiO still has problems such as unstable material properties and low material mobility.

[0005] Gallium oxide has excellent properties such as higher breakdown characteristics and lower on-resistance, which is the focus of current research by scientists. However, it is difficult to achieve p-type doping in gallium oxide, which limits the realization of bipolar devices with better performance. Although constructing a heterojunction using a p-type oxide and n-type gallium oxide can break through this limitation to a certain extent, the difficulty of p-type doping remains a challenge. On the other hand, the structure of the device also has a huge impact on the final electrical properties of the device. The common heterojunction diode is a simple superposition deposition of two materials, with a single structure and poor electric field management, resulting in no significant improvement in the electrical properties of the device.

[0006] Therefore, there is an urgent need to develop a stepped double-layer heterojunction diode to solve the above problems. Summary of the Invention

[0007] Based on the defects and deficiencies in the prior art, the present invention provides a stepped double-layer heterojunction diode. By forming two p-type Cu2O (cuprous oxide) layers with different hole concentrations and controlling the sizes of the two p-type Cu2O layers, the p-type Cu2O and other structures of the diode jointly construct a stepped pyramid structure, greatly improving the breakdown voltage characteristics of the device, reducing the reverse leakage current, and overall improving the electrical performance of the device.

[0008] An object of the present invention is to provide the above-mentioned stepped double-layer heterojunction diode, which includes the following structures from top to bottom: a multi-layer structure, a substrate, and a cathode;

[0009] Among them, the multi-layer structure sequentially includes an anode with gradually increasing diameter, a second Cu2O layer, a first Cu2O layer, and a Ga2O3 drift layer from top to bottom;

[0010] The hole concentration of the first Cu2O layer is less than that of the second Cu2O layer.

[0011] Further, the Ga2O3 drift layer sequentially includes a second Ga2O3 drift layer and a first Ga2O3 drift layer from top to bottom;

[0012] The diameter of the second Ga2O3 drift layer is less than that of the first Ga2O3 drift layer.

[0013] Further, the thicknesses of the first Cu2O layer and the second Cu2O layer are 5 - 30 nm.

[0014] Further, the hole concentration of Cu2O in the first Cu2O layer is 1.0 - 7.8×10 17 cm -3 .

[0015] Further, the hole concentration of Cu2O in the second Cu2O layer is 1.0 - 5.6×10 19 cm -3 .

[0016] Further, the material of the first Cu2O layer is p-Cu2O.

[0017] Further, the material of the second Cu2O layer is p+Cu2O.

[0018] Specifically, p-type Cu2O, as a p-type material, has good mobility and good thermal stability. Therefore, the device prepared using p-type Cu2O can increase the thermal conductivity of the device, improve the electrical performance of the device, especially the breakdown performance of the device, without adding difficult process operations.

[0019] More specifically, by depositing a double-layer Cu2O of a stepped second Cu2O layer and a first Cu2O layer on the surface of gallium oxide, a pn heterojunction is further constructed, and the hole concentrations of the second Cu2O layer and the first Cu2O layer are regulated, broadening the depletion width of the heterojunction, so that the maximum electric field strength generated by the device is transferred from the original pn junction interface to the step of p-type Cu2O, effectively improving the breakdown characteristics of the device.

[0020] Specifically, p-type cuprous oxide (Cu2O), as a p-type material, although its bandgap width is only 2.1 eV, it has the advantages of good mobility and good thermal stability. By directly depositing p-type cuprous oxide on gallium oxide, a heterojunction structure is formed at the contact surface between gallium oxide and cuprous oxide, greatly improving the recombination rate of electrons and holes in the device. In addition, it also plays a great role in improving the breakdown voltage and leakage current of the device. The HJD prepared based on n-type gallium oxide and p-type nickel oxide also improves problems such as large reverse leakage current, low reverse bias voltage, and relatively concentrated electric field near the pn junction of the device. The use of p-type oxides further improves the electrical performance and other advantages of the device.

[0021] The present invention also provides a preparation method of the stepped double-layer heterojunction diode. The preparation method of the stepped double-layer heterojunction diode includes the following steps:

[0022] S1. Prepare a Ga2O3 epitaxial wafer. The Ga2O3 epitaxial wafer from top to bottom is a Ga2O3 drift layer and a substrate. An annular groove is etched on the upper outer edge of the Ga2O3 drift layer to form a second Ga2O3 drift layer and a first Ga2O3 drift layer with an increasing diameter from top to bottom;

[0023] S2. Deposit a cathode on the lower surface of the substrate and perform annealing treatment;

[0024] S3. Deposit a first Cu2O layer, a second Cu2O layer, and an anode in sequence on the second Ga2O3 drift layer to form a multi-layer structure with gradually increasing diameters from top to bottom, obtaining a stepped double-layer heterojunction diode.

[0025] Further, in step S1, the depth of the groove is 650 - 680 nm.

[0026] Further, the preparation methods of the first Cu2O layer and the second Cu2O layer are Physical Vapor Deposition (PVD) processes;

[0027] The deposition pressure is 0.4 - 0.6 Pa, and the sputtering distance is about 20 - 50 cm.

[0028] Further, in step S2, the annealing temperature is 450 - 520 °C, and the annealing time is 60 - 90 s.

[0029] Further, in step S3, the sputtering deposition gases are argon and oxygen, and the ratio of argon to oxygen is 50:1 - 50:3.

[0030] Specifically, due to the difficulty of p-type doping caused by the large bandgap of gallium oxide material, the diode performance is limited to a certain extent. Depositing a stepped double-layer Cu2O on the surface of gallium oxide further constructs a pn heterojunction in the diode. The regulation of the hole concentration of p-type Cu2O broadens the depletion width of the heterojunction, making the maximum electric field intensity generated by the diode transfer from the original pn junction interface to the step of p-type Cu2O, effectively improving the breakdown characteristics of the diode. Based on only two-step photolithography processing, the present invention can achieve a stepped structure and improve the breakdown characteristics.

[0031] Specifically, the sputtering of Cu2O uses dual-chamber magnetron sputtering deposition. By adjusting parameters such as the chamber pressure, sputtering distance, and argon / oxygen ratio, the hole concentration and deposition quality are regulated, and a stepped double-layer Cu2O device structure with different concentrations is defined through two photolithographies, thereby effectively regulating the electric field and ultimately improving the breakdown voltage and leakage of the device.

[0032] Another object of the present invention is to provide the application of the stepped double-layer heterojunction diode in the field of semiconductor materials.

[0033] The beneficial effects of the present invention are as follows:

[0034] The device proposed by the present invention deposits a first p-type Cu₂O with a low hole concentration on the surface of the Ga₂O₃ drift layer, and then deposits a second p-type Cu₂O with a high hole concentration to form a second Cu₂O layer and a first Cu₂O layer respectively, forming two p-type Cu₂Os with different hole concentrations. At the same time, by setting the second Cu₂O layer and the first Cu₂O layer with two different diameters, a multi-layer structure can be jointly constructed with other structures of the diode. Compared with the conventional structure, firstly, the positions where the peak electric field appears in the transfer device can be shifted by the second Cu₂O layer and the first Cu₂O layer with different diameters in the multi-layer structure. Secondly, due to the different hole concentrations of the second Cu₂O layer and the first Cu₂O layer, the peak electric field can be transferred from the anode edge to the edge of the second Cu₂O layer with a higher hole concentration, so that the peak electric field appears inside the device, thereby significantly improving the breakdown voltage characteristics of the device. At the same time, the structure of the present invention broadens the heterojunction depletion layer, greatly improves the breakdown voltage characteristics of the device, reduces the reverse leakage current, and overall improves the electrical performance of the device. Description of the Drawings

[0035] Figure 1 (a)-(f) are schematic process flow diagrams of the stepped double-layer heterojunction diodes of Examples 1-3;

[0036] Figure 2 is a schematic structural diagram of the diode of Comparative Example 1;

[0037] Figure 3 is a schematic structural diagram of the diode of Comparative Example 2;

[0038] In the figure: 11, anode; 12, second Cu₂O layer; 13, first Cu₂O layer; 14, second Ga₂O₃ drift layer; 15, first Ga₂O₃ drift layer; 16, groove; 2, substrate; 3, cathode. Detailed Embodiments

[0039] In order to more clearly illustrate the technical solutions of the present invention, the following examples are listed. The raw materials, reactions, and post-treatment means appearing in the examples are all common raw materials on the market and technical means well-known to those skilled in the art, unless otherwise specified.

[0040] The terms "preferred", "preferably", "more preferably", etc. in the present invention refer to embodiments of the present invention that can provide certain beneficial effects in certain cases. However, in the same or other cases, other embodiments may also be preferred. In addition, the description of one or more preferred embodiments does not imply that other embodiments are not available, nor is it intended to exclude other embodiments from the scope of the present invention.

[0041] It should be understood that, except in any operating instance or otherwise indicated, all numbers representing amounts of ingredients used, for example, in the specification and claims, should be understood to be modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that vary depending upon the desired properties sought to be obtained by the present invention.

[0042] In the embodiment, the standard cleaning includes the following steps: Pour an appropriate amount of acetone solution (covering the flower basket) into a beaker, and pour an appropriate amount of isopropyl alcohol solution into another beaker. Place the sample on the flower basket, and then immerse the flower basket into the acetone solution and the isopropyl alcohol solution in sequence, soaking for 3 minutes respectively; then, use tweezers to pick up the sample and rinse it in flowing deionized water for three minutes; finally, use a nitrogen gun to blow dry the moisture on the surface of the sample to complete the standard cleaning.

[0043] In the embodiment, the diameter is the lateral dimension between the two ends of each layer in the cross-sectional schematic diagram of the stepped double heterojunction diode, such as Figure 1 (a) shows, the diameter in the drawing is the distance between the two ends of the substrate 2.

[0044] Example 1

[0045] A stepped double heterojunction diode, the structural design of which is as Figure 1 (a)-(f) shows, Figure 1 (a)-(f) are the process flow schematic diagrams of the stepped double heterojunction diode. The stepped double heterojunction diode includes the following structures from top to bottom: a multi-layer structure, a substrate 2 (Ga2O3, 650 μm), and a cathode 3 (Ti / Au, 20 nm / 100 nm);

[0046] Among them, the multi-layer structure includes, from top to bottom in sequence, an anode 11 (Ni / Au, 50 nm / 50 nm) with a gradually increasing diameter, a second Cu2O layer 12 (10 nm), a first Cu2O layer 13 (10 nm), and a Ga2O3 drift layer;

[0047] The Ga2O3 drift layer includes, from top to bottom in sequence, a second Ga2O3 drift layer 14 (660 nm) and a first Ga2O3 drift layer 15 (340 nm);

[0048] The diameter of the second Ga2O3 drift layer 14 is smaller than that of the first Ga2O3 drift layer 15;

[0049] The preparation method of the stepped double heterojunction diode is as follows:

[0050] S1-1. Prepare an n-type Ga2O3 epitaxial wafer. The Ga2O3 epitaxial wafer consists of a Ga2O3 drift layer and a substrate from top to bottom. Standardly clean the surface of the Ga2O3 epitaxial wafer, heat the Ga2O3 epitaxial wafer on a hot plate for 30 s to dry the residual moisture on the surface of the Ga2O3 epitaxial wafer. Dropwise coat a tackifier (hexamethyldisilazane, HMDS) on the Ga2O3 epitaxial wafer to enhance the adhesion for subsequent spin-coating of photoresist. Rotate the sample on a spin coater so that the tackifier is evenly spin-coated on the surface of the Ga2O3 epitaxial wafer; continue to dropwise coat the photoresist and rotate the sample on the spin coater so that the photoresist is evenly spin-coated on the surface of the epitaxial wafer; place the Ga2O3 epitaxial wafer on a 100 °C hot plate and bake it for 180 s for pre-baking; use a photomask aligner for photolithography alignment, expose it in hard contact mode, then place the Ga2O3 epitaxial wafer in a developer solution and shake it for development for 30 s, rinse it with deionized water, and blow it dry with a nitrogen gun; place the Ga2O3 epitaxial wafer on a 120 °C hot plate and bake it for 90 s for post-baking and hardening the film, thus completing the photolithographic patterning of the Ga2O3 epitaxial wafer.

[0051] S1-2. To prevent interference between devices, device isolation is usually required. After photolithographic patterning, apply a thermal conductive adhesive to the bottom of the Ga2O3 epitaxial wafer. Use a mixed gas of BCl3 and Cl2 (BCl3:Cl2 = 5:1, v / v), and use an ICP etcher to etch a groove 16 around the outer edge above the Ga2O3 drift layer. The depth of the groove 16 is 660 nm, forming a second Ga2O3 drift layer 14 and a first Ga2O3 drift layer 15 with an increasing diameter from top to bottom. Immerse the etched Ga2O3 epitaxial wafer in an acetone solution for ultrasonic cleaning, then soak it in isopropyl alcohol and rinse it with deionized water. Finally, immerse the Ga2O3 epitaxial wafer in a piranha solution (H2SO4:H2O2 = 4:1) for 15 min to remove impurities such as the thermal conductive adhesive, then place the Ga2O3 epitaxial wafer under deionized water for rinsing, and blow it dry with a nitrogen gun.

[0052] S2-1. Dropwise coat a double-layer photoresist on the front side of the Ga2O3 epitaxial wafer to protect the etched groove. First, dropwise coat LOR photoresist and rotate the sample on a spin coater, and place the epitaxial wafer on a 170 °C hot plate and bake it for 8 min to harden the film. Continue to dropwise coat the photoresist and rotate the sample on the spin coater so that the photoresist is evenly spin-coated on the surface of the epitaxial wafer. Finally, place the Ga2O3 epitaxial wafer on a 100 °C hot plate and bake it for 180 s for pre-baking. Finally, use an electron beam evaporation E-beam system to deposit Ti / Au with a thickness of 20 nm / 100 nm on the back of the substrate as the cathode material.

[0053] S2-2. Place the Ga2O3 epitaxial wafer with deposited Ti / Au metal in a DMSO solution at 80 °C for 30 min, then perform standard cleaning, blow dry with a nitrogen gun. In a nitrogen atmosphere, set the furnace temperature to 450 °C and the annealing time to 70 s, and perform rapid thermal annealing on the Ga2O3 epitaxial wafer to obtain the cathode.

[0054] S3-1. Define the region for depositing p-Cu2O on the second Ga2O3 drift layer with photoresist, and deposit p-Cu2O on the epitaxial wafer using a dual-chamber magnetron sputtering device. The pressure in the deposition chamber is 0.5 Pa, the sputtering distance is about 20 cm, the deposition argon / oxygen ratio is 50:1, v / v, the deposition thickness is controlled at 10 nm. After deposition, perform a lift-off process to retain the required p-Cu2O region, then perform standard cleaning to remove surface contaminants, and finally blow dry the moisture on the surface of the epitaxial wafer with a nitrogen gun to obtain the first Cu2O layer.

[0055] Among them, the hole concentration of Cu2O in the first Cu2O layer is 3.7×10 17 cm -3 。

[0056] S3-2. Define the region for depositing p+Cu2O on the first Cu2O layer with photoresist, and deposit p+Cu2O on the Ga2O3 epitaxial wafer using a dual-chamber magnetron sputtering device. The pressure in the deposition chamber is 0.5 Pa, the sputtering distance is about 20 cm, the deposition argon / oxygen ratio is 50:1, the deposition thickness is controlled at 10 nm. After deposition, perform a lift-off process to retain the required p+Cu2O region, then perform standard cleaning to remove surface contaminants, and blow dry the moisture on the surface of the epitaxial wafer with a nitrogen gun to obtain the second Cu2O layer;

[0057] Among them, the hole concentration of Cu2O in the second Cu2O layer is 1.0×10 19 cm -3 。

[0058] S3-3. Define the region for depositing the anode on the second Cu2O layer with photoresist, then perform standard cleaning to remove surface contaminants and blow dry. Using an electron beam evaporation E-beam system, deposit Ni / Au with a thickness of 50 nm / 50 nm in the gate region as the gate electrode as the anode, forming a multi-layer structure with gradually increasing diameters from top to bottom to obtain a stepped double heterojunction diode.

[0059] Example 2

[0060] A stepped double heterojunction diode, the structure design of which is as Figure 1 (a)-(f) shown, Figure 1(a)-(f) are schematic process flow diagrams of a stepped double heterojunction diode. The stepped double heterojunction diode includes the following structures from top to bottom: a multi-layer structure, a substrate 2 (Ga2O3, 650 μm), and a cathode 3 (Ti / Au, 20 nm / 100 nm);

[0061] Among them, the multi-layer structure includes, from top to bottom in sequence, an anode 11 (Ni / Au, 50 nm / 50 nm) with gradually increasing diameter, a second Cu2O layer 12 (10 nm), a first Cu2O layer 13 (10 nm), and a Ga2O3 drift layer;

[0062] The Ga2O3 drift layer includes, from top to bottom in sequence, a second Ga2O3 drift layer 14 (660 nm) and a first Ga2O3 drift layer 15 (340 nm);

[0063] The diameter of the second Ga2O3 drift layer 14 is smaller than that of the first Ga2O3 drift layer 15;

[0064] The preparation method of the stepped double heterojunction diode is as follows:

[0065] S1-1. Prepare an n-type Ga2O3 epitaxial wafer. The Ga2O3 epitaxial wafer includes a Ga2O3 drift layer and a substrate from top to bottom. Standardly clean the surface of the Ga2O3 epitaxial wafer, heat the Ga2O3 epitaxial wafer on a hot plate for 30 s to dry the residual moisture on the surface of the Ga2O3 epitaxial wafer. Dropwise apply an adhesion promoter (hexamethyldisilazane, HMDS) on the Ga2O3 epitaxial wafer to increase the adhesion for subsequent spin-coating of photoresist. Rotate the sample on a spin coater so that the adhesion promoter is evenly spin-coated on the surface of the Ga2O3 epitaxial wafer; continue to dropwise apply photoresist and rotate the sample on the spin coater so that the photoresist is evenly spin-coated on the surface of the epitaxial wafer; place the Ga2O3 epitaxial wafer on a hot plate at 100 °C and bake it for 180 s for pre-baking; use a photomask aligner for photolithography alignment, expose it in hard contact mode, then place the Ga2O3 epitaxial wafer in a developer and shake it for development for 30 s, rinse it with deionized water, and blow it dry with a nitrogen gun; place the Ga2O3 epitaxial wafer on a hot plate at 120 °C and bake it for 90 s for post-baking and hardening the film to complete the photolithography patterning of the Ga2O3 epitaxial wafer.

[0066] S1-2. To prevent mutual interference between devices, device isolation is usually carried out. After lithographic patterning, a thermal conductive adhesive is applied to the bottom of the Ga2O3 epitaxial wafer. Using a mixed gas of BCl3 and Cl2 (BCl3:Cl2 = 5:1, v / v), an ICP etcher is used to etch a groove 16 around the outer edge above the Ga2O3 drift layer. The depth of the groove 16 is 660 nm, forming a second Ga2O3 drift layer 14 and a first Ga2O3 drift layer 15 with an increasing diameter from top to bottom. The etched Ga2O3 epitaxial wafer is immersed in an acetone solution for ultrasonic cleaning, then soaked in isopropyl alcohol and rinsed with deionized water. Finally, the Ga2O3 epitaxial wafer is immersed in a piranha solution (H2SO4:H2O2 = 4:1, v / v) for 15 min to remove impurities such as the thermal conductive adhesive, and then the Ga2O3 epitaxial wafer is placed under deionized water for rinsing and blown dry with a nitrogen gun.

[0067] S2-1. A double-layer resist is spin-coated on the front side of the Ga2O3 epitaxial wafer to protect the etched groove. First, LOR resist is spin-coated and the sample is rotated on a spin coater, and the epitaxial wafer is placed on a hot plate at 170 °C for 8 min for hard baking. Then, photoresist is continuously spin-coated and the sample is rotated on the spin coater to make the photoresist uniformly spin-coated on the surface of the epitaxial wafer. Finally, the Ga2O3 epitaxial wafer is placed on a hot plate at 100 °C for 180 s for pre-baking. Finally, using an electron beam evaporation E-beam system, Ti / Au with a thickness of 20 nm / 100 nm is deposited on the back side of the substrate as the cathode material.

[0068] S2-2. The Ga2O3 epitaxial wafer with the deposited Ti / Au metal is placed in a DMSO solution at 80 °C for 30 min, then subjected to standard cleaning and blown dry with a nitrogen gun. In a nitrogen atmosphere, the temperature in the furnace is set to 450 °C and the annealing time is 70 s to perform rapid thermal annealing on the Ga2O3 epitaxial wafer to obtain the cathode.

[0069] S3-1. The area for depositing p-Cu2O is defined on the Ga2O3 drift layer with photoresist. A dual-chamber magnetron sputtering device is used to deposit p-Cu2O on the epitaxial wafer. The pressure in the deposition chamber is 0.5 Pa, the sputtering distance is about 30 cm, the volume ratio of deposition argon / oxygen is 30:1, and the deposition thickness is controlled at 20 nm. After deposition, a lift-off process is carried out to retain the required area of p-Cu2O, and then standard cleaning is performed to remove surface contaminants. Finally, the moisture on the surface of the epitaxial wafer is blown dry with a nitrogen gun to obtain the first Cu2O layer.

[0070] Among them, the hole concentration of Cu2O in the first Cu2O layer is 3.5×10 17 cm -3 .

[0071] S3-2. Define the region for depositing p+Cu2O on the first Cu2O layer using photoresist. Deposit p+Cu2O on the Ga2O3 epitaxial wafer using a dual-chamber magnetron sputtering device. The pressure in the deposition chamber is 0.5 Pa, the sputtering distance is about 30 cm, the volume ratio of deposition argon / oxygen is 30:1, the deposition thickness is controlled at 10 nm. After deposition, perform a lift-off process to retain the required region of p+Cu2O, and then perform a standard cleaning to remove surface contaminants. Use a nitrogen gun to blow the moisture on the surface of the epitaxial wafer to a dry state to obtain the second Cu2O layer;

[0072] Among them, the hole concentration of Cu2O in the second Cu2O layer is 4.3×10 19 cm -3 .

[0073] S3-3. Define the region for depositing the anode on the second Cu2O layer using photoresist. After performing a standard cleaning to remove surface contaminants and drying, use an electron beam evaporation E-beam system to deposit Ni / Au with a thickness of 50 nm / 50 nm in the gate region as the gate electrode as the anode, forming a multi-layer structure with a gradually increasing diameter from top to bottom to obtain a stepped double heterojunction diode.

[0074] Example 3

[0075] A stepped double heterojunction diode, the structure design of which is as shown in Figure 1 (a)-(f), Figure 1 (a)-(f) are schematic process flow diagrams of the stepped double heterojunction diode. The stepped double heterojunction diode includes the following structures from top to bottom: a multi-layer structure, a substrate 2 (Ga2O3, 650 μm), a cathode 3 (Ti / Au, 20 nm / 100 nm);

[0076] Among them, the multi-layer structure includes, from top to bottom, an anode 11 (Ni / Au, 50 nm / 50 nm) with a gradually increasing diameter, a second Cu2O layer 12 (10 nm), a first Cu2O layer 13 (10 nm), and a Ga2O3 drift layer;

[0077] The Ga2O3 drift layer includes, from top to bottom, a second Ga2O3 drift layer 14 (660 nm) and a first Ga2O3 drift layer 15 (340 nm);

[0078] The diameter of the second Ga2O3 drift layer 14 is smaller than that of the first Ga2O3 drift layer 15;

[0079] The preparation method of the stepped double heterojunction diode is as follows:

[0080] S1-1. Prepare an n-type Ga2O3 epitaxial wafer. The Ga2O3 epitaxial wafer consists of a Ga2O3 drift layer and a substrate from top to bottom. Standardly clean the surface of the Ga2O3 epitaxial wafer, heat the Ga2O3 epitaxial wafer on a hot plate for 30 s to dry the residual moisture on the surface of the Ga2O3 epitaxial wafer. Dropwise coat a tackifier (hexamethyldisilazane, HMDS) on the Ga2O3 epitaxial wafer to enhance the adhesion for subsequent spin-coating of photoresist. Rotate the sample on a spin coater so that the tackifier is uniformly spin-coated on the surface of the Ga2O3 epitaxial wafer; continue to dropwise coat the photoresist and rotate the sample on the spin coater so that the photoresist is uniformly spin-coated on the surface of the epitaxial wafer; place the Ga2O3 epitaxial wafer on a hot plate at 100 °C and bake for 180 s for pre-baking; use a photomask aligner for photolithography alignment, expose in hard contact mode, then place the Ga2O3 epitaxial wafer in a developer solution and shake it for development for 30 s, rinse with deionized water, and blow dry with a nitrogen gun; place the Ga2O3 epitaxial wafer on a hot plate at 120 °C and bake for 90 s for post-baking and hardening the film to complete the photolithographic patterning of the Ga2O3 epitaxial wafer.

[0081] S1-2. To prevent interference between devices, device isolation is usually carried out. After photolithographic patterning, apply a thermal conductive adhesive to the bottom of the Ga2O3 epitaxial wafer. Use a mixed gas of BCl3 and Cl2 (BCl3:Cl2 = 5:1, v / v), and use an ICP etcher to etch a groove 16 around the upper outer edge of the Ga2O3 drift layer. The depth of the groove 16 is 660 nm, forming a second Ga2O3 drift layer 14 and a first Ga2O3 drift layer 15 with an increasing diameter from top to bottom. Immerse the etched Ga2O3 epitaxial wafer in an acetone solution for ultrasonic cleaning, then soak it in isopropyl alcohol and rinse it with deionized water. Finally, immerse the Ga2O3 epitaxial wafer in a piranha solution (H2SO4:H2O2 = 4:1, v / v) for 15 min to remove impurities such as the thermal conductive adhesive, then place the Ga2O3 epitaxial wafer under deionized water for rinsing and blow dry with a nitrogen gun.

[0082] S2-1. Dropwise coat a double-layer resist on the front side of the Ga2O3 epitaxial wafer to protect the etched groove. First, dropwise coat LOR resist and rotate the sample on a spin coater, and place the epitaxial wafer on a hot plate at 170 °C and bake for 8 min to harden the film. Continue to dropwise coat the photoresist and rotate the sample on the spin coater so that the photoresist is uniformly spin-coated on the surface of the epitaxial wafer. Finally, place the Ga2O3 epitaxial wafer on a hot plate at 100 °C and bake for 180 s for pre-baking. Finally, use an electron beam evaporation E-beam system to deposit Ti / Au with a thickness of 20 nm / 100 nm on the back side of the substrate as the cathode material.

[0083] S2-2. Place the Ga2O3 epitaxial wafer with deposited Ti / Au metal in a DMSO solution at 80 °C for 30 min, then perform standard cleaning, dry it with a nitrogen gun. In a nitrogen atmosphere, set the furnace temperature to 450 °C and the annealing time to 90 s, and perform rapid thermal annealing on the Ga2O3 epitaxial wafer to obtain the cathode.

[0084] S3-1. Define the area for depositing p-Cu2O on the Ga2O3 drift layer with photoresist, and deposit p-Cu2O on the epitaxial wafer using a dual-chamber magnetron sputtering device. The pressure in the deposition chamber is 0.5 Pa, the sputtering distance is about 50 cm, the deposition argon / oxygen ratio is 10:1, the deposition thickness is controlled at 30 nm. After deposition, perform a lift-off process to retain the required area of p-Cu2O, then perform standard cleaning to remove surface contaminants, and finally use a nitrogen gun to blow the moisture on the surface of the epitaxial wafer to a dry state to obtain the first Cu2O layer.

[0085] Among them, the hole concentration of Cu2O in the first Cu2O layer is 5.6×10 17 cm -3 .

[0086] S3-2. Define the area for depositing p+Cu2O on the first Cu2O layer with photoresist, and deposit p+Cu2O on the Ga2O3 epitaxial wafer using a dual-chamber magnetron sputtering device. The pressure in the deposition chamber is 0.5 Pa, the sputtering distance is about 50 cm, the volume ratio of deposition argon / oxygen is 30:1, the deposition thickness is controlled at 10 nm. After deposition, perform a lift-off process to retain the required area of p+Cu2O, then perform standard cleaning to remove surface contaminants, and use a nitrogen gun to blow the moisture on the surface of the epitaxial wafer to a dry state to obtain the second Cu2O layer;

[0087] Among them, the hole concentration of Cu2O in the second Cu2O layer is 3.7×10 19 cm -3 .

[0088] S3-3. Define the area for depositing the anode on the second Cu2O layer with photoresist, then perform standard cleaning to remove surface contaminants and dry it. Using an electron beam evaporation E-beam system, deposit Ni / Au with a thickness of 50 nm / 50 nm in the gate area as the gate electrode as the anode to form a multi-layer structure with a gradually increasing diameter from top to bottom, and obtain a stepped double heterojunction diode.

[0089] Comparative Example 1

[0090] A diode, whose structure is as Figure 2As shown in the figure, the difference between this comparative example and Example 1 is that the multi-layer structure, substrate, and cathode of Comparative Example 1 have the same diameter, and the diameters of each layer in the multi-layer structure are the same, and other structural designs are the same as those in Example 1.

[0091] Comparative Example 2

[0092] A diode, the structure of which is as Figure 3 shown. The difference between this comparative example and Example 1 is that the second Cu2O layer is removed, and other structural designs are the same as those in Example 1.

[0093] Comparative Example 3

[0094] A diode, the structure of which is as Figure 3 shown. The difference between this comparative example and Example 1 is that the concentrations of the first Cu2O layer and the second Cu2O layer are both 5.6×10 17 cm -3 , and other structural designs are the same as those in Example 1.

[0095] Test Example

[0096] Perform performance tests on the diodes of Example 1 and Comparative Examples 1-3.

[0097] Breakdown voltage and turn-on voltage test: Use a B1505A power device analyzer to test the breakdown voltage and turn-on voltage of the diodes of Example 1 and Comparative Examples 1-3;

[0098] Reverse leakage test: Use a 4200-csc type semiconductor characteristic analysis system to test the reverse leakage of the diodes of Example 1 and Comparative Examples 1-3.

[0099] The test results are shown in Table 1.

[0100] Table 1 Performance test results of the devices of Example 1 and Comparative Examples 1-3

[0101]

[0102] It can be seen from the data in Table 1 that the device of the present invention can not only effectively transfer the peak electric field into the device body, thereby significantly increasing the breakdown voltage, effectively suppressing the reverse leakage, and the suppression effect on the leakage is better than that of Comparative Examples 1-3, but also can effectively reduce the turn-on voltage and reduce the loss.

[0103] It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, in any regard, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention.

[0104] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A stepped double heterojunction diode, characterized in that, The stepped double heterojunction diode includes the following structure from top to bottom: a multi-layer structure, a substrate, and a cathode; Among them, the multi-layer structure sequentially includes an anode with gradually increasing diameter, a second Cu2O layer, a first Cu2O layer, and a Ga2O3 drift layer from top to bottom; The hole concentration of the first Cu2O layer is less than that of the second Cu2O layer.

2. The stepped double heterojunction diode according to claim 1, wherein The Ga2O3 drift layer sequentially includes a second Ga2O3 drift layer and a first Ga2O3 drift layer from top to bottom; The diameter of the second Ga2O3 drift layer is less than that of the first Ga2O3 drift layer.

3. The stepped double heterojunction diode according to claim 1, wherein The hole concentration of Cu2O in the first Cu2O layer is 1.0 - 7.8×10 17 cm -3 .

4. The stepped double heterojunction diode according to claim 1, wherein The hole concentration of Cu2O in the second Cu2O layer is 1.0 - 5.6×10 19 cm -3 .

5. The stepped double heterojunction diode according to claim 1, characterized in that The material of the first Cu2O layer is p-Cu2O.

6. The stepped double heterojunction diode according to claim 1, wherein The material of the second Cu2O layer is p+Cu2O.

7. The preparation method of the stepped double - layer heterojunction diode according to any one of claims 1 - 6, characterized in that, The preparation method of the stepped double heterojunction diode includes the following steps: S1. Prepare a Ga2O3 epitaxial wafer. The Ga2O3 epitaxial wafer sequentially includes a Ga2O3 drift layer and a substrate from top to bottom. An etch groove is formed around the outer edge above the Ga2O3 drift layer to form a second Ga2O3 drift layer and a first Ga2O3 drift layer with gradually increasing diameter from top to bottom; S2. Deposit a cathode on the lower surface of the substrate and perform annealing treatment; S3. Deposit a first Cu2O layer, a second Cu2O layer, and an anode on the second Ga2O3 drift layer in sequence to form a multi-layer structure with gradually increasing diameter from top to bottom, and obtain a stepped double heterojunction diode.

8. The preparation method of the stepped double - layer heterojunction diode according to claim 7, characterized in that, In step S1, the depth of the groove is 650 - 680 nm.

9. The preparation method of the stepped double-layer heterojunction diode according to claim 7, wherein, The preparation methods of the first Cu2O layer and the second Cu2O layer are PVD processes; The deposition pressure is 0.4 - 0.6 Pa, and the sputtering distance is about 20 - 50 cm.

10. Application of the stepped double heterojunction diode according to any one of claims 1 - 6 in the field of semiconductor materials.

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