Reverse conducting insulated gate bipolar transistor and manufacturing method thereof

Abstract

The present disclosure relates to a reverse conducting insulated gate bipolar transistor (10), the reverse conducting insulated gate bipolar transistor comprising: a main substrate (12); a plurality of insulated gate bipolar transistor regions (14) provided on the main substrate (12); and a plurality of diode regions (16) disposed on the main substrate (12). The insulated gate bipolar transistor regions (14) and / or the diode regions (16) are arranged in a plurality of rows (18, 19, 20), each row (18, 19, 20) extending in a first direction (d1). The insulated gate bipolar transistor regions (14) of at least two adjacent ones of the plurality of rows (18, 19, 20) and / or the diode regions (16) of at least two adjacent ones of the plurality of rows (18, 19, 20) are arranged in a staggered manner along a second direction (d2) substantially perpendicular to the first direction (d1). The present disclosure also relates to a method of manufacturing at least one reverse conducting insulated gate bipolar transistor (10).

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly, to a reverse-conducting insulated gate bipolar transistor and a manufacturing method thereof. Background Art

[0002] Power semiconductor devices are widely used in various fields and / or for multiple purposes. In particular, power semiconductor devices can be used as switches or rectifiers in power electronic devices (e.g., switched-mode power supplies). in the switch or rectifier.

[0003] An insulated gate bipolar transistor (IGBT) is a power semiconductor device mainly used to provide and / or form an electronic switch. It is generally considered that an insulated gate bipolar transistor combines relatively high efficiency with relatively fast switching.

[0004] Insulated gate bipolar transistors often prevent reverse current flow. This means that, for example, unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors generally cannot conduct current flow in the reverse direction. Therefore, in cases where reverse current flow and / or suitable reverse current flow is required, insulated gate bipolar transistors have been modified by including at least one additional diode, sometimes referred to as a freewheeling diode ("FWD"), on the same chip as the insulated gate bipolar transistor. The additional diode can be arranged in parallel (particularly anti-parallel) with the corresponding insulated gate bipolar transistor to preferably selectively conduct current in the opposite or reverse direction. Such a reverse-conducting insulated gate bipolar transistor can replace a combination of one or more insulated gate bipolar transistor chips and one or more discrete diode chips (this combination is also referred to as a "discrete IGBT and diode solution"), thus providing a more compact size.

[0005] However, known insulated gate bipolar transistors in the prior art have some disadvantages. For example, insulated gate bipolar transistors generally generate a relatively large amount of heat. This may make known insulated gate bipolar transistors in the prior art vulnerable to damage and / or may shorten the lifespan of the insulated gate bipolar transistor.

[0006] Known reverse-conducting insulated gate bipolar transistors dissipate heat relatively well, especially compared to insulated gate bipolar transistors without reverse-conducting functionality, because the various regions of the reverse-conducting insulated gate bipolar transistor operate alternately, particularly as an IGBT and as a freewheeling diode in an alternating manner. However, there is still a need to further increase and / or improve the ability of reverse-conducting insulated gate bipolar transistors to handle the heat generated.

[0007] For example, as chips (e.g., reverse-conducting insulated gate bipolar transistors) have become more compact over the years, the problem of heat generation by the corresponding transistors may be exacerbated.

[0008] In addition, as another example, as chips become more powerful, they may generate more heat, particularly heat related to their size, thereby further increasing the need for improved heat handling capabilities.

[0009] Furthermore, in general, improving the ability of a device (e.g., a reverse-conducting insulated gate bipolar transistor) to handle heat generated by the device is advantageous, such as extending the life of the device and / or reducing the risk of damage and / or failure.

[0010] However, the above aspects have not been or at least not fully addressed in the prior art. Therefore, there is a need to improve the reverse-conducting insulated gate bipolar transistors known in the prior art. Summary of the Invention

[0011] Accordingly, an object of the present invention is to provide improved insulated gate bipolar transistors, particularly by providing improvements in one or more of the above aspects.

[0012] The above object is achieved by a reverse-conducting insulated gate bipolar transistor as defined in one aspect of the present invention. Preferred embodiments are defined by further features, respectively.

[0013] The transistor may include a main substrate. The transistor may include a plurality of insulated gate bipolar transistor regions, also referred to as IGBT regions, which may be disposed on and / or in the main substrate. The transistor may include a plurality of diode regions disposed on and / or in the main substrate. The insulated gate bipolar transistor regions and / or the diode regions may be arranged in multiple rows, each row extending in a first direction. The main substrate may be made of at least one semiconductor material. The main substrate may include one or more layers, preferably made of different materials (or may include different materials) and / or may be processed in different ways to provide multiple layers with one or more different properties.

[0014] As discussed above, such configurations of reverse-conducting insulated gate bipolar transistors having a plurality of insulated gate bipolar transistor (IGBT) regions and a plurality of diode regions arranged in multiple rows are known from the prior art. By operating the insulated gate bipolar transistor (IGBT) regions and the diode regions in an alternating manner (preferably, sequentially and / or selectively), such a reverse-conducting insulated gate bipolar transistor can enable current to flow in two directions (particularly two substantially opposite directions).

[0015] However, according to the present disclosure, along a second direction that is substantially perpendicular to the first direction, The insulated gate bipolar transistor regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows and / or the diode regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows can be arranged in a staggered manner. In other words, the insulated gate bipolar transistor regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows and / or the diode regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows are arranged offset from each other, that is, in a checkerboard pattern. In other words, the insulated gate bipolar transistor regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows and / or the diode regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows are not aligned, that is, at least partially misaligned. In other words, the insulated gate bipolar transistor regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows and / or the diode regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows do not overlap or at least do not completely overlap along the second direction.

[0016] This can increase the boundary area and / or boundary volume bordering the insulated gate bipolar transistor regions and / or the diode regions, and the heat generated by the corresponding regions (especially when the corresponding regions are being operated) can be dissipated into this boundary area and / or boundary volume. This can increase the level of heat dissipation from the insulated gate bipolar transistor regions and / or the diode regions. In particular, this can allow the insulated gate bipolar transistor regions and / or the diode regions to dissipate heat to one or more adjacent rows, or at least improve such heat dissipation. This can improve the temperature distribution of the reverse conducting insulated gate bipolar transistor, for example, improving the temperature distribution at one or more of its surfaces.

[0017] Furthermore, for example, compared with a configuration in which the insulated gate bipolar transistor regions and / or the diode regions are arranged in multiple lines or strips, the insulated gate bipolar transistor regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows and / or the diode regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows being arranged in a staggered manner along the second direction can reduce the size of each insulated gate bipolar transistor region and / or each diode region and / or can increase the surface-to-volume ratio of each region, thereby increasing and / or facilitating heat dissipation from the corresponding regions.

[0018] Preferably, the diode regions and / or the insulated gate bipolar transistor regions are arranged such that the diode regions and / or the insulated gate bipolar transistor regions can dissipate heat in at least 3 (preferably, at least 4) directions that are substantially in a single plane, for example, the heat on each row at least along the first direction and the direction opposite to the first direction, to adjacent rows in the second direction and the direction opposite to the second direction.

[0019] Preferably, at least some of the insulated gate bipolar transistor regions (preferably, each insulated gate bipolar transistor region) are arranged adjacent to at least three (preferably, at least four) diode regions. Alternatively or additionally, at least some of the diode regions (preferably, each diode region) are arranged adjacent to at least three (preferably, at least four) insulated gate bipolar transistor regions. Preferably, adjacent insulated gate bipolar transistor regions along the first direction and / or the second direction are separated from each other by at least one diode region. The corresponding insulated gate bipolar transistor regions and / or diode regions can dissipate heat to other adjacent insulated gate bipolar transistor regions and diode regions in the insulated gate bipolar transistor regions and diode regions.

[0020] Preferably, additionally, the insulated gate bipolar transistor regions of at least two adjacent rows in multiple rows and / or the diode regions of at least two adjacent rows in multiple rows are arranged in a staggered manner along the first direction. In other words, the insulated gate bipolar transistor regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows and / or the diode regions of at least two adjacent rows (preferably, at least three adjacent rows) in multiple rows are arranged in a staggered manner along the first direction and the second direction. This can further increase the boundary area and / or boundary volume bordering the insulated gate bipolar transistor regions and / or diode regions, and the heat generated by the corresponding regions (especially when the corresponding regions are operating) can be dissipated to this boundary area and / or boundary volume.

[0021] In the context of the present disclosure, the term "row" may mean a row and / or a column.

[0022] The reverse-conducting insulated gate bipolar transistor can be configured such that multiple insulated gate bipolar transistor (IGBT) regions can be operated simultaneously, for example, in the IGBT mode. Alternatively or additionally, the reverse-conducting insulated gate bipolar transistor can be configured such that multiple diode regions can be operated simultaneously, for example, in the reverse or freewheeling mode.

[0023] The diode region can be configured as a freewheeling diode (FWD) or a fast recovery diode (FRD).

[0024] Each insulated gate bipolar transistor region may include one or more trenches that can be filled with an electrode material (e.g., polysilicon). In other words, the insulated gate bipolar transistor region can be configured as a trench-gate type insulated gate bipolar transistor region. Preferably, at least one of the trenches substantially circumferentially surrounds the corresponding insulated gate bipolar transistor region or at least one or more components of the corresponding insulated gate bipolar transistor region. At least one gate (preferably, at least one insulated gate) can be provided or formed on and / or in one or more trenches. The insulated gate can include at least one conductive material that can be at least partially filled in the corresponding trench, and this conductive material can also be referred to as a gate electrode. The gate can be at least partially electrically insulated by at least one gate insulator film, and the at least one gate insulator film can at least partially cover or coat the conductive material. The gate or the gate electrode can be electrically connected or connectable to a gate electrode terminal.

[0025] Each insulated gate bipolar transistor region can be divided into a plurality of sub-regions by trenches. Each trench of the insulated gate bipolar transistor region can extend from the front surface side of the main substrate into a layer of the main substrate, and this layer is preferably made of an n-type or n-base semiconductor material. Each trench can terminate in the layer.

[0026] Each diode region may include one or more trenches that can be filled with an electrode material (e.g., polysilicon). Preferably, at least one of the trenches substantially circumferentially surrounds the corresponding diode region. At least one conductive material can be at least partially filled in the corresponding trench. The conductive material can be at least partially electrically insulated by at least one gate insulator film, and the at least one gate insulator film can at least partially cover or coat the conductive material.

[0027] Each diode region can be divided into a plurality of sub-regions by one or more of the trenches. Each trench of the diode region can extend from the front surface side of the main substrate into a layer of the substrate, and this layer is preferably made of an n-type or n-type semiconductor material. Each trench can terminate in the layer.

[0028] The trenches in the diode region can be connected to the emitter potential, for example, to at least one top metal layer, through one or more contacts. The trenches in the diode region are not configured to conduct current.

[0029] The trenches in the insulated gate bipolar transistor region can be used for current conduction and can also be referred to as gate trenches.

[0030] The insulated gate bipolar transistor regions and the diode regions can be arranged in an alternating manner along a first direction and / or a second direction.

[0031] The transistor may include multiple rows of an insulated gate bipolar transistor region and / or multiple rows of a diode region along a first direction and / or a second direction.

[0032] The insulated gate bipolar transistor region and the diode region may be separated from each other by at least one isolation region configured to substantially isolate at least one of the insulated gate bipolar transistor regions from at least one of the diode regions.

[0033] Each isolation region may include at least one isolation trench, preferably, a plurality of isolation trenches. Each isolation region may include at least one p-type (preferably, at least a deep-diffused p-type) region. The p-type region may extend further into the main substrate compared to one or more (preferably, each) of the trenches of the insulated gate bipolar transistor region and / or the diode region, e.g., into at least one underlying layer preferably made of an n-type or n-type-like semiconductor material. At least one of the trenches may at least partially surround (preferably, completely surround around at least one periphery) each diode region and / or each insulated gate bipolar transistor region or at least some of the diode regions and / or at least some of the insulated gate bipolar transistor regions.

[0034] The p-type region may extend into the underlying n-type layer by at least 1.5 μm (also referred to as the junction depth).

[0035] In the context of the present disclosure, a "p-type region" will be understood as a region, preferably, an implantation region implanted with boron and / or indium (preferably, a high-energy boron species and / or indium species), preferably, a region doped with boron and / or indium. The p-type region has preferably undergone a heat treatment.

[0036] In the case where the p-type region is configured as a deep-diffused p-type region, the p-type region may extend into the underlying n-type layer by at least 4 μm (also referred to as the junction depth).

[0037] In the context of the present disclosure, an "n-type region" will be understood as a region, preferably, an implantation region implanted with phosphorus, arsenic, and / or antimony, preferably, a region doped with phosphorus, arsenic, and / or antimony.

[0038] Each isolation trench or at least some of the isolation trenches may be connected to an emitter potential.

[0039] The p-type region may be at least partially disposed between at least two of the plurality of isolation trenches of the corresponding isolation region.

[0040] Each insulated gate bipolar transistor region may include at least one collector layer, preferably having a high impurity concentration, which is preferably made of p-type (preferably, p+-type) semiconductor material. The collector layer may be arranged on the opposite side of the n-type layer compared to the trenches of the insulated gate bipolar transistor region and / or the diode region, and is at least partially arranged within the main substrate.

[0041] Each insulated gate bipolar transistor region may include at least one cathode layer, preferably having a high impurity concentration, which is preferably made of n-type semiconductor material.

[0042] The main substrate may include at least one buffer layer, preferably made of n-type semiconductor material. The buffer layer may be at least partially arranged between the cathode layer and the trenches of the insulated gate bipolar transistor region and / or the diode region and / or between the collector layer and the trenches of the insulated gate bipolar transistor region and / or the diode region. Preferably, at least two layers (preferably both made of n-type semiconductor material) may be at least partially arranged between the cathode layer and the trenches of the insulated gate bipolar transistor region and / or the diode region and / or between the collector layer and the trenches of the insulated gate bipolar transistor region and / or the diode region.

[0043] The aspect ratio of the length of each insulated gate bipolar transistor region and / or each diode region along a first direction to the length along a second direction may be in the range of 0.4 to 2.5, preferably 0.5 to 2.4, more preferably 0.6 to 2.2, more preferably 0.6 to 2, more preferably 0.6 to 1.8, more preferably 0.6 to 1.6, more preferably 0.6 to 1.4, more preferably 0.8 to 1.4, more preferably 0.8 to 1.2. For example, this may increase and / or facilitate heat dissipation from the corresponding region compared to a region configured as a strip or line having a larger aspect ratio.

[0044] The transistor may further include at least one gate signal distributor trench that interconnects one or more trenches of adjacent insulated gate bipolar transistor regions. The gate signal distributor trench may be configured to supply a gate voltage, in particular an applied gate voltage, to each insulated gate bipolar transistor region. The gate signal distributor or at least one or more of its segments may extend in the first direction or the second direction, i.e., along a substantially straight path and / or a staggered path. The gate signal distributor trench may extend at least partially into the substrate and may be configured to at least partially receive a conductive material.

[0045] One or more of the insulated gate bipolar transistor regions may include at least one first trench that circumferentially extends around one or more second trenches of the corresponding insulated gate bipolar transistor region.

[0046] Each insulated gate bipolar transistor region or at least some of the insulated gate bipolar transistor regions may include at least one first trench, preferably a plurality of first trenches. Each first trench may be configured as a dummy gate or a dummy trench. The dummy gate or dummy trench may also be referred to as an auxiliary trench or an auxiliary gate, or more generally as a "dummy region". Each insulated gate bipolar transistor region or at least some of the insulated gate bipolar transistor regions may include at least one second trench, preferably a plurality of second trenches. Each second trench may be configured as a true gate.

[0047] In the context of the present disclosure, a dummy region will be understood as a region that is not used for current conduction in the on-state of the corresponding region (i.e., the corresponding insulated gate bipolar transistor region and / or diode region), e.g., a dummy trench or a dummy gate.

[0048] The dummy region (e.g., a dummy trench or a dummy gate) may be configured as a p-type region.

[0049] The dummy region may be electrically connected or connectable to at least one top metal layer, e.g., an emitter or an emitter potential. Alternatively, the dummy gate or dummy trench may be "floating", i.e., not connected to any potential.

[0050] Each insulated gate bipolar transistor region or at least some of the insulated gate bipolar transistor regions may include at least one p-type region, preferably at least one deep p-type region.

[0051] Each insulated gate bipolar transistor region or at least some of the insulated gate bipolar transistor regions may include a plurality of trenches, and / or each diode region includes a plurality of trenches.

[0052] At least two adjacent trenches among the plurality of trenches in one or more of the insulated gate bipolar transistor regions may be arranged at a distance of at least 1 μm, preferably at least 2 μm, more preferably at least 3 μm, more preferably at least 4 μm, more preferably at least 5 μm.

[0053] At least two adjacent trenches among the plurality of trenches in one or more of the insulated gate bipolar transistor regions may be arranged at a distance of less than 1 μm, preferably less than 0.9 μm, more preferably less than 0.8 μm, more preferably less than 0.7 μm, more preferably less than 0.6 μm, more preferably less than 0.5 μm.

[0054] The present disclosure also relates to a method of manufacturing at least one reverse-conducting insulated gate bipolar transistor (preferably, the reverse-conducting insulated gate bipolar transistor according to any one of the foregoing aspects). The features, configurations, and advantages described above with respect to the reverse-conducting insulated gate bipolar transistor correspondingly apply to this method.

[0055] The method may include:

[0056] Provide a main substrate.

[0057] The method may include:

[0058] Providing a plurality of insulated gate bipolar transistor regions and a plurality of diode regions on the main substrate such that the insulated gate bipolar transistor regions and / or the diode regions are arranged in multiple rows, each row extending in a first direction. Along a second direction substantially perpendicular to the first direction, at least two adjacent rows of the insulated gate bipolar transistor regions among the multiple rows and / or at least two adjacent rows of the diode regions among the multiple rows may be arranged in a staggered manner.

[0059] The various exemplary embodiments of the present disclosure herein are intended to provide features that will become readily apparent when considered in conjunction with the following description with reference to the accompanying drawings. According to various embodiments, exemplary devices are disclosed herein. However, it should be understood that these embodiments are presented by way of example and not limitation, and it will be apparent to those of ordinary skill in the art reading this disclosure that various modifications may be made to the disclosed embodiments while still remaining within the scope of the present disclosure.

[0060] Accordingly, the present disclosure is not limited to the exemplary embodiments and applications described and illustrated herein. Additionally, the specific order and / or hierarchy of steps in the methods disclosed herein are merely exemplary methods. Based on design preferences, the specific order or hierarchy of steps of the disclosed methods or processes may be rearranged while still remaining within the scope of the present disclosure. Accordingly, those of ordinary skill in the art will understand that the methods and techniques disclosed herein present the various steps or acts in the same order, and unless otherwise explicitly stated, the present disclosure is not limited to the specific order or hierarchy presented.

[0061] The following list of aspects provides alternative and / or additional features of the present invention:

[0062] 1. A transistor, preferably configured as a reverse-conducting insulated gate bipolar transistor, the transistor comprising:

[0063] A main substrate;

[0064] A plurality of first selectively conductive regions (preferably, a plurality of insulated gate bipolar transistor regions), provided on and / or in the main substrate,

[0065] A plurality of second selectively conductive regions (preferably, a plurality of diode regions), provided on and / or in the main substrate,

[0066] wherein the first selectively conductive regions and / or the second selectively conductive regions are arranged in multiple rows, each row extending in a first direction, and

[0067] Wherein, along a second direction substantially perpendicular to the first direction, the first selectively conductive regions of at least two adjacent rows among the multiple rows and / or the second selectively conductive regions of at least two adjacent rows among the multiple rows are arranged in a staggered manner.

[0068] 2. The transistor according to aspect 1, wherein the insulated gate bipolar transistor regions and the diode regions are arranged in an alternating manner along the first direction and / or the second direction.

[0069] 3. The transistor according to aspect 1 or 2, wherein the transistor includes multiple rows of insulated gate bipolar transistor regions and / or multiple rows of diode regions along the second direction.

[0070] 4. The transistor according to any one of the foregoing aspects, wherein the insulated gate bipolar transistor regions and the diode regions are separated from each other by at least one isolation region configured to substantially isolate at least one of the insulated gate bipolar transistor regions from at least one of the diode regions.

[0071] 5. The transistor according to aspect 4, wherein each isolation region includes at least one isolation trench (preferably multiple isolation trenches) and optionally at least one deep diffused p-type region.

[0072] 6. The transistor according to aspect 5, wherein the deep diffused p-type region is at least partially arranged between at least two of the multiple isolation trenches of the corresponding isolation region.

[0073] 7. The transistor according to any one of the foregoing aspects, wherein the aspect ratio of the length of each insulated gate bipolar transistor region and / or each diode region along the first direction to the length along the second direction is in the range of 0.4 to 2.5, preferably 0.5 to 2.4, more preferably 0.6 to 2.2, and even more preferably 0.6 to 2.

[0074] 8. The transistor according to any one of the foregoing aspects, further comprising at least one gate signal distributor trench for interconnecting one or more trenches of adjacent insulated gate bipolar transistor regions.

[0075] 9. The transistor according to any one of the foregoing aspects, wherein one or more of the insulated gate bipolar transistor regions include at least one first trench that circumferentially extends around one or more second trenches of the corresponding insulated gate bipolar transistor region.

[0076] 10. The transistor according to any one of the foregoing aspects, wherein each insulated gate bipolar transistor region includes at least one first trench (preferably multiple first trenches) and at least one second trench (preferably multiple second trenches), each first trench being configured as a dummy gate and each second trench being configured as a real gate.

[0077] 11. The transistor according to any one of the foregoing aspects, wherein each insulated gate bipolar transistor region includes at least one deep p-type region.

[0078] 12. The transistor according to any one of the foregoing aspects, wherein each insulated gate bipolar transistor region includes a plurality of trenches, and / or each diode region includes a plurality of trenches.

[0079] 13. The transistor according to aspect 12, wherein at least two adjacent trenches among the plurality of trenches in one or more of the insulated gate bipolar transistor regions are arranged at a distance of at least 1 μm, preferably at least 2 μm, more preferably at least 3 μm, more preferably at least 4 μm, more preferably at least 5 μm.

[0080] 14. The transistor according to aspect 12 or 13, wherein at least two adjacent trenches among the plurality of trenches in one or more of the insulated gate bipolar transistor regions are arranged at a distance less than 1 μm, preferably less than 0.9 μm, more preferably less than 0.8 μm, more preferably less than 0.7 μm, more preferably less than 0.6 μm, more preferably less than 0.5 μm.

[0081] 15. The transistor according to any one of the foregoing aspects, wherein the first selectively conductive region and the second selectively conductive region can operate in an alternating manner and / or in a non-overlapping manner, so that the first selectively conductive region can be operated before and / or after operating the second selectively conductive region.

[0082] 16. A method of manufacturing at least one transistor (preferably, at least one reverse-conducting insulated gate bipolar transistor, preferably, the reverse-conducting insulated gate bipolar transistor according to any one of the foregoing aspects), comprising:

[0083] Providing a main substrate;

[0084] Providing a plurality of first selectively conductive regions (preferably, a plurality of insulated gate bipolar transistor regions) and a plurality of second selectively conductive regions (preferably, a plurality of diode regions) on and / or in the main substrate, such that the first selectively conductive regions and / or the second selectively conductive regions are arranged in a plurality of rows, each row extending in a first direction, wherein, along a second direction substantially perpendicular to the first direction, at least two adjacent rows of the first selectively conductive regions among the plurality of rows and / or at least two adjacent rows of the second selectively conductive regions among the plurality of rows are arranged in a staggered manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Hereinafter, embodiments of the present invention will be further clarified with reference to the drawings. The drawings are schematic diagrams, And thus may not show all details of the system and its components. In particular, the drawings are not necessarily to scale, and the dimensions shown are merely exemplary and may vary. The drawings illustrate exemplary embodiments to provide a thorough understanding of the present invention. The drawings are not intended to limit the scope of the present invention, which is defined by the appended claims and will include their equivalents.

[0086] Figure 1a A reverse-conducting insulated gate bipolar transistor according to an embodiment of the present disclosure is shown in a schematic top view;

[0087] Figure 1b A reverse-conducting insulated gate bipolar transistor according to an embodiment of the present disclosure is shown in a schematic top view;

[0088] Figure 1c A reverse-conducting insulated gate bipolar transistor according to an embodiment of the present disclosure is shown in a schematic top view;

[0089] Figure 2 A reverse-conducting insulated gate bipolar transistor is shown in a schematic top view Figure 1a of;

[0090] Figure 3 A reverse-conducting insulated gate bipolar transistor is shown in a schematic bottom view Figure 1a and Figure 2 of;

[0091] Figure 4 A reverse-conducting insulated gate bipolar transistor according to an embodiment of the present disclosure is shown in a schematic top view;

[0092] Figure 5 A reverse-conducting insulated gate bipolar transistor is shown in a schematic top view Figure 4 of the path of the gate signal distributor trench;

[0093] Figure 6 A reverse-conducting insulated gate bipolar transistor is shown in a schematic top view Figure 4 of the path of the gate signal distributor trench;

[0094] Figure 7 Details of the insulated gate bipolar transistor region and the diode region of a reverse-conducting insulated gate bipolar transistor are shown in a schematic enlarged cross-sectional view Figures 1a to 6 of;

[0095] Figure 8 A modified insulated gate bipolar transistor region according to an embodiment of the present disclosure is shown in a schematic enlarged cross-sectional view;

[0096] Figure 9 A modified insulated gate bipolar transistor region according to an embodiment of the present disclosure is shown in a schematic enlarged cross-sectional view. Detailed implementation mode

[0097] Figures 1a to 1c The reverse-conducting insulated gate bipolar transistor 10 is shown in a schematic top view. The transistor 10 may include a main substrate 12 and a plurality of insulated gate bipolar transistor regions 14 disposed on and / or in the main substrate 12. The transistor 10 may include a plurality of diode regions 16 disposed on and / or in the main substrate 12. For clarity, only some of the insulated gate bipolar transistor regions 14 and diode regions 16 in the figure are given reference numerals. This may apply to one or more other components shown in the figure.

[0098] The transistor 10 may include at least two transistor segments 11 and 15, as Figure 1a shown in an exemplary manner. Each transistor segment 11, 15 may include a plurality of insulated gate bipolar transistor regions 14 and a plurality of diode regions 16. The transistor segments 11 and 15 may be constructed in substantially the same manner. Alternatively, the transistor segments 11 and 15 may be constructed in different ways, for example, having different numbers and / or arrangements of insulated gate bipolar transistor regions 14 and / or diode regions 16.

[0099] As Figure 1a shown, the size (e.g., area) of the region 14 may be substantially the same as that of the region 16. For example, each region 14 may have a first region, and each region 16 may have a second region, and the first region and the second region extend in Figures 1a to 1c the drawing plane and / or extend parallel to the drawing plane. The ratio of the first region to the second region may be substantially 1:1, as Figure 1a shown. Alternatively, the size of the region 14, e.g., the area, may be different from that of the region 16. For example, as Figure 1b and Figure 1c shown, the size, e.g., the area (especially relative to the area that extends in Figures 1a to 1c the drawing plane or extends parallel to the drawing plane) of the region 14 or at least some of the regions 14 may be different. Preferably, the region 14 or at least some of the regions 14 may be larger than the region 16 or at least some of the regions 16, for example, may have an area in Figures 1a to 1ca larger area extending in or parallel to the drawing plane. For example, the ratio of the first area to the second area may be greater than or less than 1:1. For example, the ratio of the first area to the second area may be at least 1.1:1, preferably at least 1.5:1, more preferably at least 2:1, more preferably at least 2.5:1, more preferably at least 3:1. The first area may be the entire area of all regions 14 and / or the second area may be the entire area of all regions 16. Providing an insulated gate bipolar transistor region 14 larger than the diode region 16 can improve IGBT conduction losses, and thus can provide advantages, especially for motor drive applications. Especially from Figure 1b and Figure 1c From the perspective of, the region 14 may surround the diode region 16, particularly close to the gate bus region 27 (see further description below).

[0100] The insulated gate bipolar transistor regions 14 and / or the diode regions 16 may be arranged in multiple rows 18, 19, 20. Each row 18, 19, 20 may extend in a first direction d1. Along a second direction d2 substantially perpendicular to the first direction d1, the insulated gate bipolar transistor regions 14 of at least two adjacent rows among the multiple rows 18, 19, 20 and / or the diode regions 16 of at least two adjacent rows among the multiple rows 18, 19, 20 are arranged in a staggered manner.

[0101] The transistor 10 may include multiple rows 21, 22, 23 of insulated gate bipolar transistor regions 14 and / or multiple rows 21, 22, 23 of diode regions 16 along the second direction d2.

[0102] The insulated gate bipolar transistor regions 14 and the diode regions 16 may be arranged in an alternating manner along the first direction d1 and / or the second direction d2.

[0103] The insulated gate bipolar transistor regions 14 and the diode regions 16 may be separated from each other by at least one isolation region 28, and the at least one isolation region is configured to substantially isolate at least one of the insulated gate bipolar transistor regions 14 from at least one of the diode regions 16.

[0104] The insulated gate bipolar transistor regions 14 of at least two adjacent rows among the multiple rows 18, 19, 20 and / or the diode regions 16 of at least two adjacent rows among the multiple rows 18, 19, 20 being configured in a staggered manner can, for example, increase and / or promote heat dissipation from the corresponding regions by increasing the boundary area and / or boundary volume adjacent to the insulated gate bipolar transistor regions 14 and / or or the diode regions 16. This can improve the temperature distribution of the transistor 10, for example, improve the temperature distribution at one or more of its surfaces.

[0105] In addition, for example, compared to a configuration in which the insulated gate bipolar transistor regions 14 and / or the diode regions 16 are configured as lines or strips, this can reduce the size of each insulated gate bipolar transistor region 14 and / or each diode region 16, thereby increasing and / or facilitating heat dissipation from the corresponding regions.

[0106] The transistor 10 may include at least one gate bus 27. The gate bus 27 may extend at least partially (preferably, completely) around the transistor segment 11 and / or the transistor segment 15.

[0107] The aspect ratio of the length L1 along the first direction d1 to the length L2 along the second direction d2 of each insulated gate bipolar transistor region 14 and / or each diode region 16 may be in the range of 0.4 to 2.5, preferably 0.5 to 2.4, more preferably 0.6 to 2.2, more preferably 0.6 to 2. As described above, especially from Figure 1b and Figure 1c From the perspective of, the region 14 may surround the diode region 16, particularly close to and / or adjacent to the gate bus region 27. For example, such that the region 14 may be at least partially disposed between the corresponding gate bus 27 and the region 16. In this case, the region 14 may extend in the direction d1 for a distance L3, L3', particularly extending from the adjacent region 16 to the corresponding gate bus 27. The region 14 may extend in the direction d2 for a distance L4, L4', particularly extending from the adjacent region 16 to the corresponding gate bus 27.

[0108] Figure 2 Basically shows Figure 1a The transistor 10 as an example, although the same features and / or effects described with respect to Figure 2 Can also be generally applied to Figure 1b and Figure 1c The transistor 10. In particular, Figure 2 Shows heat dissipation (indicated by the arrow 30) from, for example, the diode region 16 during the operation of the diode region 16. This can also be applied to the insulated gate bipolar transistor region 14, for example, during the operation of the insulated gate bipolar transistor region 14. In particular, heat can be dissipated from the corresponding region to adjacent or adjoining regions. For example, as shown in Figure 2 The diode region 16 may dissipate heat to two or more (preferably, three or more) adjacent insulated gate bipolar transistor regions 14 and / or vice versa.

[0109] Figure 3Shows a schematic bottom view of the transistor 10. In particular, each insulated-gate bipolar transistor region 14 may have a p-type (in particular p+-type) region at or towards the bottom of the respective insulated-gate bipolar transistor region 14, as Figure 3 shown. Each diode region 16 may have an n-type (in particular n+-type) region at or towards the bottom of the respective diode region 16, as Figure 3 shown. One or more additional layers may be provided further towards the bottom of the transistor 10, i.e., at least one back layer made of metal, i.e., which may at least partially cover Figure 3 the p+-type and n+-type regions shown in Figure 7 and the corresponding further description below).

[0110] Figure 4 Shows an enlarged view of one of the transistor segments 11, 15 of the transistor 10 (e.g., transistor segment 11). The transistor 10 may include one or more ground contacts 36. The transistor 10 may include one or more gate busbars 38. The gate busbar 38 may be made of polysilicon.

[0111] Each insulated-gate bipolar transistor region 14 may include one or more trenches 40, 42 (also referred to as gate trenches). Each insulated-gate bipolar transistor region 14 may include at least one first trench 42 that circumferentially extends around one or more second trenches 40 of the respective insulated-gate bipolar transistor region 14. Alternatively or additionally, each diode region 16 may include a plurality of trenches 46, 48. Each diode region 16 may include at least one first trench 46 that circumferentially extends around one or more second trenches 48 of the respective diode region 16.

[0112] The transistor 10 may include at least one gate signal distributor trench 50 that interconnects one or more trenches 40, 42 of adjacent insulated-gate bipolar transistor regions 14.

[0113] At least a segment of the gate signal distributor trench 50 may extend in a first direction d1 and / or a second direction d2. At least a segment of the gate signal distributor trench 50 may extend along a substantially straight path, e.g., between the gate busbars 38 (e.g., along the direction d2, as Figure 4 shown) and / or at least a segment of the gate signal distributor trench 50 may extend along a staggered path (e.g., along the direction d1, as Figure 4 shown), e.g., to avoid cross junctions and thereby increase reliability.

[0114] Figure 5 The above-mentioned interleaved path of at least a section of the gate signal distributor trench 50 is shown as an example, and this path is Figure 5 indicated by the arrow in

[0115] Figure 6 The above-mentioned substantially straight path of at least a section of the gate signal distributor trench 50 is shown as an example, and this path is Figure 6 indicated by the arrow in

[0116] Figure 7 Details of one of the insulated gate bipolar transistor regions 14 and one of the diode regions 16 in the insulated gate bipolar transistor region 14 of the transistor 10 are shown in a schematic enlarged cross-sectional view. As discussed above, the insulated gate bipolar transistor region 14 may include one or more trenches 40, 42 (also referred to as gate trenches). The insulated gate bipolar transistor region 14 may include at least one first trench 42 that circumferentially extends around one or more second trenches 40 of the corresponding insulated gate bipolar transistor region 14. Each of the trenches 40, 42 may be at least partially filled with at least one conductive material 56, which may also be referred to as a gate electrode, and the gate electrode may be at least partially electrically insulated by at least one gate insulator film 58, and the at least one gate insulator film may at least partially cover or coat the conductive material 56. The trenches 40, 42 may be electrically connected or connectable to a gate electrode terminal 60 (e.g., an anode), which may be configured as at least one metal layer, via one or more connection elements or regions 61, for example. The trenches 40, 42 may be configured as active trenches.

[0117] The insulated gate bipolar transistor region 14 may include one or more (preferably, at least two) n+-type regions or implants 62. The insulated gate bipolar transistor region 14 may include at least one p+-type region or implant 64. The p+-type region or implant 64 may be arranged between at least two n+-type regions or implants 62. The p+-type region or implant 64 and / or the n+-type region or implant 62 may be arranged between adjacent trenches 40, 42. The p+-type region or implant 64 and / or the n+-type region or implant 62 may be implanted within the p-type region 66.

[0118] As discussed above, the diode region 16 can include a plurality of trenches 46, 48. Each diode region 16 can include at least one first trench 46 that extends circumferentially around one or more second trenches 48 of the respective diode region 16. Each trench 46, 48 can be at least partially filled with at least one conductive material 70, which can be at least partially electrically insulated by at least one insulator film 72, which can at least partially cover or coat the conductive material 70. One or more of the trenches 46, 48 can be configured as passive or "dummy" trenches.

[0119] The diode region 16 can include at least one p+ type region or implant 76. The p+ type region or implant 76 can be implanted within the p-type region 78.

[0120] The isolation region 28 can include at least one isolation trench 80. The isolation trench 80 can be electrically connected or connectable to the gate electrode terminal 60, for example, via one or more connection elements or regions 84. The isolation region 28 can include at least one deep diffused p-type region 86.

[0121] The deep diffused p-type region 86 can be at least partially disposed between at least two of the plurality of isolation trenches 80, and / or can be at least partially disposed within at least one isolation trench 80 that extends circumferentially around the deep diffused p-type region 86.

[0122] The cell pitch or trench pitch cp1 of two adjacent trenches 40, 42 in the insulated gate bipolar transistor region 14 can be different from (specifically, greater than) the cell pitch or trench pitch cp2 of two adjacent trenches 46, 48 in the diode region 16.

[0123] The transistor 10 (specifically, the substrate 12) can include at least one intermediate layer 90, which can be configured as an n-type region. Any of all the trenches 40, 42, 46, 48, 80 can extend into the intermediate layer 90.

[0124] The transistor 10 (specifically, the substrate 12) can include at least one buffer layer 92, which can be configured as an n-type region.

[0125] The intermediate layer 90 and / or the buffer layer 92 can extend across the insulated gate bipolar transistor region 14 and the diode region 16.

[0126] The insulated gate bipolar transistor region 14 can include at least one p+ type region 94, which can be disposed on a side of the intermediate layer 90 and / or the buffer layer 92 opposite to the trenches 40, 42.

[0127] The diode region 16 may include at least one n+-type region 96, and the at least one n+-type region may be disposed on a side of the intermediate layer 90 and / or the buffer layer 92 opposite to the trenches 46 and 48.

[0128] The transistor 10 may include at least one cathode or collector layer 98, and the at least one cathode or collector layer may be made of metal.

[0129] Figure 8 Modifications of the insulated gate bipolar transistor region 14 are shown. In particular, as Figure 8 shown, the insulated gate bipolar transistor region 14 may include at least one deep p-type region 100. The deep p-type region 100 may be disposed between the trenches 40 and / or 42. The deep p-type region 100 may be disposed between the trenches 40. The trench 40 may be adjacent to the deep p-type region 100. The deep p-type region 100 may be configured as a dummy region.

[0130] The distance d between adjacent trenches (in particular, between the trench 40 and the trench 42) may be d > 1 μm.

[0131] Figure 9 Another modification of the insulated gate bipolar transistor region 14 is shown. In particular, as Figure 9 shown, the insulated gate bipolar transistor region 14 may include at least one first trench 102, preferably a plurality of first trenches 102. Each first trench 102 may be configured as a dummy gate. The insulated gate bipolar transistor region 14 may include at least one second trench 104, preferably a plurality of second trenches 104. Each second trench 104 may be configured as a real gate. The distance d between adjacent trenches (in particular, between adjacent second trenches 104) may be d < 1 μm. The first trench 102 and / or the second trench 104 may be electrically connected to the gate electrode terminal 60.

Claims

1. An inverse-conducting insulated gate bipolar transistor (10), comprising: A main substrate (12); A plurality of insulated gate bipolar transistor regions (14) disposed on the main substrate (12); A plurality of diode regions (16) disposed on the main substrate (12); Wherein the insulated gate bipolar transistor regions (14) and / or the diode regions (16) are arranged in multiple rows (18, 19, 20), each row (18, 19, 20) extending in a first direction (d1), and Wherein, along a second direction (d2) substantially perpendicular to the first direction (d1), the insulated gate bipolar transistor regions (14) of at least two adjacent rows among the multiple rows (18, 19, 20) and / or the diode regions (16) of at least two adjacent rows among the multiple rows (18, 19, 20) are arranged in a staggered manner.

2. The transistor (10) according to claim 1, wherein the insulated gate bipolar transistor regions (14) and the diode regions (16) are arranged in an alternating manner along the first direction (d1) and / or the second direction (d2).

3. The transistor (10) according to claim 1 or 2, wherein the transistor (10) comprises multiple rows (21, 22, 23) of the insulated gate bipolar transistor regions (14) and / or multiple rows (21, 22, 23) of the diode regions (16) along the second direction (d2).

4. The transistor (10) according to any one of the preceding claims, wherein the insulated gate bipolar transistor regions (14) and the diode regions (16) are separated from each other by at least one isolation region (28), and the at least one isolation region (28) is configured to substantially isolate at least one of the insulated gate bipolar transistor regions (14) from at least one of the diode regions (16).

5. The transistor (10) according to claim 4, wherein each isolation region (28) comprises at least one isolation trench (80), preferably a plurality of isolation trenches, and optionally at least one deep-diffused p-type region (86).

6. The transistor (10) according to claim 5, wherein the deep-diffused p-type region (86) is at least partially disposed between at least two of the plurality of isolation trenches (80) of the corresponding isolation region (28).

7. The transistor (10) according to any one of the preceding claims, wherein the aspect ratio of the length (L1) along the first direction (d1) to the length (L2) along the second direction (d2) of each insulated gate bipolar transistor region (14) and / or each diode region is in the range of 0.4 to 2.5, preferably 0.5 to 2.4, more preferably 0.6 to 2.2, more preferably 0.6 to 2.

8. The transistor (10) according to any one of the preceding claims, further comprising at least one gate signal distributor trench (50) for interconnecting one or more trenches (40, 42) of adjacent insulated gate bipolar transistor regions (14).

9. The transistor (10) according to any one of the preceding claims, wherein one or more of the insulated gate bipolar transistor regions (14) include at least one first trench (42) that extends circumferentially around one or more second trenches (40) of the respective insulated gate bipolar transistor region (14).

10. The transistor (10) according to any one of the preceding claims, wherein each insulated gate bipolar transistor region (14) includes at least one first trench (102) and at least one second trench (104), wherein the at least one first trench (102) is preferably plural, the at least one second trench (104) is preferably plural, each first trench is configured as a dummy gate, and each second trench is configured as a real gate.

11. The transistor (10) according to any one of the preceding claims, wherein each insulated gate bipolar transistor region (14) includes at least one deep p-type region (100).

12. The transistor (10) according to any one of the preceding claims, wherein each insulated gate bipolar transistor region (14) includes a plurality of trenches (40, 42), and / or each diode region (16) includes a plurality of trenches (46, 48).

13. The transistor (10) according to claim 12, wherein at least two adjacent trenches among the plurality of trenches (40, 42) in one or more of the insulated gate bipolar transistor regions (14) are arranged at a distance of at least 1 μm, preferably at least 2 μm, more preferably at least 3 μm, more preferably at least 4 μm, more preferably at least 5 μm.

14. The transistor (10) according to claim 12 or 13, wherein at least two adjacent trenches among the plurality of trenches (40, 42) in one or more of the insulated gate bipolar transistor regions (14) are arranged at a distance less than 1 μm, preferably less than 0.9 μm, more preferably less than 0.8 μm, more preferably less than 0.7 μm, more preferably less than 0.6 μm, more preferably less than 0.5 μm.

15. A method of manufacturing at least one reverse-conducting insulated gate bipolar transistor (10), preferably the reverse-conducting insulated gate bipolar transistor (10) according to any one of the preceding claims, comprising: providing a main substrate (12); disposing a plurality of insulated gate bipolar transistor regions (14) and a plurality of diode regions (16) on the main substrate (12) such that the insulated gate bipolar transistor regions (14) and / or the diode regions (16) are arranged in multiple rows (18, 19, 20), each row (18, 19, 20) extending in a first direction (d1), wherein, along a second direction (d2) substantially perpendicular to the first direction (d1), the insulated gate bipolar transistor regions (14) of at least two adjacent rows among the multiple rows (18, 19, 20) and / or the diode regions (16) of at least two adjacent rows among the multiple rows (18, 19, 20) are arranged in a staggered manner.

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