Integrated circuit device and manufacturing method thereof

Abstract

A device includes: a first active region; a first ohmic contact layer and a second ohmic contact layer on a front side and a back side of the first portion of the first active region, respectively, and coupled to the front side and the back side of the first portion of the first active region; a metal-to-source / drain (MD) contact including a first portion on the first ohmic contact layer and at least a second portion or a third portion alongside a first lateral side or a second lateral side of the first portion of the first active region, the first portion of the MD contact being coupled to the first ohmic contact layer; and a buried via (BV) structure including: a first portion underlying and coupled to the second ohmic contact layer; and a second portion under the MD contact and coupled to the MD contact. The embodiment of the invention also relates to an integrated circuit device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to integrated circuit devices and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry manufactures a variety of analog and digital devices to solve problems in many different fields. The development of semiconductor process technology nodes has gradually reduced component sizes and tightened pitches, resulting in a gradual increase in transistor density. ICs have become smaller. Summary of the Invention

[0003] Embodiments of the present disclosure provide an integrated circuit device, comprising: a first active region; a first ohmic contact layer and a second ohmic contact layer, respectively located on the front side and the back side of a first portion of the first active region, and coupled to the front side and the back side of the first portion of the first active region; a metal-to-source / drain (MD) contact, comprising a first portion located on the first ohmic contact layer and at least a second portion or a third portion respectively located beside a first lateral side or a second lateral side of the first portion of the first active region, the first portion of the metal-to-source / drain contact being coupled to the first ohmic contact layer; and a buried via (BV) structure, comprising: a first portion, located under the second ohmic contact layer and coupled to the second ohmic contact layer; a second portion, located under the metal-to-source / drain contact and coupled to the metal-to-source / drain contact.

[0004] Another embodiment of the present disclosure provides an integrated circuit device, comprising: with respect to layers respectively extending in orthogonal first and second directions, each of the layers having a thickness with respect to a third direction, the layers including a buried via (BV) layer located above a buried metallization layer, an active region (AR) layer located above the buried via layer, and a first layer located above the active region layer, line structures in the first layer extending in the second direction, the line structures including a first line structure and a second line structure, the first line structure and the second line structure respectively representing a gate of a transistor or an isolation dummy gate (IDG); a metal-to-source / drain region (MD) contact having a first portion in the first layer and a second portion in the active region layer, the metal-to-source / drain contact having ends respectively extending oppositely in the second direction, and the first portion of the metal-to-source / drain contact being located between the first line structure and the second line structure, a first side and a second side of the metal-to-source / drain contact respectively extending oppositely in the first direction towards the first line structure and the second line structure, but being separated from the first line structure and the second line structure by respective first and second gaps; a buried via structure at least in the buried via layer, the buried via structure being located below the second portion of the metal-to-source / drain contact and coupled to the second portion of the metal-to-source / drain contact, the buried via structure having ends respectively extending oppositely in the second direction, and a first side and a second side of the buried via structure respectively extending oppositely in the first direction to be close to the first line structure and the second line structure, but not extending beyond the first line structure and the second line structure; and with respect to the third direction, a buried segment in the buried metallization layer is located below the buried via layer and coupled to the buried via structure.

[0005] Another embodiment of the present disclosure provides a method of manufacturing an integrated circuit device, the method comprising: forming an active region, including: forming a first active region; forming an ohmic contact layer, including: forming a first ohmic contact layer on a front side of a first portion of the first active region, and the first ohmic contact layer being coupled to the front side of the first portion of the first active region; and forming a second ohmic contact layer on a back side of the first portion of the first active region, and the second ohmic contact layer being coupled to the back side of the first portion of the first active region; forming a metal-to-source / drain (MD) contact, including: forming a first portion of the metal-to-source / drain contact on the first ohmic contact layer, creating a coupling between the first ohmic contact layer and the first portion of the metal-to-source / drain contact; and forming a second portion of the metal-to-source / drain contact beside a first lateral side of the first portion of the first active region; or forming a third portion of the metal-to-source / drain contact beside a second lateral side of the first portion of the first active region; and forming a buried via (BV) structure, including: forming a first portion of the buried via structure below the second ohmic contact layer, and the first portion of the buried via structure being coupled to the second ohmic contact layer; and forming a second portion of the buried via structure below the second portion or the third portion of the metal-to-source / drain contact, and the second portion of the buried via structure being coupled to the second portion or the third portion of the metal-to-source / drain contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the figures of the drawings, one or more embodiments are illustrated by way of example and not limitation, wherein, throughout the specification, elements with the same reference numeral signs represent the same elements. Unless otherwise disclosed, the figures are not drawn to scale.

[0007] Figures 1A to 1F are corresponding cross-sectional views according to some embodiments.

[0008] FIG. 2A to FIG. 2B are corresponding layout views according to some embodiments.

[0009] Figure 3A are schematic diagrams according to some embodiments.

[0010] FIG. 3B to FIG. 3D are corresponding layout views according to some embodiments.

[0011] FIG. 4A to FIG. 4C are corresponding cross-sectional views according to some embodiments.

[0012] FIG. 5A to FIG. 5B are corresponding layout views according to some embodiments.

[0013] Figure 5C is a combined schematic view and a three-quarter perspective view according to some embodiments.

[0014] FIG. 6A to FIG. 6D is a corresponding cross-sectional view according to some embodiments.

[0015] FIG. 7A to FIG. 7D is a flowchart of a corresponding method of manufacturing a memory device according to some embodiments.

[0016] Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing process associated therewith according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure discloses many different embodiments or examples for implementing different features of the subject matter. Examples of components, materials, values, steps, operations, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In some embodiments, the term standard cell structure refers to a standardized building block included in various standard cell structure libraries. In some embodiments, various standard cell structures are selected from their libraries and used as components in a layout diagram representing a circuit.

[0020] In some embodiments, the device includes a metal-to-source / drain (MD) contact and a buried via (BV) structure coupled to an active region. In some embodiments, the MD contact is coupled to the active region and wraps the active region to also couple to the BV structure, where such an MD contact is sometimes referred to as a wrap-around (WA) MD contact (WA_MD contact). In some embodiments, more specifically, the device includes: a first active region; a first ohmic contact layer and a second ohmic contact layer located on the front side and the back side of a first portion of the first active region, respectively, and coupled to the front side and the back side of the first portion of the first active region; an MD contact including a first portion located on the first ohmic contact layer and at least a second portion or a third portion located beside a first lateral side or a second lateral side of the first portion of the first active region, respectively, the first portion of the MD contact being coupled to the first ohmic contact layer; and a BV structure including a first portion located below the second ohmic contact layer and coupled to the second ohmic contact layer and a second portion located below the MD contact and coupled to the second portion of the MD contact.

[0021] According to another method, the corresponding device includes: an MD contact corresponding to the WA_MD; a corresponding active region; and a corresponding BV structure. With respect to the short axis of the corresponding active region, the corresponding BV structure according to another method does not significantly extend beyond the corresponding active region. Thus, there is only one current path between the corresponding active region and the corresponding BV structure in the corresponding device according to another method. In contrast, a device including a WA MD contact according to some embodiments (WA_MD-based device) has at least two current paths between the active region and the BV structure because the WA_MD wraps the active region and thus also couples to the BV structure. According to another method, the resistance R_WA_MD between the BV structure and the active region in the WA_MD-based device is significantly lower than the corresponding resistance R_OA. Thus, the power consumption of the WA_MD-based device according to some embodiments is reduced compared to other methods, for example, due to reduced resistive losses. In some embodiments, R_WA_MD ≤ (≈0.5)*R_OA.

[0022] Figure 1A is a cross-sectional view of a device 100A according to some embodiments.

[0023] Device 100A is an example of a device having an MD contact and a BV structure coupled to an active region as discussed below. Device 100A is an example of a device having a WA_MD contact. In some embodiments, device 100A is an example of a device corresponding to the cross-section line I.A-I.A' of Figure 2A the device.

[0024] Figure 1AArranged according to an orthogonal Cartesian coordinate system, where the first direction, the second direction, and the third direction are, for example, correspondingly parallel to the X-axis, the Y-axis, and the Z-axis. In some embodiments, the first orthogonal direction, the second orthogonal direction, and the third orthogonal direction are not correspondingly parallel to the X-axis, the Y-axis, and the Z-axis.

[0025] Device 100A is organized into layers with respect to the Z-axis. The layers of device 100A include: an active region (AR) layer; a G&MD layer located on the AR layer; a VGD layer located on the G&MD layer; a first layer of a metallization layer located on the VGD layer; a BV layer located below the AR layer; and a first buried metallization layer located below the VGD layer. It should be noted that Figure 1A the layer boundaries shown therein are approximate, particularly with respect to the boundary between the G&MD layer and the AR layer.

[0026] The AR layer includes active regions, and the active regions include source / drain (S / D) regions and a channel region located between the corresponding S / D regions. In some embodiments, the formation of the active regions includes: forming a semiconductor layer (e.g., a silicon layer) on a substrate, such as by epitaxy, to produce an epitaxial layer; typically, for example, by ion implantation, doping the selected regions of the semiconductor layer that will become the active regions with a p-type (P-type) or n-type (N-type) dopant, respectively; in a first portion of the selected regions that will become the S / D regions, doping the first portion relatively more heavily; and in the remaining regions of the semiconductor layer, i.e., the non-selected regions of the semiconductor layer, converting the remaining regions into insulating regions, such as forming shallow trench isolation (STI) regions. In the context of a field effect transistor (FET): p-type dopants are used for p-channel metal oxide semiconductor (PMOS) transistor technology, such as p-type FETs (PFETs); and n-type dopants are used for n-channel metal oxide semiconductor (NMOS) transistor technology, such as n-type FETs (NFETs). In the context of complementary metal oxide semiconductor (CMOS) transistor technology, the AR layer includes p-type active regions and n-type active regions. In some embodiments, the formation of the active regions further includes doping a second portion relatively more lightly in a second portion of the selected regions that will become the channel region.

[0027] In Figure 1A it, the G&MD layer includes MD contacts (discussed below) and / or gate lines / structures (discussed below), where G&MD is an abbreviation for gate and MD contacts, and MD is an abbreviation discussed below. In some embodiments, portions of the MD contacts extend at least substantially into the AR layer, as discussed below. The VGD layer includes a VG structure (discussed below) or a VD structure (discussed below).

[0028] The first layer of the metallization layer includes segments. In some embodiments, depending on the numbering convention of the corresponding process node for fabricating such a device, the first layer of the metallization layer is metallization layer zero (MET0) or metallization layer one (MET1), and if the metallization layer is via layer zero (VIA0) or via layer one (VIA1), then it is the first interconnect layer on the first layer accordingly. In Figure 1A And in other figures disclosed herein, the following nomenclature is adopted: Assume that the first layer of the metallization layer is MET0; assume that the first interconnect layer is VIA0; assume that the second layer of the metallization layer is MET1, assume that the second interconnect layer is VIA1; and assume that the third layer of the metallization layer is MET2. The metallization segments in layer MET0 are called M0 segments. The via structures in layer VIA0 are called V0 structures. The metallization segments in layer MET1 are called M1 segments. The via structures in layer VIA1 are called V1 structures. The metallization segments in layer MET2 are called M2 segments.

[0029] The BV layer includes buried via (BV) structures (discussed below). As discussed below, in some embodiments, portions of the BV structures extend at least substantially into the AR layer. The first buried layer of metallization includes metallization segments. Extending the nomenclature discussed above, the first buried layer of metallization is called BM0, and the metallization segments included in layer BM0 are called BMO segments.

[0030] In Figure 1A , device 100A includes: an example of AR 102 configured with a first dopant type; an example of AR 104 configured with a second dopant type; examples of ohmic contact (OC) layers 110 and 112; examples of dielectric structures and layers, including dielectric structures 118(1) and 118(2); MD contacts 106(1) and 106(2); BV structures 120(1) and 120(2); examples of M0 segments 124; examples of M0 segments 126; and BM0 segments 128(1) and 128(2). In some embodiments, MD is an abbreviation for metal to S / D or metal on S / D or metal above S / D. In some embodiments, MD is an abbreviation for metal on diffusion or metal above diffusion. MD contact 106(1) includes a first portion 108(1) and a second portion 108(2). MD contact 106(2) includes a first portion 108(3) and a second portion 108(4). BV structure 120(1) includes a first portion 122(1) and a second portion 122(2). BV structure 120(2) includes a first portion 122(3) and a second portion 122(4).

[0031] Figure 1AAssume that the first dopant is N-type and the second dopant is P-type, such that AR 102 is an N-type AR and AR 104 is a P-type AR. For simplicity of illustration, not all elements of device 100A are labeled with reference numerals. In some embodiments, one or more instances of each of OC layers 110 and 112 include corresponding silicide layers and the like.

[0032] In Figure 1A , relative to the Y-axis, the width of an instance of M0 segment 124 is substantially greater than the width of an instance of M0 segment 126. In some embodiments, the width of an instance of M0 segment 124 is approximately the same as the width of an instance of M0 segment 126. The pitch of an instance of M0 segment 124 is greater than the pitch of an instance of M0 segment 126. In some embodiments, the instances of M0 segment 124 are omitted (see Figure 1D ). In some embodiments, the instances of M0 segment 124 are power grid (PG) segments configured for corresponding reference voltages (e.g., VDD, VSS, etc.). In some embodiments, the instances of M0 segment 126 are configured for routing signals. Examples of routed signals include input / output (I / O) signals, data signals, control signals, etc.

[0033] The first instance of OC layer 110 is located on AR 102. The first part 108(1) of MD contact 106(1) is located on the first instance of OC layer 110. The first instance of OC layer 110 facilitates an electrical coupling between the first part 108(1) of MD contact 106(1) and AR 102. The second instance of OC layer 110 is located on AR 104. The first part 108(3) of MD contact 106(2) is located on the second instance of OC layer 110. The second instance of OC layer 110 facilitates an electrical coupling between the first part 108(3) of MD contact 106(2) and AR 104.

[0034] The first instance of OC layer 112 is located below AR 102. The first part 122(1) of BV structure 120(1) is located below the first instance of OC layer 112. The first instance of OC layer 112 facilitates an electrical coupling between the first part 122(1) of BV structure 120(1) and AR 102. The second instance of OC layer 112 is located below AR 104. The first part 122(3) of BV structure 120(2) is located below the second instance of OC layer 112. The second instance of OC layer 112 facilitates an electrical coupling between the first part 122(3) of BV structure 120(2) and AR 104.

[0035] In Figure 1AIn, the dielectric structure 118(1) is located on / against the first lateral side of the AR 102. Relative to the Y-axis, the second lateral side of the AR 102 is close to the AR 104, while the first side of the AR 102 is away from the AR 104. The dielectric structure 118(2) is located on / against the second lateral side of the AR 104. Relative to the Y-axis, the first lateral side of the AR 104 is close to the AR 102, while the second side of the AR 104 is away from the AR 102. In some embodiments, the lateral sides of the AR 102 or AR 104 are referred to as sides. In Figure 1A In, relative to the Y-axis, the first lateral side of each of the AR 102 and 104 is the left side, and the second lateral side of each of the AR 102 and 104 is the right side.

[0036] The dielectric structure 118(1) separates the second part 108(2) of the MD contact 106(1) from the left side of the AR 102. The bottom surface of the dielectric structure 118(1) is located on the first part of the second part 122(2) of the BV structure 120(1). The dielectric structure 118(2) separates the second part 108(4) of the MD contact 106(2) from the right side of the AR 104. The bottom surface of the dielectric structure 118(2) is located on the first part of the second part 122(3) of the BV structure 120(2).

[0037] Regarding the MD contact 106(1), the imaginary boundary between the second part 108(2) and the first part 108(1) is indicated by a dashed line. Relative to the Z-axis, the second part 108(2) of the MD contact 106(1) extends beside the left side of the AR 102. Relative to the Z-axis, the second part 108(2) of the MD contact 106(1) extends substantially into the AR layer. The lower end of the second part 108(2) of the MD contact 106(1) is located on the second part of the second part 122(2) of the BV structure 120(1). Thus, the second part 108(2) of the MD contact 106(1) is electrically coupled to the second part 122(2) of the BV structure 120(1).

[0038] Regarding Figure 1A, in some embodiments, the lower surface at the dorsal side of the AR 102 is substantially flat and substantially parallel to the X-Y plane. The upper surface of the first portion 122(1) of the BV structure 120(1) is substantially flat and substantially parallel to the lower surface of the AR 102. The upper surface of the second portion 122(2) of the BV structure 120(1) is substantially flat and substantially parallel to the X-Y plane. The upper surface of the second portion 122(2) of the BV structure 120(1) is also substantially coplanar with the upper surface of the first portion 122(1) of the BV structure 120(1). The lower surface of the lower end of the second portion 108(2) of the MD contact 106(1) is substantially flat and substantially parallel to the upper surface of the second portion 122(2) of the BV structure 120(1), which facilitates the electrical coupling between the lower end of the second portion 108(2) of the MD contact and the second portion 122(2) of the BV structure 120(1).

[0039] Regarding the MD contact 106(2), the imaginary boundary between the second portion 108(4) and the first portion 108(3) is indicated by a dashed line. Relative to the Z-axis, the second portion 108(4) of the MD contact 106(2) extends beside the right side of the AR 104. Relative to the Z-axis, the second portion 108(4) of the MD contact 106(2) extends substantially into the AR layer. The lower end of the second portion 108(4) of the MD contact 106(2) is located on the second portion of the second portion 122(4) of the BV structure 120(2). Thereby, the second portion 108(4) of the MD contact 106(2) is electrically coupled to the second portion 122(4) of the BV structure 120(2).

[0040] The BV structure 120(1) is located on the BM0 segment 128(1). The BV structure 120(2) is located on the BM0 segment 128(2). In some embodiments, the BM0 segment 128(1) or 128(2) is configured for a corresponding reference voltage, e.g., VDD, VSS, etc.

[0041] In Figure 1A , the first current path between the BV structure 120(1) and the AR 102 is from the first portion 122(1) of the BV structure 120(1) through the first instance of the OC layer 112 to the AR 102. The second portion 108(2) of the MD contact 106(1) facilitates the second current path between the BV structure 120(1) and the AR 102. The second current path between the BV structure 120(1) and the AR 102 is from the second portion 122(2) of the BV structure 120(1) through the second portion 108(2) of the MD contact 106(1) and a portion of the first instance of the OC layer 110 to the AR 102.

[0042] The resistance R_bs of the first current path is represented by the resistance R_OC112 across the first instance of the ohmic contact layer 112, such that R_bs≈R_OC112, where bs is an abbreviation for the back side. The resistance R_fs of the second current path is represented by the combination including: the resistance R_MDBV of the ohmic boundary between the second part 122(2) of the BV structure 120(1) and the second part 108(2) of the MD contact 106(1); the resistance R_MD of the second part 108(2) of the MD contact 106(1); and the resistance R_OC110 across the part of the first instance of the ohmic contact layer 110. Thus, R_fs≈R_MDBV+R_MD+R_OC110, where fs is an abbreviation for the front side.

[0043] The first and second current paths between the BV structure 120(1) and the AR 102 are in parallel, which reduces the total resistance R_BVAR102A between the BV structure 120(1) and the AR 102 of the device 100A. Generally, two parallel resistors R1 and R2 have an equivalent total resistance R_tot, as follows: R_tot=(R1*R2) / (R1+R2). The total resistance between the BV structure 120(1) and the AR 102 of the device 100A is expressed as R_BVAR102A=(R_bs*R_fs) / (R_bs+R_fs). In some embodiments, by way of example, R_MDBV≈0.2*R_bs, R_MD≈0.2*R_bs, and R_OC110≈0.5*R_bs, such that R_fs≈(0.2+0.2+0.5)*R_bs≈0.9*R_bs and R_BVAR102A≈0.5*R_bs.

[0044] In Figure 1A the first current path between the BV structure 120(2) and the AR 104 is from the first part 122(3) of the BV structure 120(2) through the second instance of the OC layer 112 to the AR 104. The second part 108(4) of the MD contact 106(2) facilitates the second current path between the BV structure 120(2) and the AR 104. The second current path between the BV structure 120(2) and the AR 104 is from the second part 122(4) of the BV structure 120(2) through the second part 108(4) of the MD contact 106(2) and the part of the second instance of the OC layer 110 to the AR 104. The expression of the total resistance R_BVAR104A between the BV structure 120(2) and the AR 104 of the device 100A is similar to the expression of R_BVAR102A, such that R_BVAR1104A≈0.5*R_bs.

[0045] According to another method, the device corresponding to device 100A includes an MD contact corresponding to MD contact 106(1), an active region corresponding to AR 102, and a BV structure corresponding to the first part 122(1) of BV structure 120(1). With respect to the Y-axis, the BV structure according to another method does not significantly extend beyond the active region according to another method. Thus, there is only one current path between the counterpart of AR 102 according to another method and the BV structure 120(1) of device 100A for the device counterpart according to another method, such that the total resistance between the counterpart of AR 102 according to another method and the first part 122(1) of BV structure 120(1) is denoted as R_bs, which results in another method experiencing higher energy consumption, e.g., due to greater resistive losses, etc. In contrast, device 100A (or other such embodiments disclosed herein) has a significantly lower resistance between BV structure 120(1) and AR 102, i.e., R_BVAR102A ≈ 0.5*R_bs, and a significantly lower resistance between BV structure 20(2) and AR 104, i.e., R_BVAR104A ≈ 0.5*R_bs, such that device 100A (etc.) has reduced energy consumption compared to other methods, e.g., due to reduced resistive losses, etc.

[0046] Figure 1B is a cross-sectional view of device 100B according to some embodiments.

[0047] Device 100B is an example of a device having an MD contact and a BV structure coupled to an active region. Device 100B is an example of a device having a WA_MD contact. Figure 1B Device 100B of Figure 1A is similar to Figure 2A device 100A. For the sake of brevity, the discussion will focus on the differences between device 100B and device 100A rather than the similarities. In some embodiments, device 100B is an example of a device corresponding to the cross-section line I.A-I.A’ of

[0048] Compared with Figure 1A device 100A of Figure 1B device 100B also includes a first instance of OC layer 114 and a first instance of OC layer 116. In device 100B, the first instance of OC layer 114 and the first instance of OC layer 116 correspondingly replace the dielectric structures 118(1) and 118(2) of device 100A. OC layer 114 is located on the left side of AR 102 / against the left side of AR 102. OC layer 116 is located on the second lateral side on the right side of AR 104 / against the second lateral side on the right side of AR 104. In some embodiments, one or more instances of each of OC layers 114 and 116 include corresponding silicide layers, etc.

[0049] In Figure 1B it, the first instance of the OC layer 114 facilitates a third current path between the BV structure 120(1) and the AR 102. The third current path between the BV structure 120(1) and the AR 102 is from the second part 122(2) of the BV structure 120(1), through the second part 108(2) of the MD contact 106(1) and the first instance of the OC layer 114 to the AR 102. The difference between the second current path and the third current path between the BV structure 120(1) and the AR 102 is that the former includes the first instance of the OC layer 110, while the latter includes the first instance of the OC layer 114.

[0050] The first instance of the OC layer 116 facilitates a third current path between the BV structure 120(2) and the AR 104. The third current path between the BV structure 120(2) and the AR 104 is from the second part 122(4) of the BV structure 120(2), through the second part 108(4) of the MD contact 106(2) and the first instance of the OC layer 116 to the AR 104. The difference between the second current path and the third current path between the BV structure 120(2) and the AR 104 is that the former includes the second instance of the OC layer 110, while the latter includes the first instance of the OC layer 116.

[0051] The resistance R_ls of the third current path is represented by a combination including the following: R_MDBV; R_MD; and the resistance R_OC114 across the first instance of the OC layer 114. Thus, R_ls≈R_MDBV + R_MD + R_OC114, where ls is an abbreviation for the lateral side.

[0052] The second current path and the third current path between the BV structure 120(1) and the AR 102 are effectively in parallel with each other, and each current path is in parallel with the first current path between the BV structure 120(1) and the AR 102, which reduces the total resistance R_BVAR102B between the BV structure 120(1) and the AR 102 of the device 100B. The total resistance between the BV structure 120(1) and the AR 102 of the device 100B is expressed as R_BVAR102B=(R_bs*R_fs*R_ls) / (R_bs + R_fs + R_ls).

[0053] With respect to the major axis of each, typically, the length of the first instance of the OC layer 116 is greater than the length of the portion of the first instance of the ohmic contact layer 110 represented by R_OC110. In some embodiments, with respect to the minor axis of each, typically, the thickness of the first instance of the OC layer 116 is approximately equal to the thickness of the portion of the first instance of the ohmic contact layer 110 represented by R_OC110. Thus, in some embodiments, R_OC114 ≤ R_OC110. Extended Figure 1A example, and further assume that for example R_OC114 ≈ R_OC110, such that R_OC114 ≈ 0.5 * R_bs, then R_BVAR102D ≈ 0.3 * R_bs.

[0054] Device 100B (or other such embodiments disclosed herein) has a significantly lower resistance between the BV structure 120(1) and the AR 102, i.e., R_BVAR102B ≈ 0.3 * R_bs, and has a significantly lower resistance between the BV structure 20(2) and the AR 104, i.e., R_BVAR104B ≈ 0.3m * R_bs, such that the power consumption of device 100B (etc.) is reduced compared to other methods, for example due to reduced resistive losses, etc.

[0055] Figure 1C is a cross-sectional view of a device 100C according to some embodiments.

[0056] Device 100C is an example of a device having an MD contact and a BV structure coupled to an active region. Device 100C is an example of a device having a WA_MD contact. Figure 1C The device 100C of Figure 1B is similar to the device 100B of Figure 2A . For the sake of brevity, the discussion will focus on the differences between device 100C and device 100B rather than the similarities. In some embodiments, device 100C is an example of a device corresponding to the cross-section line I.A - I.A' of

[0057] Compared with Figure 1B the device 100B of Figure 1C the device 100C of Figure 1C also includes a third portion 122(3) of the BV structure 120(1), resulting in an enlarged version of the BV structure 120(1). Figure 1C The enlarged version of the BV structure 120(1) in Figure 1B is given the reference numeral 120(3) in Figure 1C The version of the first part 108(1) in Figure 1C and the truncated version of the MD contact 106(1) are correspondingly assigned the reference numerals 108(5) and 106(3) in

[0058] The third part 122(3) of the BV structure 120(3) is located below the first part 108(5) of the MD contact 106(3) and is coupled to the first part 108(5) of the MD contact 106(3). Relative to the Z-axis, the third part 122(3) of the BV structure 120(3) extends beside the left side of the AR 102. The third part 122(3) of the BV structure 120(3) is located on / against the OC layer 114. Thus, the third part 122(3) of the BV structure 120(3) is electrically coupled to the first part 108(5) of the MD contact 106(3) and the AR 102, the latter through the first instance of the OC layer 114. In some embodiments, the boundary between the third part 122(3) of the BV structure 120(3) and the first part 108(5) of the MD contact 106(3) approximates Figure 1B the imaginary boundary between the second part 108(2) and the first part 108(1) of the MD contact 106(1) in

[0059] In some embodiments, the corresponding upper and lower surfaces at the front and back sides of the AR 102 are substantially flat and substantially parallel to the X-Y plane. Relative to the Z-axis: the third part 122(3) of the BV structure 120(3) substantially extends above the lower surface of the AR(102); the third part 122(3) of the BV structure 120(3) substantially extends into the AR layer; the portion of the first part 108(5) of the MD contact 106(3) adjacent to the upper end of the BV structure 120(3) significantly extends below the uppermost surface of the MD contact 106(1); and the first part 108(5) of the MD contact 106(3) significantly extends into the AR layer.

[0060] As with Figure 1B the second part 108(2) of the MD contact 106(1) in Figure 1C the third part 122(3) of the BV structure 120(3) in Figure 1C facilitates a third current path between the BV structure 120(3) and the AR 102 in the device 100C of Figure 1BThe third current path in device 100B is different in that the former includes the third part 122(3) of the BV structure 120(3), while the latter includes the second part 108(2) of the MD contact 106(1).

[0061] In some embodiments, Figure 1C the resistance R_BV of the third part 122(3) of the BV structure 120(3) in Figure 1B is approximately equal to the resistance R_MD of the second part 108(2) of the MD contact 106(1) in

[0062] such that R_BV≈R_MD. In these embodiments, the total resistance R_BVAR102C between the BV structure 120(3) and the AR 102 of device 100C is approximately equal to the total resistance R_BVAR102B between the BV structure 120(1) and the AR 102 of device 100B, such that R_BVAR102C = R_BVAR102B≈0.3*R_bs.

[0063] Figure 1D is a cross-sectional view of a device 100D according to some embodiments.

[0064] Device 100D is an example of a device having an MD contact and a BV structure coupled to an active region. Device 100D is an example of a device having a WA_MD contact. Figure 1D The device 100D of Figure 1A is similar to the device 100A of Figure 2A For the sake of brevity, the discussion will focus on the differences between device 100D and device 100A rather than the similarities. In some embodiments, device 100D is an example of a device corresponding to the cross-section line I.A-I.A' of

[0065] In Figure 1D the instances of the M0 segment 124 of Figure 1A are omitted. Additionally, Figure 1D the width of the instances of the M0 segment 126 in Figure 1A is greater than the width of the instances of the M0 segment 126 in Figure 1D The pitch of the instances of the M0 segment 126 in Figure 1AThe pitch of an example of the M0 segment 126 in. In some embodiments, compared to another method, the device 100D experiences an increased M0 pitch that is greater than or equal to an improvement of about 20%.

[0066] Figure 1E is a cross-sectional view of a device 100E according to some embodiments.

[0067] Device 100E is an example of a device having an MD contact and a BV structure coupled to an active region. Device 100E is an example of a device having a WA_MD contact. Figure 1E The device 100E of Figure 1A is similar to the device 100A of Figure 2B For the sake of brevity, the discussion will focus on the differences between device 100E and device 100A rather than the similarities. In some embodiments, device 100E is the device corresponding to the cross-sectional line I.E-I.E’ of

[0068] Compared with Figure 1A the device 100A of Figure 1E the device 100E of

[0069] also includes: examples of dielectric structures and layers, including dielectric structures 118(3) and 118(4); MD contact 106(4); BV structure 120(4); and BM0 segments 128(3) and 128(4). Device 100E does not include MD contacts 106(1) and 106(2), BV structures 120(1)-120(2), nor the BM0 segments 128(1)-128(2) of device 100A.

[0070] MD contact 106(4) includes a first portion 108(6), a second portion 108(7), and a third portion 108(8). Dielectric structure 118(3) is located on the right side of or against the right side of AR 102. Dielectric structure 118(4) is located on the left side of / against the left side of AR 104. BV structure 120(4) includes a first portion 122(4) and a second portion 122(5).

[0071] Regarding the MD contact 106(4): (A) The first imaginary boundary between the third part 108(8) and (B) the first part 108(6) and the second part 108(7) is represented by a dashed line that is substantially parallel to the X-axis; the second imaginary boundary between the first part 108(6) and the second part 108(7) is represented by a dashed line that is substantially parallel to the Z-axis.

[0072] Relative to the Z-axis, the third part 108(8) of the MD contact 106(4) extends beside the right side of the AR 102 and the left side of the AR 104. Relative to the Z-axis, the third part 108(8) of the MD contact 106(4) extends substantially into the AR layer. The lower end of the third part 108(8) of the MD contact 106(4) is located on the second part of the second part 122(5) of the BV structure 120(4). Thereby, the third part 108(8) of the MD contact 106(4) is electrically coupled to the second part 122(5) of the BV structure 120(4).

[0073] In some embodiments, the lower surface of the dorsal side of the AR 102 is substantially flat and substantially parallel to the X-Y plane. The upper surface of the first part 122(4) of the BV structure 120(4) is substantially flat and substantially parallel to the lower surface of the AR 102. The upper surface of the second part 122(5) of the BV structure 120(4) is substantially flat and substantially parallel to the X-Y plane. The upper surface of the second part 122(5) of the BV structure 120(4) is also substantially coplanar with the upper surface of the first part 122(4) of the BV structure 120(4). The lower surface of the lower end of the third part 108(8) of the MD contact 106(4) is substantially flat and substantially parallel to the upper surface of the second part 122(5) of the BV structure 120(4), which facilitates the electrical coupling between the lower end of the third part 108(8) of the MD contact and the second part 122(5) of the BV structure 120(4).

[0074] Most of the first part 122(4) of the BV structure 120(4) is located on the BM0 segment 128(3). In some embodiments, the BM0 segment 128(3) or 128(2) is configured for a corresponding reference voltage, such as VDD, VSS, etc.

[0075] In Figure 1EIn [the figure], the third part 108(8) of the MD contact 106(4) facilitates a second current path between the BV structure 120(4) and the AR 102 and a first current path between the BV structure 120(4) and the AR 104. The first current path between the BV structure 120(4) and the AR 102 is from the first part 122(4) of the BV structure 120(4), through the first instance of the OC layer 112, to the AR 102. The second current path between the BV structure 120(4) and the AR 102 is from the second part 122(5) of the BV structure 120(4), through the third part 108(8) of the MD contact 106(4) and the first instance of the OC layer 110, to the AR 102. The first current path between the BV structure 120(4) and the AR 104 is from the first part 122(4) of the BV structure 120(4), through the second instance of the OC layer 112, to the AR 104.

[0076] According to another method, a device corresponding to the device 100E includes an MD contact corresponding to the MD contact 106(4), an active region corresponding to the AR 102, and a BV structure corresponding to the first part 122(4) of the BV structure 120(4). Relative to the Y-axis, the BV structure according to another method does not significantly extend beyond the active region according to another method. The device counterpart according to another method has only one current path between the counterpart of the AR 102 according to another method and the first part 122(4) of the BV structure 120(4) of the device 100E, such that the total resistance between the counterpart of the AR 102 according to another method and the BV structure 120(4) is represented as R_bs, which results in another method experiencing higher energy consumption, for example, due to greater resistance losses, etc. In contrast, due to the first and second current paths between the BV structure 120(4) and the AR 102 and the first current path between the BV structure 120(4) and the AR 104, the device 100E (or other such embodiments disclosed herein) has significantly lower resistance, such that the energy consumption of the device 100E (etc.) is reduced compared to other methods, for example, due to reduced resistance losses, etc.

[0077] Figure 1F is a cross-sectional view of a device 100F according to some embodiments.

[0078] The device 100F is an example of a device having an MD contact and a BV structure coupled to an active region. The device 100F is an example of a device having a WA_MD contact. Figure 1F The device 100F is similar to Figure 1E The device 100E. For the sake of brevity, the discussion will focus on the differences between the device 100F and the device 100E rather than the similarities. In some embodiments, the device 100F is related to Figure 2BAn example of a device corresponding to the cross - hatch line I.E - I.E'.

[0079] Compared with Figure 1E device 100E, Figure 1F device 100F further includes examples of OC layer 114 and examples of OC layer 116. In device 100F, the examples of OC layer 114 and the examples of OC layer 116 correspondingly replace the dielectric structures 118(3) and 118(4) of device 100E. In Figure 1F , the example of OC layer 114 is located on the left side of or against the left side of AR 104. The example of OC layer 116 is located on the right side of or against the right side of AR 102.

[0080] In Figure 1F , the example of OC layer 116 facilitates a third current path between BV structure 120(4) and AR 102. The current path between BV structure 120(4) and AR 102 is from the second part 122(5) of BV structure 120(4), through the third part 108(8) of MD contact 106(4) and the example of OC layer 116 to AR 102.

[0081] The example of OC layer 114 facilitates a second current path between BV structure 120(4) and AR 104. The second current path between BV structure 120(4) and AR 104 is from the second part 122(5) of BV structure 120 through the third part 108(8) of MD contact 106(4) and the example of OC layer 114 to AR 104.

[0082] According to another method, the device corresponding to device 100E includes an MD contact corresponding to MD contact 106(4), an active region corresponding to AR 102, and a BV structure corresponding to the first part 122(4) of BV structure 120(4). Relative to the Y-axis, the BV structure according to another method does not significantly extend beyond the active region according to another method. There is only one current path between the counterpart of AR 102 according to another method and the first part 122(4) of the BV structure 120(4) of device 100F for the device counterpart according to another method, such that the total resistance between the counterpart of AR 102 according to another method and the BV structure 120(4) is represented as R_bs, which results in another method experiencing higher energy consumption, e.g., due to greater resistive losses, etc. In contrast, due to the first current path, the second current path, and the third current path between BV structure 120(4) and AR 102, and the first current path and the second current path between BV structure 120(4) and AR 104, device 100F (or other such embodiments disclosed herein) has significantly lower resistance, such that the energy consumption of device 100E (etc.) is reduced compared to another method, e.g., due to reduced resistive losses, etc.

[0083] Figure 2A is a layout diagram of device 200A according to some embodiments.

[0084] Device 200A is an example of a device having an MD contact and a BV structure coupled to an active region. Device 200A is an example of a device having a WA_MD contact.

[0085] In Figure 2A , device 200A is an inverter. Inverter 200A is an example of a D4 inverter (INVD4) inverter. The text string D4 is an abbreviation, where D is a unit of drive strength. Thus, the abbreviation D4 indicates that the cell region corresponding to inverter 200A has a current drive / source strength of 4D. In some embodiments, the value of the unit drive strength D is determined by, for example, the design rules and scaling of the corresponding semiconductor process technology node.

[0086] Figure 2A The layout diagram of represents a transistor-based device. The structures in the device are represented by patterns (also called shapes) in the layout diagram. For the sake of simplicity in discussion, Figure 2A the elements in the layout diagram (and other layout diagrams disclosed herein) will be referred to as structures rather than the patterns themselves. For example, Figure 2A the instance of 238 in represents an instance of a VD structure. In the following discussion, the instance of element 238 is referred to as an instance of VD structure 238 rather than an instance of VD pattern 238.

[0087] In Figure 2AIn it, the section line IA - IA’ extends parallel to the Y-axis. In some embodiments, Figure 2A the section line I.A - I.A’ corresponds to Figure 1A the cross-section of Figure 2A the section line I.A - I.A’ corresponds to Figure 1B the cross-section of Figure 2A the section line I.A - I.A’ corresponds to Figure 1C the cross-section of Figure 2A the section line I.A - I.A’ corresponds to Figure 1D the cross-section of

[0088] In Figure 2A and other layout diagrams disclosed herein, an orthogonal Cartesian coordinate system is assumed, where the first direction, the second direction, and the third direction are, for example, parallel to the X-axis, the Y-axis, and the Z-axis, respectively. The layout diagram itself is a top view. The shapes in the layout diagram are two-dimensional with respect to, for example, the X-axis and the Y-axis, while the represented device is three-dimensional. Thus, the shapes in such a layout diagram are described as having a width / length with respect to the X-axis and a height with respect to the Y-axis. With respect to the Z-axis, for example, the bottom / back side of the first component represented in the layout diagram is stacked on the top / front side of the second component device represented in the layout diagram, or the top / front side of the first component is stacked below the bottom / back side of the second component, for example. In some embodiments, the first direction to the third direction correspond to directions other than the X-axis, the Y-axis, and the Z-axis.

[0089] Generally, with respect to the Z-axis, the device is organized as a stack of layers, where there are corresponding structures, that is, the corresponding structures belong to the stack of layers. Each shape in the layout diagram more specifically represents a component in the corresponding layer of the corresponding device. Furthermore, generally, by superimposing a second shape on a first shape such that the second shape at least partially overlaps the first shape, the layout diagram represents the relative depth of the shape and the corresponding layer, that is, the position along the Z-axis. For the sake of simplicity, a second-level stack along the Z-axis (i.e., a different / twisted stacking order) is used in the layout diagram to represent some structures in the device that have a first-level stack along the Z-axis. For example, in Figure 2A it, the BV structure 220(1) is shown as being located above the AR 204, and correspondingly, the BV structure 120(1) is located below the AR 104 in Figure 1A it.

[0090] Layout diagrams vary in the amount of detail represented. In some cases, the select layers of a layout diagram are combined / abstracted into a single layer, e.g., for simplicity. Optionally and / or additionally, in some cases, not all layers corresponding to the device are represented, i.e., for example, the select layers of the layout diagram are omitted for simplicity of illustration. Optionally and / or additionally, in some cases, not all elements of a given depicted layer of the layout diagram are represented, i.e., for example, the select elements of a given depicted layer of the layout diagram are omitted for simplicity of illustration. Figure 2A And the other layout diagrams disclosed herein are examples of layout diagrams in which the select layers and / or select elements of a given shown layer are omitted. For example, Figure 2A instances of the OC layer 110, instances of the OC layer 112, etc. are omitted. In some embodiments, Figure 2A the layout diagram is part of a larger layout diagram.

[0091] In Figure 2A the inverter 200A includes: an instance of an N-type AR 202; an instance of a P-type AR 204; instances of gate lines / structures 230 and 232; MD contacts including MD contact 206(1) and MD contact 216(2); an instance of a VG structure 236; an instance of a VD structure 238; M0 segments 226(1) and 226(2); an instance of a V0 structure 240; M1 segments 242(1) and 242(2); a BV structure including BV structures 220(1) and 220(2); and BM0 segments 228(1) and 228(2). With respect to the inverter 200A, the M1 segment 242(1) represents the input node I. The M1 segment 242(2) represents the output node ZN.

[0092] For simplicity, Figure 2A not all components in Figure 2A are labeled with reference numerals. For example, Figure 2A the MD contacts in

[0093] In Figure 2A are not labeled with reference numerals other than MD contacts 206(2) and 206(1). Similarly for example, other than BV structures 220(1) and 220(2),

[0094] In some embodiments, the IDG is a dielectric structure that includes one or more dielectric materials and serves as an electrical isolation structure. Thus, the IDG is not a conductive structure and thus does not serve as an active gate of, for example, a transistor. The IDG includes one or more dielectric materials and serves as an electrical isolation structure. In some embodiments, the IDG is based on a gate line / structure as a precursor. In some embodiments, the method of forming the IDG includes: forming a gate line / structure; sacrificing / removing (e.g., etching) the gate line / structure to form a trench that is at least partially around a corresponding portion of the active region; (optionally) removing a portion or all of the corresponding active region that was previously adjacent to the gate line / structure to deepen the trench and thereby partially or completely divide the corresponding active region into a corresponding left or right side that extends beyond the unit region relative to the X-axis; and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrical isolation structure (i.e., the IDG) are similar to the dimensions of the sacrificed gate line / structure. In some embodiments, the IDG is a dielectric component that includes one or more dielectric materials (e.g., oxides, nitrides, oxynitrides, or other suitable materials) and serves as an isolation component. In some embodiments, the IDG is a continuous polysilicon on an oxide diffusion (OD) edge structure and is referred to as a CPODE structure.

[0095] Figure 2B is a layout diagram of a device 200B according to some embodiments.

[0096] Device 200B is an example of a device having an MD contact and a BV structure coupled to an active region. Device 200B is an example of a device having a WA_MD contact.

[0097] Device 200B is an inverter. Figure 2B The inverter 200B of Figure 2A is similar to the inverter 200A of Figure 2B For simplicity, the discussion will focus on the differences between inverter 200B and inverter 200A rather than the similarities. In some embodiments, inverter 200B is an example of a device corresponding to the cross-section line I.E-I.E' of

[0098] In Figure 2BIn [circuit], the inverter 200B includes: an example of an N-type AR 202; an example of a P-type AR 204; examples of gate lines / structures 230 and 232; an MD contact including the MD contact 206(4); an example of a VG structure 236; an example of a VD structure 238; an M0 segment 226(3); an example of a V0 structure 240; an M1 segment 242(3); a BV structure including the BV structure 220(4); and BM0 segments 228(3) and 228(4). Regarding the inverter 200B, the M1 segment 242(3) represents the input node I. The BM0 segment 228(3) represents the output node ZN.

[0099] For simplicity, Figure 2B not all components in [circuit] are labeled with reference numbers. For example, Figure 2B the MD contacts in [circuit] are not labeled with reference numbers except for the MD contact 206(4). Similarly for example, Figure 2B the BV structures in [circuit] are not labeled with reference numbers except for the BV structure 220(4).

[0100] In Figure 2B [circuit], the gate line / structure 232 is aligned with the left and right boundaries of the inverter 200B, respectively. In some embodiments, the gate line / structure 232 is replaced by a corresponding isolation dummy gate (IDG) discussed below. Although in Figure 2A [circuit] each of the inputs I and ZN is located on the front side of the inverter 200A, in Figure 2B [circuit], the input I and ZD are located on the front side and the back side of the inverter 200B, respectively.

[0101] Figure 3A is a schematic diagram 344 according to some embodiments.

[0102] The schematic diagram 344 assumes reference voltages VDD and VSS, etc. In Figure 3A [circuit], the non-switching PG line configured for VDD is labeled TVDD, and the switching line configured for VDD is labeled VVVD. In some embodiments, TVDD is an abbreviation of the true VDD. In some embodiments, VVDD is an abbreviation of a pseudo VDD.

[0103] The schematic diagram 344 includes a head circuit 346A and a sleep circuit 348. The head circuit 346A includes an inverter 350(1) and PFETs P1, P2, and P3. The inverter 350(1) is coupled between a gate bias voltage and VSS. The inverter 350(1) is configured to receive a sleep signal VSLEEPIN and generate an inverted version SLP of the signal. The PFETs P1, P2, and P3 are coupled in parallel between the TVDD PG line and the VVDD PG line and are configured to receive the signal SLP at their gates.

[0104] The sleep circuit 348 includes inverters 350(2), 350(3), and 350(4). The inverters 350(2), 350(3), and 350(4) are coupled in parallel between the VVDD PG line and VSS. The inverter 350(2) is coupled to receive VVDD. The output of the inverter 350(2) is coupled to the input of the inverter 350(3). The output of the inverter 350(3) is coupled to the input of the inverter 350(4). In some embodiments, the circuit 348 is referred to as a sleep circuit because, in effect, the voltage on the VVDD PG line is selectively turned off or on by the head circuit 346A, such that the circuit 348 is placed in a sleep or wake state by the head circuit 346A accordingly. When placed in the sleep state, the circuit 348 exhibits reduced leakage current.

[0105] Figure 3B is a layout diagram of the device 346B according to some embodiments.

[0106] The device 346B is an example of a device having an MD contact and a BV structure coupled to an active region. The device 346B is an example of a device having a WA_MD contact.

[0107] The device 346B represents the head circuit. In some embodiments, Figure 3B the head circuit 346B corresponds to Figure 3A the head circuit 346A. A portion of the head circuit 346B is shown in the exploded view 352.

[0108] FIG. 3C to FIG. 3D is a layout diagram of the corresponding devices 346C and 346D according to some embodiments.

[0109] Each of the devices 346C and 346D is an example of a device having an MD contact and a BV structure coupled to an active region. Each of the devices 346C and 346D is an example of a device having a WA_MD contact.

[0110] Each of the devices 346C and 346D represents the corresponding head circuit. Each of the head circuits 346C and 346D is similar to Figure 3B the exploded view 352 of the head circuit 346B. For the sake of brevity, the discussion will focus on the differences between each of the head circuits 346C and 346D and Figure 3B the exploded view 352 of the head circuit 346B, rather than the similarities.

[0111] In some embodiments, Figure 3C the cross-hatching IV.A-IV.A' in Figure 4A corresponds to the head circuit 446A. In some embodiments, Figure 3C the cross-hatching IV.B-IV.B' in Figure 4B The head circuit 446B. In some embodiments, Figure 3D The cross - hatch IV.C - IV.C’ in Figure 4C corresponds to the head circuit 446C.

[0112] FIG. 3C to FIG. 3D Each of those in

[0113] In Figure 3C each MD contact extends through all three ARs with respect to the Y - axis. Each BV structure is correspondingly located below and coupled to a respective one of the odd - numbered instances of the MD contacts. With respect to the Y - axis, the length of the BV structure is substantially the same as the length of the MD contact. There is no other corresponding BV structure below the even - numbered instances of the MD contacts.

[0114] In Figure 3D each MD contact extends through all three ARs with respect to the Y - axis. Each BV structure is correspondingly located below and coupled to a respective one of the odd - numbered instances of the MD contacts. With respect to the Y - axis, the length of each BV structure is sufficient to extend significantly beyond the top and bottom boundaries of the corresponding odd - numbered MD contact and also not to protrude from under any other MD contact. There is no other corresponding BV structure below the even - numbered instances of the MD contacts.

[0115] Figure 4A is a cross - sectional view of a device 400A according to some embodiments.

[0116] Device 400A is an example of a device having MD contacts and BV structures coupled to an active region. Device 400A is an example of a device having WA_MD contacts.

[0117] Figure 4A The device 400A in Figure 1E is similar to the device 100E in Figure 3C For the sake of brevity, the discussion will focus on the differences between device 400A and device 400E rather than the similarities. In some embodiments, device 400A is an example of a device corresponding to the cross - hatch IV.A - IV.A’ in Figure 4A Note that, from the perspective of the Y - axis, for simplicity of illustration, Figure 3C the relative width of the AR 402(1) in

[0118] Figure 4AThe device 400A includes: an N-type AR 402(1) and P-type ARs 404(1) and 404(2); examples of OC layers 410 and 412; examples of dielectric structures and layers, including dielectric structure 418; an MD contact 406(5); a BV structure 420(5); and a BM0 segment 428(5). In some embodiments, the example of dielectric structure 418 is replaced by a corresponding example of OC layer 114 and an example of OC layer 116.

[0119] The MD contact 406(5) includes portions 408(11)-408(16). Portion 408(11) is located on AR 404(1). Portion 408(12) is located on AR 402(1). Portion 408(13) is located on AR 404(2). Portion 408(14) is located between AR 404(1) and AR 402(1). Portion 408(15) is located between AR 402(1) and AR 404(2). Portion 408(16) is located to the right of AR 404(2).

[0120] The BV structure 420(5) includes portions 422(11)-422(16). Portion 422(11) is located below AR 404(1). Portion 422(12) is located below portion 408(14) of the MD contact 406(5). Portion 422(13) is located below AR 402(1). Portion 422(14) is located below portion 408(15) of the MD contact 406(5). Portion 422(15) is located below AR 404(2). Portion 422(16) is located below portion 408(16) of the MD contact 406(5).

[0121] Figure 4B is a cross-sectional view of a device 400B according to some embodiments.

[0122] Device 400B is an example of a device having an MD contact and a BV structure coupled to an active region. Device 400B is an example of a device having a WA_MD contact.

[0123] Figure 4B The device 400B is similar to Figure 4A the device 400A. For the sake of brevity, the discussion will focus on the differences between device 400B and device 400A rather than the similarities. In some embodiments, device 400B is an example of a device corresponding to Figure 3C the cross-sectional line IV.B-IV.B’; from the perspective of the Y-axis, note that, for simplicity of illustration, Figure 4B the relative width of AR 402(1) in Figure 3C is narrower than the relative width of the middle AR in

[0124] Compared with Figure 4A device 400A, Figure 4B device 400B further includes examples of OC layer 114 and OC layer 116. In device 400B, the examples of OC layer 414 and OC layer 416 correspondingly replace the dielectric structure 418 of device 400A. The example of OC layer 414 is correspondingly located on the left side of or against the left side of AR 402(1) and AR 404(2). The example of OC layer 416 is correspondingly located on the right side of or against the right side of each of AR 404(1), AR 402(1) and AR 404(2).

[0125] Compared with Figure 4A device 400A, Figure 4B device 400B further includes parts 408(14)-418(16) of BV structure 420(5), resulting in an enlarged version of BV structure 420(5). Figure 4A The enlarged version of BV structure 420(5) in Figure 4B is given the reference numeral 420(6). In device 400B, in terms of occupied space, parts 422(17)-422(19) of BV structure 420(6) effectively replace the corresponding parts 408(14)-408(16) of Figure 4A MD contact 406(5), resulting in a truncated version of MD contact 406. Figure 4B The truncated version of MD contact 406(5) in Figure 4B is assigned the reference numeral 406(6).

[0126] In Figure 4B the examples of OC layer 414 facilitate additional corresponding current paths between BV structure 420(6) and AR 404(1), 402(1) and 404(2). The examples of OC layer 416 facilitate additional corresponding current paths between BV structure 420(5) and AR 404(1), 402(1) and 404(2).

[0127] Figure 4C is a cross-sectional view of device 400C according to some embodiments.

[0128] Device 400C is an example of a device having an MD contact and a BV structure coupled to an active region. Device 400C is an example of a device having a WA_MD contact.

[0129] Figure 4C Device 400C is similar to Figure 1CDevice 100C. For the sake of brevity, the discussion will focus on the differences between device 400C and device 100C rather than the similarities. In some embodiments, device 400C is an example of a device corresponding to the cross-section line IV.C-IV.C’ of Figure 3D the device.

[0130] Figure 4C Device 400C includes: N-type AR 402(3); P-type AR 404(3); examples of dielectric structures and layers; an example of OC layer 414; an example of OC layer 416; MD contact 406(7); BV structures 420(7) and 420(8); and BM0 segments 428(6) and 428(7). MD contact 406(7) includes portions 408(21)-408(23). BV structure 420(7) includes portions 422(21)-422(25). BV structure 420(8) includes portions 422(26)-422(28).

[0131] Regarding MD contact 406(7), most of portion 408(21) is located on AR 402(3) and is coupled to AR 402(3) through an example of OC layer 410. Most of portion 408(22) is located on AR 404(3) and is coupled to AR 404(3) through an example of OC layer 410. Portion 408(23) is located between AR 402(3) and AR 404(3). The right side of portion 408(21) abuts the left side of portion 408(22). The lower left portion of portion 408(21) is located on and coupled to portion 422(24) of BV structure 420(7). The lower right portion of portion 408(21) is located on and coupled to portion 408(23). The lower left portion of portion 408(22) is located on and coupled to portion 408(23). A portion of portion 408(23) abuts AR 402(3) and is coupled to AR 402(3) through an example of OC layer 416. A portion of portion 408(23) is coupled to portion 422(25) of BV structure 420(7). A portion of portion 408(23) abuts AR 404(3) and is coupled to AR 404(3) through an example of OC layer 414.

[0132] Regarding BV structure 420(7), portion 422(24) abuts against AR 402(3) and is coupled to AR 402(3) through an instance of OC layer 414. Portion 422(22) is located below AR 402(3) and is coupled to AR 402(3) through an instance of OC layer 412. The left side of portion 422(22) abuts against the right side of portion 422(21). Portion 422(24) is located on portion 422(21). The right side of portion 422(2) abuts against the left side of portion 422(23). Portion 422(25) is located on portion 422(23).

[0133] Regarding BV structure 420(8), portion 422(26) is located below AR 404(3) and is coupled to AR 404(3) through an instance of OC layer 412. The right side of portion 422(26) abuts against the left side of portion 422(27). Portion 422(28) is located on portion 422(27). Portion 422(28) abuts against AR 404(3) and is coupled to AR 404(3) through an instance of OC layer 416.

[0134] Figure 5A is a layout diagram of device 500A according to some embodiments.

[0135] Device 500A is a circuit arrangement including feed-through via (FTV) 501A. In Figure 5A , the cross-hatch line VI.A-VI.A’ extends parallel to the Y-axis. In some embodiments, Figure 5A the cross-hatch line VI.A-VI.A’ of Fig. 6A corresponds to the cross-section of Figure 5A . In Figure 5A , the cross-hatch line VI.B-VI.B’ extends parallel to the Y-axis. In Figure 5A , the cross-hatch line VI.B-VI.B’ extends parallel to the X-axis. In some embodiments, Figure 6B the cross-hatch line VI.B-VI.B’ of Figure 5A corresponds to the cross-section of Figure 5A the cross-hatch line VI.B-VI.B’ of Figure 6C corresponds to the cross-section of

[0136] Device 500A includes: N-type AR 502; P-type AR 504; gate lines / structures 530(1)-530(4); IDGs 532(1)-532(2); MD contact 506(1); VD structure 538; BV structure 520(1); and BM0 segment 528(1). In some embodiments, at least one of ID 532(1) and 532(2) is replaced by a corresponding gate line / structure.

[0137] The N-type AR 502 includes a dummy portion 503, herein referred to as the N-type dummy AR 503. The P-type AR 504 includes a dummy portion 505, herein referred to as the P-type dummy AR 505. In some embodiments, the dummy AR is a portion of a given AR and is electrically isolated from other portions of the given AR. In Figure 5A this case, the dummy AR 503 is isolated from other portions of the AR 502 by the IDGs 532(1)-532(2). Similarly, the dummy AR 505 is isolated from other portions of the AR 504 by the IDGs 532(1)-532(2). In some embodiments; the IDGs 532(1)-532(2) are replaced by gate lines / structures; in some such embodiments, the dummy AR 503 is the result of different doping compared to other portions of the doped AR 502, and the dummy AR 505 is the result of different doping compared to other portions of the doped AR 504.

[0138] Relative to the X-axis, the adjacent gate lines / structures 530(1)-530(4) and IDGs 532(1)-532(2) are separated from each other by a uniform distance. In some embodiments, the uniform distance represents one contact poly pitch (CPP) of the corresponding semiconductor process technology node. For example, each of (A) the gate lines / structures 530(1) and 530(2), (B) the gate lines / structures 530(2) and IDG 532(1), and (C) the IDGs 532(1) and 532(2) are separated from each other by one CPP. In some embodiments, CPP is an abbreviation for contact poly pitch, where the word "poly" does not necessarily mean that the gate lines / structures will be formed of polycrystalline silicon, but represents historical convenience, i.e., because gate structures in ICs fabricated according to previous semiconductor process technology nodes were typically formed of polycrystalline silicon.

[0139] In Figure 5A this case, the FTV 501A includes the MD contact 506(1) and the BV structure 520(1). The FTV 501A extends parallel to the Y-axis. The FTV 501A facilitates a current path from the BM0 segment 528(1) to the M0 segment 526 through the BV structure 520(1), the MD contact 506(1), and the VD structure 538.

[0140] Relative to the X-axis, the left and right sides of each of the MD contact 506(1) and the BV structure 520(1) extend in a direction opposite to and parallel to the X-axis, and thus approach the IDGs 532(1) and 532(2), respectively. Relative to the X-axis, the left and right sides of each of the MD contact 506(1) and the BV structure 520(1) do not substantially extend beyond the IDGs 532(1) and 532(2). Assuming that the IDGs 532(1) and 532(2) are separated from each other by a CPP relative to the X-axis, the width of the FTV 501A is approximately one CPP or less.

[0141] Relative to the X-axis: the IDG 532(1) represents the right boundary of the cell region 558(1); and the IDG 532(2) represents the left boundary of the cell region 558(2). Thus, the FTV 501A is located in the inter-cell gap between the cell regions 558(1) and 558(2).

[0142] According to another method, the device corresponding to the device 500A includes an FTV type corresponding to the FTV 501A and gate lines / structures corresponding to the IDGs 232(1) and 232(2). Relative to the X-axis, the corresponding FTV of the other method substantially extends beyond each of the corresponding gate lines / structures of the other method, which consumes a considerable area and reduces the device density. In contrast, the FTV 501A etc. do not substantially extend beyond the IDGs 532(1) and 532(2), such that the device 500A etc. consume less area and increase the device density compared to the other method.

[0143] Figure 5B is a layout diagram of the device 500B according to some embodiments.

[0144] The device 500B is a circuit layout including a feed-through via (FTV) 501B. In Figure 5B the cross-sectional line VI.D-VI.D' extends parallel to the Y-axis. In some embodiments, Figure 5B the cross-sectional line VI.D-VI.D' of Figure 1E corresponds to the cross-section of

[0145] The device 500B includes: gate lines / structures 530(11)-530(14); IDGs 532(11)-532(14); an MD contact 506(3); an example of a VD structure 538; M0 segments 626(11)-626(17); an example of a V0 structure 540; M1 segments 542(1)-542(3); an example of a V1 structure 562; an M2 segment 564; and a BV structure 520(3). In some embodiments, at least one of the IDs 532(11)-532(14) is replaced by a corresponding gate line / structure.

[0146] In Figure 5B , the FTV 501B includes MD contacts 506(3) and BV structures 520(3). The FTV 501B extends parallel to the Y-axis. The FTV 501B facilitates a current path from the BM0 segment (see Figure 5B of 528(2), Fig.6D of 628(2)) to the M0 segment 526(16) through an example of the BV structure 520(3), MD contacts 506(3), and VD structure 538. Additionally, the cell region 558(11) is coupled to the cell region 558(2) through an inter-cell coupling represented by the current path, which includes: the M0 segment 526(16); an example of the V0 structure 540; the M1 segment 542(3); an example of the V1 structure 562; the M2 segment 564; another example of the V1 structure 562; the M1 segment 542(2); another example of the V0 structure 540; and the M0 segment 526(13).

[0147] Relative to the X-axis, the left and right sides of each of the MD contacts 506(3) and BV structures 520(3) extend oppositely and parallel to the X-axis, thereby approaching the gate lines / structures 532(12) and 530(13) correspondingly. Relative to the X-axis, the left and right sides of each of the MD contacts 506(3) and BV structures 520(3) do not substantially extend beyond the gate lines / structures 532(12) and 530(13). Relative to the X-axis: IDG 532(11) and 532(12) represent the left and right boundaries of the cell region 558(11) correspondingly; and IDG 532(13) and 532(14) represent the left and right boundaries of the cell region 558(12) correspondingly.

[0148] According to another method, the device corresponding to the device 500A includes an FTV type corresponding to the FTV 501B and gate lines / structures corresponding to the gate lines / structures 532(12) and 530(13). Relative to the X-axis, the corresponding FTV of the another method substantially extends beyond each of the corresponding gate lines / structures of the another method, which consumes a considerable area and reduces the device density. In contrast, the FTV 501B etc. do not substantially extend beyond the gate lines / structures 532(12) and 530(13), such that the device 500B etc. consume less area and increase the device density compared to the another method.

[0149] Figure 5C is a combined schematic view and three-quarter perspective view of a device 500C according to some embodiments.

[0150] The device 500C is Figure 5B an alternative representation of the device 500B of Figure 5B In comparison, Figure 5C also includes: a representation of BM0 segment 528(2); representations of inverters 550(1) and 550(2); and a representation of an imaginary reference plane 560 parallel to the X-Y plane. With respect to the Z axis, device 500C is described as having a front side located above reference plane 560 and a back side located below reference plane 560.

[0151] Fig. 6A is a cross-sectional view of device 600A according to some embodiments.

[0152] Device 600A is an example of a device having an FTV structure, which is composed of MD contacts coupled to a BV structure. Fig. 6A Device 600A is similar to Figure 1E Device 100E. For the sake of brevity, the discussion will focus on the differences between device 600A and device 100E rather than the similarities. In some embodiments, device 600A is an example of a device corresponding to the cross-hatching IV.A-IV.A' of Figure 5A where the cross-hatching IV.A-IV.A' is parallel to the Y axis.

[0153] Device 600A includes: a pseudo-N-type AR 603; a pseudo-P-type AR 605; MD contacts 606(1); a VD structure 638; an M0 segment, including M0 segment 626(1); a BV structure 620(1); and a BM0 segment 628(1).

[0154] In Fig. 6A FTV 601A includes MD contacts 606(1) and a BV structure 620(1). MD contacts 606(1) include portions 608(31), 608(32), and 608(33).

[0155] Figure 6B is a cross-sectional view of device 600B according to some embodiments.

[0156] Device 600B is an example of a device having an FTV structure, which is composed of MD contacts coupled to a BV structure. Figure 6B Device 600B is similar to Fig. 6A Device 600A. For the sake of brevity, the discussion will focus on the differences between device 600B and device 600A rather than the similarities. In some embodiments, device 600B is an example of a device corresponding to the cross-hatching IV.B-IV.B' of Figure 5A where the cross-hatching IV.B-IV.B' is parallel to the X axis.

[0157] Device 600B includes: IDGs 632(1)-632(2); MD contact 606(1); BV structure 620(1); and BM0 segment 628(1). Relative to the X-axis, the left and right sides of BV structure 620(1) do not substantially extend beyond IDGs 632(1) and 632(2).

[0158] Figure 6C is a cross-sectional view of device 600C according to some embodiments.

[0159] Device 600C is an example of a device having an FTV structure, the FTV structure being composed of MD contacts coupled to a BV structure. Figure 6C Device 600C is similar to Figure 6B Device 600B. For the sake of brevity, the discussion will focus on the differences between device 600C and device 600B rather than the similarities. In some embodiments, device 600C is an example of a device corresponding to Figure 5A section line IV.C-IV.C’ where section line IVC.IV.C’ is parallel to the X-axis.

[0160] Device 600C includes MD contact 606(2) and BV structure 620(2), while device 600B includes MD contact 606(1) and BV structure 620(1). Relative to the Z-axis, BV structure 620(2) substantially extends into the AR layer, while BV structure 620(1) does not substantially extend into the AR layer. Accordingly, relative to the Z-axis, MD contact 606(2) does not penetrate as deeply into the AR layer as MD contact 606(1). Thus, in some aspects, Figure 6C is associated with Figure 6B in a manner somewhat similar to the way Figure 1C is associated with Figure 1A in some respects.

[0161] Fig.6D is a cross-sectional view of device 600D according to some embodiments.

[0162] Device 600D is an example of a device having an FTV structure, the FTV structure being composed of MD contacts coupled to a BV structure. In some embodiments, device 600D is an example of a device corresponding to Figure 5B section line IV.D-IV.D’ where section line IV.D.IV.D’ is parallel to the Y-axis.

[0163] Device 600D includes: MD contact 606(3); VD structure 638; BV structure 620(3); and BM0 segment 628(2). In Fig.6D FTV 601D includes MD contact 606(3) and BV structure 620(3).

[0164] Fig. 7A is a flowchart 700 of a method of manufacturing a device according to some embodiments.

[0165] According to some embodiments, the method of flowchart (flowchart) 700 can be implemented, for example, using an EDA system 800 ( Figure 8 , discussed below) and an IC manufacturing system 900 ( Fig. 9 , discussed below). Examples of devices that can be manufactured according to the method of flowchart 700 include the devices disclosed herein, devices based on the layout diagrams disclosed herein, and the like.

[0166] In Fig. 7A , the method of flowchart 700 includes blocks 702 - 704. At block 702, a layout diagram is generated, which includes, among other things, the layout diagrams disclosed herein, layout diagrams corresponding to one or more devices disclosed herein, and the like. According to some embodiments, for example, block 702 can be implemented using an EDA system 800 ( Figure 8 , discussed below). The process proceeds from block 702 to block 704.

[0167] At block 704, based on the layout diagram, (a) one or more lithographic exposures are performed, or (b) one or more lithographic masks are manufactured, or (c) at least one of one or more components in a layer of the device (e.g., the device) is manufactured. See the discussion of the IC manufacturing system 900 below Fig. 9 in.

[0168] Figure 7B is a flowchart 710B of a method of manufacturing a device according to some embodiments.

[0169] Flowchart 710B is Fig. 7A an example of block 704 of. Flowchart 710B includes blocks 712 - 730. The examples provided in the context of flowchart 710B assume a first orthogonal direction, a second orthogonal direction, and a third orthogonal direction, which are, for example, parallel to the X-axis, Y-axis, and Z-axis, respectively. According to some embodiments, the method of flowchart 710B can be implemented, for example, using an IC manufacturing system 900 ( Fig. 9 , discussed below). Examples of devices that can be manufactured according to the method of flowchart 710B include the devices disclosed herein, devices based on the layout diagrams disclosed herein, and the like.

[0170] At block 712, a first active region and a second active region are formed. Examples of the first active region include Figures 1A to 1F AR 102 of FIG. 4A to FIG. 4C , AR 402(1) - 402(3), AR 502, etc. of Figures 1A to 1F AR 104 of FIG. 4A to FIG. 4CAR 404(1)-404(3), Figure 4A AR 504, etc. The process proceeds from block 712 to block 714.

[0171] At block 714, an ohmic contact (OC) layer is formed, including forming a first ohmic contact layer on the front side of the first portion of the first active region and coupling the first ohmic contact layer to the front side of the first portion of the first active region, and forming a second ohmic contact layer on the back side of the first portion of the first active region and coupling the second ohmic contact layer to the back side of the first portion of the first active region. The process proceeds from block 714 to block 716.

[0172] At block 716, an MD contact is formed. Examples of MD contacts include those corresponding to Figures 1A to 1F MD contacts 106(1)-106(4) corresponding to FIG. 4A to FIG. 4C MD contacts 406(5)-406(7) corresponding to Figure 5A MD contact 506(1), etc. Block 716 includes blocks 718-720. Within block 716, the process proceeds to block 718.

[0173] At block 718, a first portion of the MD contact is formed on the first OC layer. Examples of the first portion of the MD contact include: Figures 1A to 1C portions 108(1) and 108(3) corresponding to Figure 1E to Figure 1F portion 108(6) corresponding to FIG. 4A to FIG. 4B portion 408(12) corresponding to Figure 4C portion 408(21), etc. The process proceeds from block 718 to block 720.

[0174] At block 720, a second portion of the MD contact is formed beside the first lateral side of the first AR. Examples of the second portion of the MD contact include: Figures 1A to 1C portions 108(2) and 108(4) corresponding to Figure 4A portion 408(14) corresponding to Figure 4C portion 408(23), etc. From block 720, the process proceeds from block 716 to block 724. However, as an option in some embodiments, the process proceeds from block 720 to block 722, which option is indicated by the dashed arrow in Figure 7B this figure.

[0175] At block 722, a third portion of the MD contact is formed beside the second lateral side of the first AR. Examples of the third portion of the MD contact include: Figure 4A portion 408(15), etc. From block 722, the process proceeds from block 716 to block 724.

[0176] At block 724, a BV structure is formed. Examples of BV structures include those corresponding to Figures 1A to 1F The BV structures 120(1)-120(4) corresponding to FIG. 4A to FIG. 4C the BV structures 420(5)-420(8), Figure 5A the BV structure 520(1), etc. The frame 724 includes frames 726-730. Inside the frame 724, the process proceeds to the frame 726.

[0177] At the frame 726, the first part of the BV structure is formed below the second OC layer. Examples of the first part of the BV structure include: Figures 1A to 1F the corresponding parts 122(1) and 122(3)-122(4) in FIG. 4A to FIG. 4B the part 422(13) and 422(15) in Figure 4C the part 422(22) and 422(26) in, etc. The process proceeds from the frame 726 to the frame 728.

[0178] At the frame 728, the second part of the BV structure is formed beside the first lateral side of the first AR. Examples of the second part of the BV structure include: Figures 1A to 1D the corresponding parts 122(2) and 122(4) in Figure 1E to Figure 1F the part 122(5) in FIG. 4A to FIG. 4B the part 422(12) and 422(15) in Figure 4C the part 422(21) and 422(27) in, etc. The process exits the frame 724 from the frame 728. However, as an option in some embodiments, the process proceeds from the frame 728 to the frame 730, which is indicated by the dashed arrow in Figure 7B

[0179] At the frame 730, the third part of the BV structure is formed beside the second lateral side of the first AR. Examples of the third part of the BV structure include: FIG. 4A to FIG. 4B the part 422(15) and 422(16) in Figure 4C the part 422(23) in, etc.

[0180] In some embodiments, at the frame 714, forming the first OC layer includes forming a silicide layer, and forming the second ohmic contact layer includes forming a silicide layer.

[0181] In some embodiments, at the frame 714, forming the ohmic contact layer further includes: (i) forming a third OC layer on the first lateral side of the first part of the first active region and coupling the third OC layer to the first lateral side of the first part of the first active region; or (ii) forming a fourth OC layer on the second lateral side of the first part of the first active region and coupling the fourth OC layer to the second lateral side of the first part of the first active region. Examples of the third OC layer include: Figure 1B and Figure 1C ​on the left side of the AR 102 and Figure 1F an instance of the OC layer 114 on the left side of the AR 104, Figure 4B on the left side of the AR 402(1) and 404(2) in, and Figure 4C an instance of the OC layer 414 on the left side of the AR 404(3) in, etc. Examples of the fourth OC layer include Figure 1B and Figure 1C on the right side of the AR 104 and Figure 1F an instance of the OC layer 116 on the right side of the AR 104 in, Figure 4B on the right side of the AR 402(1) and 404(2) in, and Figure 4C an instance of the OC layer 416 on the right side of the AR 404(3) in, etc. In such an embodiment: The block 720 further includes coupling the second part of the MD contact to the third ohmic contact layer accordingly; or the block 722 includes: coupling the third part of the MD contact to the fourth ohmic contact layer.

[0182] In some embodiments, the block 714 includes (i) and (ii). In some embodiments, at the block 714, forming the third OC layer includes forming a silicide layer, and forming the fourth ohmic contact layer includes forming a silicide layer.

[0183] In some embodiments, after the block 712 and before the block 714, the flowchart 710B includes (i) forming a first dielectric layer (e.g., an instance of 118(1), 418, etc.) on the first lateral side of the first active region, where the second part of the MD contact is located on the first dielectric layer; or (ii) forming a second dielectric layer (e.g., an instance of 118(2), 418, etc.) on the second lateral side of the first active region, where the third part of the MD contact is located on the second dielectric layer. In some embodiments, the block 712 includes (i) and (ii).

[0184] In some embodiments, the block 720 includes extending the second part of the MD contact (e.g., 108(2), etc.) to the upper surface of the second part of the BV structure (e.g., 122(2), etc.) and coupling to the upper surface of the second part of the BV structure; or the block 722 includes extending the third part of the MD contact (e.g., 408(15), etc.) to the upper surface of the third part of the BV structure (e.g., 422(14), etc.) and coupling to the upper surface of the third part of the BV structure.

[0185] In some embodiments, the block 720 includes extending a second portion of the MD contact (e.g., 108(2), etc.) beneath the upper surface of the first portion of the first active region so as to be located on the upper surface of the second portion of the BV structure (e.g., 122(2), etc.) and coupled to the upper surface of the second portion of the BV structure; or extending a third portion of the MD contact (e.g., 408(15), etc.) beneath the upper surface of the first portion of the first active region so as to be located on the upper surface of the third portion of the BV structure (e.g., 422(14), etc.) and coupled to the upper surface of the third portion of the BV structure.

[0186] In some embodiments, the block 716 includes blocks 720 and 722, and further includes: block 723(1) ( Figure 7B not shown in ), block 723(1) includes forming a fourth portion of the MD contact (e.g., 408(13)) on the third ohmic contact layer of the first portion of the second active region to create a coupling therebetween; and block 723(2) ( Figure 7B not shown in ), block 723(2) includes forming a fifth portion of the MD contact (e.g., 408(16), etc.) beside the second lateral side of the first portion of the second active region. In such an embodiment, the block 724 includes blocks 728 and 730, and further includes: block 725(1) ( Figure 7B not shown in ), block 725(1) includes forming the third portion of the BV structure (e.g., 422(14), etc.) beneath the third portion of the MD contact (e.g., 408(15), etc.) and coupling the third portion of the BV structure to the third portion of the MD contact; block 725(2) ( Figure 7B not shown in ), block 725(2) includes forming the fourth portion of the BV structure (e.g., 422(15), etc.) beneath the fourth ohmic contact layer and coupling the fourth portion of the BV structure to the fourth ohmic contact layer; and block 725(3) ( Figure 7B not shown in ), block 725(3) includes forming the fifth portion of the BV structure (e.g., 422(16), etc.) beneath the fifth portion of the MD contact and coupling the fifth portion of the BV structure to the fifth portion of the MD contact.

[0187] In some embodiments: Frame 720 includes extending a second portion of the MD contact (such as 408(14), etc.) to the upper surface of a second portion of the BV structure (such as 422(12), etc.) and coupling to the upper surface of the second portion of the BV structure; Frame 725(1) includes extending a third portion of the MD contact (such as, 408(15), etc.) to the upper surface of a third portion of the BV structure (such as, 422(14), etc.) and coupling to the upper surface of the third portion of the BV structure; or Frame 725(3), which extends a fifth portion of the MD contact (such as 408(16), etc.) to the upper surface of a fourth portion of the BV structure (such as 422(16), etc.) and couples to the upper surface of the fourth portion of the BV structure.

[0188] In some embodiments, the lower surface at the backside of each of the first active region and the second active region is substantially flat, and Frame 724 further includes: substantially extending the upper surface of a second portion (such as 422(12)) of the BV structure (such as 420(5)) above the lower surface of each of the first active region and the second active region; extending the upper surface of a third portion (such as 422(14)) of the BV structure (such as 420(5)) above the lower surface of each of the first active region and the second active region; or extending the upper surface of a fifth portion (such as 422(16)) of the BV structure (such as 420(5)) above the lower surface of each of the first active region and the second active region.

[0189] In Figure 7B , without considering the smaller frames inside the larger frame, for example, the smaller frames 718 - 722 are located inside the larger frame 714, Flowchart 710B shows the following sequence: Frame 712 → Frame 714 → Frame 716 → Frame 724.

[0190] Figure 7C is Flowchart 710C of a method for manufacturing a device according to some embodiments.

[0191] According to some embodiments, the method of Flowchart (Flowchart) 710C is implementable, for example, using the EDA system 800( Figure 8 , discussed below) and the IC manufacturing system 900( Fig. 9 , discussed below). Examples of devices that can be manufactured according to the method of Flowchart 710C include the devices disclosed herein, devices based on the layout diagrams disclosed herein, etc.

[0192] Figure 7C Flowchart 710C of Figure 7B is similar to Flowchart 710B of

[0193] Flowchart 710C includes the same blocks as flowchart 710B. However, for simplicity of illustration, flowchart 710C does not show the smaller blocks located inside the larger blocks: Figure 7C The smaller blocks 718 - 722 are not shown, where the smaller blocks 718 - 722 are located inside the larger block 716; and Figure 7C The smaller blocks 726 - 730 are not shown, where the smaller blocks 726 - 730 are located inside the larger block 724.

[0194] Flowchart 710C shows the blocks in a different order from flowchart 710B. Without considering the smaller blocks inside the larger blocks, flowchart 710C shows the following order: block 712 → block 714 → block 724 → block 716.

[0195] Fig.7D is flowchart 710D of a method of manufacturing a device according to some embodiments.

[0196] Flowchart 710D is Fig. 7A an example of block 704 of. Flowchart 710D includes blocks 742 - 764. In some embodiments, blocks 742 - 764 have a different flow order than that shown in flowchart 710D. The examples provided in the context of flowchart 710D assume a first orthogonal direction, a second orthogonal direction, and a third orthogonal direction, for example, parallel to the X - axis, Y - axis, and Z - axis respectively. According to some embodiments, the method of flowchart 710D can be implemented, for example, using an IC manufacturing system 900( Fig. 9 , discussed below). Examples of devices that can be manufactured according to the method of flowchart 710D include the devices disclosed herein, devices based on the layout diagrams disclosed herein, etc.

[0197] Flowchart 710D assumes that the layers extend in orthogonal first (e.g., parallel to the Y - axis) and second (e.g., parallel to the X - axis) directions respectively, and each layer has a thickness with respect to the third direction (e.g., parallel to the Z - axis). The assumed layers include a buried via (BV) layer located above a buried metallization layer, an AR layer located above the BV layer, and a G&MD layer located above the AR layer,

[0198] At block 742, in the G&MD layer, a line structure extending in the first direction (e.g., Y - axis) is formed. Forming the line structure includes forming a first line structure (e.g., 532(1), etc.) and a second line structure (e.g., 532(2), etc.) that respectively represent a transistor gate or an isolation dummy gate (IDG). The flow proceeds from block 742 to block 744.

[0199] At block 744, MD contacts (e.g., 506(5), etc.) are formed. Block 744 includes blocks 746 - 754. The flow within block 744 proceeds to block 746.

[0200] At block 746, a first portion of the MD contact (e.g., 608(31), 608(32), etc.) is formed in the G&MD layer. The process proceeds from block 746 to block 748.

[0201] At block 748, a second portion of the MD contact (e.g., 608(33), etc.) is formed in the AR layer. The process proceeds from block 748 to block 750.

[0202] At block 750, the ends of the MD contact (e.g., 506(5)) are correspondingly and oppositely extended in a first direction (e.g., the Y-axis). The process proceeds from block 750 to block 752.

[0203] At block 752, the first portion of the MD contact (e.g., 608(31), 608(32), etc.) is positioned between a first line structure (e.g., 532(1)) and a second line structure (e.g., 532(2)). The process proceeds from block 752 to block 754.

[0204] At block 754, the first side and the second side of the MD contact (e.g., 506(5)) are correspondingly and oppositely extended in a second direction (e.g., the X-axis) towards the first line structure (e.g., 532(1)) and the second line structure (e.g., 530(2)), but are also separated from the first line structure and the second line structure by corresponding first and second gaps (e.g., 556(1) and 556(2)). The process leaves block 744 at block 754 and proceeds to block 756.

[0205] At block 756, a BV structure (e.g., 520(1)) is formed. Block 756 includes blocks 758 - 762. Within block 756, the process proceeds to block 758.

[0206] At block 758, a first portion of the BV structure (e.g., 620(1), 620(2)) is formed in the BV layer below the MD contact, creating a coupling therebetween. The process proceeds from block 758 to block 760.

[0207] At block 760, the ends of the BV structure (e.g., 520(1)) are correspondingly and oppositely extended in a first direction (e.g., the Y-axis). The process proceeds from block 760 to block 762.

[0208] At block 762, the first side (e.g., the left side) and the second side (e.g., the right side) of the BV structure (e.g., 520(1)) are correspondingly and oppositely extended in a second direction (e.g., the X-axis) to approach the first line structure (e.g., 532(1)) and the second line structure (e.g., 532(2)), but do not extend beyond the first line structure and the second line structure. The process leaves block 756 at block 762 and proceeds to block 764.

[0209] At block 764, a buried segment (e.g., 528(1)) is formed in the buried metallization layer and the buried segment is coupled to a BV structure (e.g., 520(1)).

[0210] In some embodiments, block 764 includes: ends that extend oppositely correspondingly in a second direction (X-axis) of the buried segment (e.g., 528(1)); relative to a first direction (Y-axis), a first side (e.g., Fig. 6A the right side in ) of the buried segment (e.g., 628(1)) is extended to be close to a first side (e.g., Fig. 6A the right side in ) of the BV structure (e.g., 520(1)), and a second side (e.g., Fig. 6A the left side in ) of the buried segment is extended in a second direction (e.g., Y-axis) to be at least aligned with a second side (e.g., Fig. 6A the right side in ) of the BV structure (620(1)).

[0211] In some embodiments, block 764 includes: a second side (e.g., Fig. 6A the left side in ) of the buried segment is extended in a second direction (e.g., Y-axis) such that it extends substantially beyond a second side (e.g., Fig. 6A the left side in ) of the BV structure (e.g., 620(1)).

[0212] In some embodiments, flowchart 710D further includes: a block 740 ( Fig.7D not shown in ) before block 742, block 740 includes forming an active region in the AR layer and the active region extends in a first direction (e.g., X-axis). Block 740 includes block 740(1) ( Fig.7D not shown in ) and block 740(2) ( Fig.7D not shown in ). In block 740, the process proceeds to block 741(1).

[0213] At block 740(1), a first active region (e.g., 502) is formed, the first active region has a first pseudo-part (e.g., 503, 603) that extends between a first line structure (e.g., 532(1)) and a second line structure (e.g., 532(2)), and the first pseudo-part (e.g., 503) does not extend beyond the first line structure (e.g., 532(1)) and the second line structure (e.g., 532(2)). The process proceeds from block 740(1) to block 741(2).

[0214] At block 741(2), a second active region (e.g., 504) is formed having a second dummy portion (e.g., 505, 605) extending between a first line structure (e.g., 532(1)) and a second line structure (e.g., 532(2)), the second dummy portion (e.g., 505) not extending beyond the first line structure (e.g., 532(1)) and the second line structure (e.g., 532(2)). The process exits block 740 at block 741(2). In such an embodiment, block 744 also includes blocks 745(1)-745(3) ( Fig.7D not shown in Fig.7D ). Block 745(1) ( Fig.7D not shown in

[0215] ) includes positioning a second portion (e.g., 608(33)) of an MD contact (e.g., 606(5)) between a first dummy portion (e.g., 603) and a second dummy portion (e.g., 605) relative to a second direction (Y-axis). Block 745(2) includes coupling an MD contact (e.g., 506(5)) to a BV structure (e.g., 520(1)). Block 745(3) includes extending first and second ends of an MD contact (e.g., 506(5)) oppositely correspondingly in a first direction (Y-axis) and away from the MD contact (e.g., 506(5)) to overlap with a first dummy portion (e.g., 503) and a second dummy portion (e.g., 505), but not extending beyond the first dummy portion (e.g., 503) and the second dummy portion (e.g., 505). In some embodiments, block 745(3) includes extending an end of a BV structure (e.g., 620(1)) correspondingly at least partially below a first dummy portion (e.g., 503) and a second dummy portion (e.g., 505) relative to a first direction (e.g., Y-axis).

[0215] In some embodiments, the first line structure (e.g., 530(12)) and the second line structure (e.g., 530(13)) represent gates of respective transistors, and block 742 also includes: forming a third line structure (e.g., 532(13)), a fourth line structure (e.g., 532(14)), a fifth line structure (e.g., 532(11)), and a sixth line structure (e.g., 532(12)) representing an IDG, and positioning the first line structure (e.g., 530(12)) and the second line structure (e.g., 530(13)) between the third line structure (e.g., 532(13)) and the fourth line structure (e.g., 532(14)).

[0216] Relative to a first direction (e.g., X-axis): the third line structure (e.g., 532(13)) and the fourth line structure (e.g., 532(14)) represent a first side boundary (e.g., Figure 5B left side in Figure 5Bto the right side in); and the fifth line structure (e.g., 532(11)) and the sixth line structure (e.g., 532(12)) represent the first side boundary of the second unit region (558(11)) (e.g., Figure 5B the left side in); and the second side boundary (e.g., Figure 5B the right side in). In such an embodiment, the block 742 further includes: relative to the first direction (e.g., the X-axis), the third line structure (e.g., 532(13)) and the sixth line structure (e.g., 532(12)) are separated by an inter-cell gap (e.g., by observing Figure 5B ). In such an embodiment, the flowchart 710D further includes a block 766 ( Fig.7D not shown in).

[0217] The block 766 includes forming a metallization segment (e.g., 564) in a metallization layer (e.g., M2) above the g&MD layer. The block 766 includes blocks 768(1)-768(3) ( Fig.7D not shown in). Within the block 766, the process proceeds to the block 768(1). At the block 768(1), the metallization segment (e.g., 564) is coupled to an MD contact (e.g., 506(1)). The process proceeds from the block 768(1) to the block 768(2). At the block 768(2), the metallization segment (e.g., 564) is extended from the first unit region (e.g., 582(12)) to the second unit region (e.g., 558(11)) relative to the second direction (e.g., the X-axis). The process proceeds from the block 768(2) to the block 768(3). At the block 768(3), the metallization segment (e.g., 564) is also coupled to the second unit region (e.g., 558(11)).

[0218] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0219] In some embodiments, the EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, the EDA system 800 is a general computing device including a hardware processor 802 and a non-transitory computer-readable storage medium 804. Among other things, the storage medium 804 is also encoded with computer program code 806, a set of executable instructions. The execution of the instructions 806 by the hardware processor 802 represents (at least in part) an EDA tool that implements a method for generating a layout diagram (such as the method disclosed herein), a method for generating a layout diagram (such as the layout diagram disclosed herein or a layout diagram corresponding to the device disclosed herein, etc.) according to one or more embodiments (hereinafter referred to as the process and / or method).

[0220] The storage medium 804 also stores a layout diagram 811, such as the layout diagram disclosed herein, etc.

[0221] The processor 802 is electrically coupled to the computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I / O interface 810 via the bus 808. A network interface 812 is also electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814 such that the processor 802 and the computer-readable storage medium 804 can be connected to external components via the network 814. The processor 802 is configured to execute computer program code 806 encoded in the computer-readable storage medium 804 such that the EDA system 800 can be used to perform some or all of the processes and / or methods. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0222] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid state memories, magnetic tapes, removable computer disks, random access memory (RAM), read only memory (ROM), rigid disks, and / or optical disks. In one or more embodiments using optical disks, the computer-readable storage medium 804 includes compact disk read only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0223] In one or more embodiments, the storage medium 804 stores computer program code 806 configured to make the EDA system 800 (where such execution represents (at least in part) an EDA tool) available to perform some or all of the processes and / or methods. In one or more embodiments, the storage medium 804 also stores information that facilitates the execution of some or all of the processes and / or methods. In one or more embodiments, the storage medium 804 stores a standard cell library 807 including the standard cells disclosed herein. In some embodiments, the storage medium 804 stores one or more layout diagrams 811.

[0224] The EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for passing information and commands to the processor 802.

[0225] The EDA system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the EDA system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods are implemented in two or more EDA systems 800.

[0226] The EDA system 800 is configured to receive information through the I / O interface 810. The information received through the I / O interface 810 includes one or more of instructions, data, design rules, a standard cell library, and / or other parameters for the processor 802 to process. This information is transmitted to the processor 802 via the bus 808. The EDA system 800 is configured to receive information related to the user interface (UI) through the I / O interface 810. This information is stored as the UI 842 in the computer-readable medium 804.

[0227] In some embodiments, part or all of the processes and / or methods are implemented as independent software applications executed by the processor. In some embodiments, part or all of the processes and / or methods are implemented as software applications that are part of additional software applications. In some embodiments, part or all of the processes and / or methods are implemented as plugins of software applications. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as software applications used by the EDA system 800. In some embodiments, tools such as those available from CADENCE DESIGN SYSTEMS, Inc. are used, such as to generate a layout including standard cells using a tool or another suitable layout generation tool.

[0228] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of optical discs (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM), RAM, memory cards, etc.

[0229] Fig. 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and an associated IC manufacturing process according to some embodiments.

[0230] In some embodiments, based on Fig. 7AThe layout diagram generated by the block 702, the IC manufacturing system 900 implements Fig. 7A of block 704, where the manufacturing system 900 is used to manufacture at least one component in (A) one or more semiconductor masks or (B) at least one component in an early semiconductor integrated circuit layer. In some embodiments, the IC manufacturing system 900 implements FIG. 7A to FIG. 7B of the flowchart.

[0231] In Fig. 9 , the IC manufacturing system 900 includes entities that interact in the design, development, and manufacturing cycle and / or services related to manufacturing the IC device 960, such as the design house 920, the mask house 930, and the IC manufacturer / fabricator ("fab") 950. The entities in the system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 920, the mask house 930, and the IC manufacturer 950 are owned by a single larger company. In some embodiments, two or more of the design house 920, the mask house 930, and the IC manufacturer 950 coexist in a common facility and use common resources.

[0232] The design house (or design team) 920 generates the IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers of the various components that make up the IC device 960 to be manufactured. The layers are combined to form various IC components. For example, portions of the IC design layout 922 include various IC components, such as active regions, gate terminals, source and drain electrodes, metal wires or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Depending on the context, the source / drain regions may be referred to individually or collectively as the source or drain. The design house 920 performs appropriate design processes to form the IC design layout 922. The design processes include one or more of logic design, physical design, or layout and routing. The IC design layout 922 is presented in one or more data files having information with geometric patterns. For example, the IC design layout 922 is represented in the GDSII file format or the DFII file format.

[0233] The mask chamber 930 includes data preparation 932 and mask fabrication 934. The mask chamber 930 uses the IC design layout 922 to fabricate one or more masks 935 for use in fabricating the respective layers of the IC device 960 according to the IC design layout 922. The mask chamber 930 performs mask data preparation 932, in which the IC design layout 922 is converted into a representative data file ("RDF"). The mask data preparation 932 provides the RDF to the mask fabrication 934. The mask fabrication 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) or a semiconductor wafer. The design layout is manipulated by the mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 950. In Fig. 9 , the mask data preparation 932, the mask fabrication 934, and the mask 935 are shown as separate elements. In some embodiments, the mask data preparation 932 and the mask fabrication 934 are collectively referred to as mask data preparation.

[0234] In some embodiments, the mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 922. In some embodiments, the mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is further used, and the ILT treats the OPC as an inverse imaging problem.

[0235] In some embodiments, the mask data preparation 932 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the OPC-processed IC design layout. The set of mask creation rules contains certain geometric and / or connectivity limitations to ensure sufficient margins to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication 934, which may undo some of the modifications performed by the OPC to meet the mask creation rules.

[0236] In some embodiments, mask data preparation 932 includes lithography process check (LPC), and the LPC simulation processes that will be implemented by the IC manufacturer 950 to fabricate the IC device 960. The LPC simulates the process based on the IC design layout 922 to fabricate a simulated fabricated device, such as the IC device 960. The process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after the LPC fabricates the simulated fabricated device, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further optimize the IC design layout 922.

[0237] For clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, mask data preparation 932 includes additional features, such as logical operations (LOP) to modify the IC design layout according to manufacturing rules. In addition, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different orders.

[0238] After mask data preparation 932 and during mask manufacturing 934, a mask 935 or a set of masks 935 is fabricated based on the modified IC design layout. In some embodiments, based on the modified IC design layout, a pattern is formed on the mask (photomask or intermediate mask) using an electron beam (e-beam) or a mechanism of multiple electron beams. Masks are formed by various techniques. In some embodiments, a binary technique is used to form the mask. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (such as an ultraviolet (UV) beam) for exposing an image-sensitive material layer (such as photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, a phase-shift technique is used to form the mask. In a phase-shift mask (PSM), various components in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase-shift mask is an attenuated PSM or an alternating PSM. The mask generated by mask manufacturing 934 is used for various processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0239] IC manufacturer 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer 950 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for the interconnect and packaging of IC products, and a third manufacturing facility can provide other services for the foundry business.

[0240] IC manufacturer 950 uses mask 935 fabricated by mask chamber 930 to fabricate IC device 960 using manufacturing tool 952. Thus, IC manufacturer 950 uses IC design layout 922 at least indirectly to fabricate IC device 960. In some embodiments, semiconductor wafer 953 is fabricated by IC manufacturer 950 using mask(s) 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric components, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0241] In some embodiments, a device includes: a first active region; a first ohmic contact layer and a second ohmic contact layer, located on the front side and the back side of a first portion of the first active region respectively, and coupled to the front side and the back side of the first portion of the first active region; a metal-to-source / drain (MD) contact, including a first portion located on the first ohmic contact layer and at least a second portion or a third portion located beside the first lateral side or the second lateral side of the first portion of the first active region respectively, the first portion of the MD contact being coupled to the first ohmic contact layer; and a buried via (BV) structure, including: a first portion located below the second ohmic contact layer and coupled to the second ohmic contact layer; a second portion located below the MD contact and coupled to the second portion of the MD contact.

[0242] In some embodiments, each of the first ohmic contact layer and the second ohmic contact layer includes a corresponding silicide layer.

[0243] In some embodiments, the device further includes: a third ohmic contact layer or a fourth ohmic contact layer, located on the first lateral side or the second lateral side of the first portion of the first active region respectively and coupled to the first lateral side or the second lateral side of the first portion of the first active region, and wherein: the second portion or the third portion of the MD contact is coupled to the third ohmic contact layer or the fourth ohmic contact layer respectively.

[0244] In some embodiments, the third ohmic contact layer includes a silicide layer; or the fourth ohmic contact layer includes a silicide layer.

[0245] In some embodiments, the device further comprises: a first dielectric layer and a second dielectric layer, located on a first lateral side or a second lateral side of a first portion of the first active region, respectively; and wherein a second portion or a third portion of the MD contact is located on the first dielectric layer or the second dielectric layer, respectively.

[0246] In some embodiments, the BV structure further comprises at least a second portion or a third portion, located beside a first lateral side or a second lateral side of a first portion of the first active region, respectively; and a second portion or a third portion of the MD contact is located on and coupled to the second portion or the third portion of the BV structure, respectively.

[0247] In some embodiments, the BV structure further comprises a second portion and a third portion; the MD contact comprises a second portion and a third portion; and the second portion and the third portion of the MD contact are located on and coupled to the second portion and the third portion of the BV structure, respectively.

[0248] In some embodiments, the lower surface at the back side of the first portion of the first active region is substantially flat; the upper surface of the first portion of the BV structure is substantially flat and substantially parallel to the lower surface of the first portion of the first active region; the upper surface of the second portion or the third portion of the BV structure is substantially flat; the upper surface of the second portion or the third portion of the BV structure is also substantially coplanar with the upper surface of the first portion of the BV structure; and the second portion or the third portion of the MD contact extends downward, respectively, to be located on and coupled to the upper surface of the second portion or the third portion of the BV structure, respectively.

[0249] In some embodiments, the device further comprises: the upper surface and the lower surface located at the front side and the back side of the first portion of the first active region, respectively, are substantially flat; the upper surface of the second portion or the third portion of the BV structure extends substantially above the lower surface of the first portion of the first active region; and the second portion or the third portion of the MD contact extends substantially below the upper surface of the first portion of the first active region, respectively, to be located on and coupled to the upper surface of the second portion or the third portion of the BV structure.

[0250] In some embodiments, the device further includes: a second active region; a third ohmic contact layer and a fourth ohmic contact layer, correspondingly located on the front side and the back side of a first portion of the second active region, and coupled to the front side and the back side of the first portion of the second active region; and wherein, a first lateral side and a second lateral side of the first portion of the second active region are correspondingly located at the proximal end and the distal end of a first lateral side and a second lateral side of the first portion of the first active region; the MD contact includes a second portion and a third portion; the second portion of the MD contact is located beside the first lateral side of the first portion of the first active region; the third portion of the MD contact is located beside the second lateral side of the first portion of the first active region; the MD contact further includes a fourth portion located on the third ohmic contact layer of the first portion of the second active region, and a fifth portion correspondingly located beside the second lateral side of the first portion of the second active region, the fourth portion of the MD contact is coupled to the third ohmic contact layer; and a second portion of the BV structure is located below the second portion of the MD contact and coupled to the second portion of the MD contact; and the BV structure further includes: a third portion of the BV structure, located below the third portion of the MD contact and coupled to the third portion of the MD contact; a fourth portion of the BV structure, located below the fourth ohmic contact layer, and coupled to the fourth ohmic contact layer; and a fifth portion of the BV structure is located below the fifth portion of the MD contact, and coupled to the fifth portion of the MD contact.

[0251] In some embodiments, a lower surface at the back side of each of the first portions of the first active region and the second active region is substantially flat; an upper surface of each of the first portion and the fourth portion of the BV structure is substantially flat, and correspondingly substantially parallel to the lower surface of each of the first portions of the first active region and the second active region; an upper surface of at least one of the second portion, the third portion or the fifth portion of the BV structure is substantially flat; an upper surface of the second portion, the third portion or the fifth portion of the BV structure is further substantially coplanar with an upper surface of each of the first portion and the fourth portion of the BV structure; and the second portion, the third portion or the fifth portion of the MD contact correspondingly extends downward so as to be located on the upper surface of the second portion, the third portion or the fifth portion of the BV structure and coupled to the upper surface of the second portion, the third portion or the fifth portion of the BV structure.

[0252] In some embodiments, a lower surface correspondingly located at the back side of each of the first portions of the first active region and the second active region is substantially flat; and an upper surface of at least one of the second portion, the third portion or the fifth portion of the BV structure substantially extends above the lower surface of each of the first portions of the first active region and the second active region.

[0253] In some embodiments, the device includes layers extending in respective orthogonal first and second directions, each layer having a thickness with respect to a third direction. The layers include a buried via (BV) layer located above a buried metallization layer, an active region (AR) layer located above the BV layer, and a first layer located above the AR layer. The wire structures in the first layer extend in the second direction and include a first wire structure and a second wire structure, where the first wire structure and the second wire structure respectively represent the gate or isolation dummy gate (IDG) of a transistor; a metal-to-source / drain region (MD) contact having a first portion in the first layer and a second portion in the AR layer. The MD contact has ends extending in opposite directions in the second direction, and the first portion of the MD contact is located between the first wire structure and the second wire structure. The first side and the second side of the MD contact extend in opposite directions toward the first wire structure and the second wire structure in the first direction, but are separated from the first wire structure and the second wire structure by respective first and second gaps; at least a BV structure in the BV layer, the BV structure being located below the second portion of the MD contact and coupled to the second portion of the MD contact. The BV structure has ends extending in opposite directions in the second direction, and the first side and the second side of the BV structure extend in opposite directions in the first direction to be close to the first wire structure and the second wire structure, but do not extend beyond the first wire structure and the second wire structure; and with respect to the third direction, a buried segment in the buried metallization layer is located below the BV layer and coupled to the BV structure.

[0254] In some embodiments, the device further includes: a first active region and a second active region, located in the AR layer and extending in the first direction. The first active region and the second active region respectively have a first dummy portion and a second dummy portion extending between the first wire structure and the second wire structure, and the first dummy portion and the second dummy portion do not extend beyond the first wire structure and the second wire structure; and wherein, with respect to the second direction, the first portion of the MD contact is located between the first dummy portion and the second dummy portion and is coupled to the BV structure; and the first end and the second end of the MD contact extend in opposite directions away from the first portion of the MD contact in the second direction to overlap with the first dummy portion and the second dummy portion, but do not extend beyond the first dummy portion and the second dummy portion.

[0255] In some embodiments, with respect to the second direction, the ends of the BV structure respectively extend at least partially below the first dummy portion and the second dummy portion.

[0256] In some embodiments, the first line structure and the second line structure represent the gates of corresponding transistors; the first line structure and the second line structure are located between the third line structure and the fourth line structure; the third line structure and the fourth line structure represent IDGs; with respect to a first direction, the third line structure and the fourth line structure represent the first side boundary and the second side boundary of a first cell region; the fifth line structure and the sixth line structure represent IDGs; with respect to the first direction, the fifth line structure and the sixth line structure represent the first side boundary and the second side boundary of a second cell region; with respect to the first direction, the fifth line structure and the sixth line structure are separated by an inter-cell gap; and the device further includes: a metallization segment in a metallization layer (M2) located above a first layer, the metallization segment being coupled to an MD contact, the metallization segment extending from the first cell region to the second cell region with respect to the first direction, and the metallization segment also being coupled to the second cell region.

[0257] In some embodiments, a method (of manufacturing a device) includes: forming an active region, including: forming a first active region; forming an ohmic contact layer, including forming a first ohmic contact layer on a front side of a first portion of the first active region, and the first ohmic contact layer being coupled to the front side of the first portion of the first active region, and forming a second ohmic contact layer on a back side of the first portion of the first active region, and the second ohmic contact layer being coupled to the back side of the first portion of the first active region;

[0258] forming a metal-to-source / drain (MD) contact, including forming a first portion of the MD contact on the first ohmic contact layer, creating a coupling between the first ohmic contact layer and the first portion of the MD contact, and forming a second portion of the MD contact beside a first lateral side of the first portion of the first active region, or forming a third portion of the MD contact beside a second lateral side of the first portion of the first active region; and forming a buried via (BV) structure, including forming a first portion of the BV structure below the second ohmic contact layer, and the first portion of the BV structure being coupled to the second ohmic contact layer, and forming a second portion of the BV structure below the second portion or the third portion of the MD contact, and the second portion of the BV structure being coupled to the second portion or the third portion of the MD contact.

[0259] In some embodiments, forming the ohmic contact layer further includes forming a third ohmic contact layer on a first lateral side of the first portion of the first active region, and the third ohmic contact layer being coupled to the first lateral side of the first portion of the first active region, or forming a fourth ohmic contact layer on a second lateral side of the first portion of the first active region, and the fourth ohmic contact layer being coupled to the second lateral side of the first portion of the first active region; and forming the metal-to-source / drain (MD) contact further includes coupling the second portion of the MD contact to the third ohmic contact layer, or coupling the third portion of the MD contact to the fourth ohmic contact layer.

[0260] In some embodiments, forming a buried via (BV) structure further includes forming a second portion of the BV structure beside a first lateral side of a first portion of the first active region, or forming a third portion of the BV structure beside a second lateral side of the first portion of the first active region; and forming a metal-to-source / drain (MD) contact further includes coupling a second portion of the MD contact to the second portion of the BV structure, or coupling a third portion of the MD contact to the third portion of the BV structure.

[0261] In some embodiments, forming an active region includes forming a second active region, with a first lateral side and a second lateral side of a first portion of the second active region located at a proximal end and a distal end, respectively, of the first lateral side and the second lateral side of the first portion of the first active region; forming an ohmic contact layer further includes forming a third ohmic contact layer on a front side of the first portion of the second active region, and coupling the third ohmic contact layer to the front side of the first portion of the second active region, and forming a fourth ohmic contact layer on a back side of the first portion of the second active region, and coupling the fourth ohmic contact layer to the back side of the first portion of the second active region; and forming a metal-to-source / drain (MD) contact further includes forming a second portion of the MD contact and forming a third portion of the MD contact; the second portion of the MD contact is located beside the first lateral side of the first portion of the first active region; the third portion of the MD contact is located beside the second lateral side of the first portion of the first active region; the second portion of the BV structure is located below and coupled to the second portion of the MD contact; forming a metal-to-source / drain (MD) contact further includes forming a fourth portion of the MD contact on the third ohmic contact layer of the first portion of the second active region, creating a coupling between the third ohmic contact layer of the first portion of the second active region and the fourth portion of the MD contact, and forming a fifth portion of the MD contact beside the second lateral side of the first portion of the second active region; and forming a buried via (BV) structure further includes forming a third portion of the BV structure below the third portion of the MD contact, and coupling the third portion of the BV structure to the third portion of the MD contact, forming a fourth portion of the BV structure below the fourth ohmic contact layer, and coupling the fourth portion of the BV structure to the fourth ohmic contact layer, and forming a fifth portion of the BV structure below the fifth portion of the MD contact, and coupling the fifth portion of the BV structure to the fifth portion of the MD contact.

[0262] One or more of the disclosed embodiments will readily be seen by one of ordinary skill in the art to implement one or more of the above advantages. After reading the above specification, one of ordinary skill in the art will be able to affect various changes, substitutions of equivalents, and various other embodiments disclosed herein. Accordingly, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit device, comprising: A first active region; A first ohmic contact layer and a second ohmic contact layer, respectively located on the front side and the back side of a first part of the first active region, and coupled to the front side and the back side of the first part of the first active region; A metal-to-source / drain (MD) contact, comprising a first part located on the first ohmic contact layer and at least a second part or a third part respectively located beside a first lateral side or a second lateral side of the first part of the first active region, and the first part of the metal-to-source / drain contact is coupled to the first ohmic contact layer; And A buried via (BV) structure, comprising: A first part, located below the second ohmic contact layer and coupled to the second ohmic contact layer; A second part, located below the metal-to-source / drain contact and coupled to the metal-to-source / drain contact.

2. The integrated circuit device according to claim 1, wherein: Each of the first ohmic contact layer and the second ohmic contact layer comprises a corresponding silicide layer.

3. The integrated circuit device according to claim 1, further comprising: A third ohmic contact layer or a fourth ohmic contact layer, respectively located on the first lateral side or the second lateral side of the first part of the first active region and coupled to the first lateral side or the second lateral side of the first part of the first active region; and Wherein: The second part or the third part of the metal-to-source / drain contact is correspondingly coupled to the third ohmic contact layer or the fourth ohmic contact layer.

4. The integrated circuit device according to claim 3, wherein: The third ohmic contact layer comprises a silicide layer; or The fourth ohmic contact layer comprises a silicide layer.

5. The integrated circuit device according to claim 1, further comprising: A first dielectric layer and a second dielectric layer, respectively located on the first lateral side or the second lateral side of the first part of the first active region; And Wherein: The second part or the third part of the metal-to-source / drain contact is correspondingly located on the first dielectric layer or the second dielectric layer.

6. The integrated circuit device according to claim 1, wherein: The buried via structure further comprises at least a second part or a third part, the second part or the third part is respectively located beside the first lateral side or the second lateral side of the first part of the first active region; and The second part or the third part of the metal-to-source / drain contact is correspondingly located on the second part or the third part of the buried via structure and coupled to the second part or the third part of the buried via structure.

7. The integrated circuit device according to claim 6, wherein: The buried via structure further comprises the second part and the third part; The metal-to-source / drain contact comprises the second part and the third part; and The second and third portions of the metal-to-source / drain contact are correspondingly located on and coupled to the second and third portions of the buried via structure.

8. The integrated circuit device according to claim 6, wherein: The lower surface at the back side of the first portion of the first active region is substantially flat; The upper surface of the first portion of the buried via structure is substantially flat and substantially parallel to the lower surface of the first portion of the first active region; The upper surface of the second or third portion of the buried via structure is substantially flat; The upper surface of the second or third portion of the buried via structure is also substantially coplanar with the upper surface of the first portion of the buried via structure; and The second or third portion of the metal-to-source / drain contact extends downward correspondingly to be located on and coupled to the upper surface of the second or third portion of the buried via structure.

9. An integrated circuit device, comprising: With respect to layers extending correspondingly in orthogonal first and second directions, each of the layers having a thickness with respect to a third direction, the layers including a buried via (BV) layer located above a buried metallization layer, an active region (AR) layer located above the buried via layer, and a first layer located above the active region layer, A line structure in the first layer extends in the second direction, the line structure including a first line structure and a second line structure, the first line structure and the second line structure correspondingly representing a gate or an isolation dummy gate (IDG) of a transistor; A metal-to-source / drain region (MD) contact having a first portion in the first layer and a second portion in the active region layer, The metal-to-source / drain contact has ends extending oppositely correspondingly in the second direction, and The first portion of the metal-to-source / drain contact is located between the first line structure and the second line structure, The first and second sides of the metal-to-source / drain contact extend oppositely correspondingly in the first direction toward the first line structure and the second line structure, but are separated from the first line structure and the second line structure by corresponding first and second gaps; A buried via structure, at least located in the buried via layer, the buried via structure being located below the second portion of the metal-to-source / drain contact and coupled to the second portion of the metal-to-source / drain contact, The buried via structure has ends extending oppositely correspondingly in the second direction, and The first and second sides of the buried via structure extend oppositely correspondingly in the first direction to be close to the first line structure and the second line structure, but do not extend beyond the first line structure and the second line structure; and Relative to the third direction, the buried segment in the buried metallization layer is located below the buried via layer and coupled to the buried via structure.

10. A method of manufacturing an integrated circuit device, the method comprising: Forming an active region, including: Forming a first active region; Forming an ohmic contact layer, including: Forming a first ohmic contact layer on a front side of a first portion of the first active region, and the first ohmic contact layer is coupled to the front side of the first portion of the first active region; and Forming a second ohmic contact layer on a back side of the first portion of the first active region, and the second ohmic contact layer is coupled to the back side of the first portion of the first active region; Forming a metal-to-source / drain (MD) contact, including: Forming a first portion of the metal-to-source / drain contact on the first ohmic contact layer, creating a coupling between the first ohmic contact layer and the first portion of the metal-to-source / drain contact; and Forming a second portion of the metal-to-source / drain contact beside a first lateral side of the first portion of the first active region; or Forming a third portion of the metal-to-source / drain contact beside a second lateral side of the first portion of the first active region; and Forming a buried via (BV) structure, including: Forming a first portion of the buried via structure below the second ohmic contact layer, and the first portion of the buried via structure is coupled to the second ohmic contact layer; and Forming a second portion of the buried via structure below the second portion or the third portion of the metal-to-source / drain contact, and the second portion of the buried via structure is coupled to the second portion or the third portion of the metal-to-source / drain contact.

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