Passivation layer of display chip, preparation method of passivation layer and display chip

Abstract

The invention discloses a passivation layer of a display chip, the display chip is provided with a light-emitting layer, the passivation layer comprises a first passivation layer, the first passivation layer is located on the side wall of the light-emitting layer, and the first passivation layer is made of nitrogen-containing and aluminum-containing materials. The passivation layer is formed by the nitrogen-containing and aluminum-containing material, so that the interface defects between the light-emitting layer and the passivation layer can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of light emitting diodes, and particularly relates to a passivation layer of a display chip, a preparation method thereof, and a display chip. Background Art

[0002] A micro light emitting diode (Micro Light Emitting Diode) micro display chip is a new type of LED structure obtained by thinning, miniaturizing, and arraying the original LED structure. It integrates an array of micron-scale LED units on an active addressing driving panel to achieve the lighting and individual control of the LED units, thereby outputting a desired display image.

[0003] As Figure 1 shown, the Micro display chip includes a light emitting mesa MESA 001, and the side surface of the MESA is covered with a passivation layer 002. For a micro display chip that emits blue-green light, the semiconductor layer of the light emitting mesa 001 mainly uses a GaN layer, and the passivation layer 002 is mostly made of one or more materials such as SiO2, Al2O, and Si3N4 by deposition. Since the lattice match between GaN and materials such as SiO2, Al2O, and Si3N4 is poor, a large number of interface defects are easily formed at the contact surface between the light emitting mesa and the passivation layer, thereby capturing the carriers of the GaN layer, quenching excitons, and causing a decrease in the light emitting efficiency, as Figure 2 shown. Summary of the Invention

[0004] In view of some or all of the problems in the prior art, a first aspect of the present invention provides a passivation layer of a display chip, wherein the display chip includes a light emitting layer, and the passivation layer includes:

[0005] A first passivation layer, which is disposed on the side wall of the light emitting layer, and the material of the first passivation layer uses a material containing nitrogen and aluminum.

[0006] Further, the first passivation layer at least covers the side wall surface of the light emitting layer.

[0007] Further, the first passivation layer has a cup shape.

[0008] Further, the first passivation layer is a continuous thin film layer having a cup-shaped protrusion.

[0009] Further, the material of the first passivation layer uses Al x Ga y In z N, wherein x + y + z = 1.

[0010] Further, the value range of x is from 0.7 to 1.0, the value range of y is from 0 to 0.2, and the value range of z is from 0 to 0.1.

[0011] Further, the material used for the first passivation layer is AlN.

[0012] Further, the thickness range of the first passivation layer is from 10 to 50 nm.

[0013] Further, the passivation layer further includes a second passivation layer, and the second passivation layer is disposed on the first passivation layer.

[0014] Further, the material of the second passivation layer is one or a combination of SiO2, Al2O, and Si3N4.

[0015] Further, the light-emitting layer includes a multi-layer stacked quantum well light-emitting layer.

[0016] Further, the light-emitting layer contains gallium and nitrogen.

[0017] Based on the passivation layer of the display chip as described above, the second aspect of the present invention provides a microLED display chip, which includes the passivation layer of the display chip as described above.

[0018] Further, the microLED display chip further includes: a microLED light-emitting mesa array; wherein each microLED light-emitting mesa includes:

[0019] A first-type semiconductor layer;

[0020] The light-emitting layer, located on the first-type semiconductor layer;

[0021] A second-type semiconductor layer, located on the light-emitting layer.

[0022] Further, the passivation layer at least coats the sidewall surfaces of the first-type semiconductor layer, the light-emitting layer, and the second-type semiconductor layer.

[0023] Further, the microLED display chip further includes:

[0024] A top electrode, located above the second-type semiconductor layer and electrically connected to the second-type semiconductor layer;

[0025] A bottom electrode, located below the first-type semiconductor layer and electrically connected to the first-type semiconductor layer.

[0026] Further, the microLED display chip further includes: a pixel driving backplane, located below the bottom electrode and electrically connected to the bottom electrode.

[0027] In the third aspect of the present invention, a microLED display device is provided, which includes a passivation layer of the display chip as described above.

[0028] In the fourth aspect of the present invention, a method for preparing a passivation layer of the display chip as described above is provided, including:

[0029] Step 01: Provide a semiconductor substrate having a light-emitting layer;

[0030] Step 02: Deposit a nitrogen-containing and aluminum-containing material on the sidewalls of the light-emitting layer.

[0031] Further, the step 02 includes:

[0032] Step 201: Introduce a gas containing an aluminum source into the semiconductor substrate;

[0033] Step 202: Introduce an inert gas into the semiconductor substrate;

[0034] Step 203: Introduce a gas containing a nitrogen source into the semiconductor to form a nitrogen-containing and aluminum-containing material.

[0035] Further, the step 02 further includes: repeating steps 201 to 203 several times.

[0036] Further, the gas containing an aluminum source in the step 201 is trimethylaluminum; the gas containing a nitrogen source in the step 203 is NH3.

[0037] Further, a by-product is also formed in the step 203, and after the step 02, it further includes: removing the by-product.

[0038] Further, the by-product in the step 203 is methane.

[0039] Further, in the step 201, the gas containing an aluminum source is adsorbed on the semiconductor substrate.

[0040] Further, the semiconductor substrate is a substrate made of a material containing nitrogen and gallium.

[0041] Further, in the step 201, specifically, a gas containing an aluminum source and a carrier gas are introduced.

[0042] Further, in the step 201, the carrier gas is nitrogen or argon.

[0043] A passivation layer of a display chip provided by the present invention introduces a passivation layer containing nitrogen and aluminum, such as AlN, etc., which covers the surface of the light-emitting layer. The light-emitting layer contains nitrogen and gallium, and is made of materials such as GaN. Since the lattice of AlN matches that of GaN, using AlN as the passivation layer material directly covering GaN can reduce the interface defects between the light-emitting layer and the passivation layer. In addition, compared with traditional passivation layer materials such as SiO2, Al2O, and Si3N4, AlN has a large bandgap, which can effectively confine carriers within GaN, thereby improving the efficiency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] To further clarify the above and other advantages and features of the embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present invention and will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar reference numerals.

[0045] Figure 1 Showing a schematic structural diagram of a microLED display chip in the prior art;

[0046] Figure 2 Showing a schematic energy band diagram of a passivation layer and a light-emitting layer in the prior art;

[0047] Figure 3 Showing a schematic structural diagram of a passivation layer of a display chip according to an embodiment of the present invention;

[0048] Figure 4 Showing a schematic structural diagram of a passivation layer of a display chip according to another embodiment of the present invention;

[0049] Figure 5 Showing a schematic diagram of the bandgap width of aluminum nitride;

[0050] Figure 6 Showing a schematic energy band diagram of a passivation layer and a light-emitting layer of a display chip according to an embodiment of the present invention;

[0051] Figure 7 Showing a schematic structural diagram of a microLED display chip according to an embodiment of the present invention;

[0052] Figure 8 Showing a schematic structural diagram of a microLED display chip according to another embodiment of the present invention;

[0053] Figure 9 Showing a schematic flowchart of a preparation method of a passivation layer of a display chip according to an embodiment of the present invention;

[0054] Figure 10Schematic flow diagram of depositing a passivation layer showing an embodiment of the present invention; and

[0055] Figures 11a to 11e Schematic process diagram of a method for preparing a passivation layer of a display chip showing an embodiment of the present invention. Detailed implementation manners

[0056] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments can be implemented without one or more specific details or in conjunction with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive aspects of the present invention. Similarly, for purposes of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the embodiments shown in the drawings are illustrative representations and not necessarily drawn to scale correctly.

[0057] In this specification, the reference to "an embodiment" or "the embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. The phrase "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment.

[0058] It should be noted that the embodiments of the present invention describe the process steps in a specific order. However, this is only for the purpose of illustrating the specific embodiment and does not limit the sequence of the steps. On the contrary, in different embodiments of the present invention, the sequence of the steps can be adjusted according to the process adjustment.

[0059] In the present invention, the term "from bottom to top" means from the side facing away from the light-emitting side of the micro light-emitting diode to the side facing the light-emitting side. Here, the "light-emitting side" refers to the side where the light emitted by the micro light-emitting diode exits the micro light-emitting diode, for example, the side where the microlens is located. The term "top surface of the light-emitting mesa" refers to the surface of the light-emitting mesa facing the light-emitting side, while the term "bottom surface of the light-emitting mesa" refers to the surface of the light-emitting mesa facing away from the light-emitting side. The term "side surface of the light-emitting mesa" refers to the surface of the light-emitting mesa between the top surface and the bottom surface.

[0060] Aiming at the problem that there are many interface defects between the passivation layer and the light-emitting mesa in the existing display chips, which may lead to a decrease in light-emitting efficiency, the present invention provides a passivation layer for a display chip, which is made of a material containing nitrogen and aluminum. Therefore, for a blue-green light chip with a GaN semiconductor layer as the light-emitting mesa, the lattice between the passivation layer and the light-emitting mesa is more matched, there are fewer interface defects, and the device efficiency can be improved.

[0061] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings of the embodiments.

[0062] Figure 3 The structural schematic diagram of the passivation layer of a display chip showing an embodiment of the present invention is as follows. As Figure 3 shown, a passivation layer of a display chip includes a first passivation layer 321, wherein the first passivation layer 321 is disposed on the sidewall of the light-emitting layer 301. In some embodiments, the light-emitting layer 301 contains Ga and N. Based on this, in some embodiments, the material of the first passivation layer 321 is a nitrogen-containing and aluminum-containing material, which directly covers the surface of the light-emitting layer 301, and can reduce interface defects.

[0063] In some embodiments, the first passivation layer 321 is a cup-shaped continuous thin film layer that at least covers the sidewall surface of the light-emitting layer 301. In some embodiments, as Figure 4 shown, the first passivation layer 321 further has a protrusion 401. In some embodiments, the thickness of the first passivation layer 321 is 10 to 50 nm.

[0064] As Figure 5 shown, the bandgap of GaN is between that of InN and AlN. The bandgap of InN is 0.63 eV, the bandgap of AlN is 6.2 eV, and that of GaN is 3.4 eV. According to calculations, the radiation wavelength of GaN-based semiconductors exactly covers the entire visible light region, so it is mostly used for preparing the light-emitting layer. And the bandgap of AlN is larger than that of GaN, so carriers can be effectively confined within GaN, thereby improving the device efficiency, as Figure 6 shown. Based on this, in some embodiments, the material of the first passivation layer 321 is AlN.

[0065] In some embodiments, the material of the first passivation layer 321 can also be Al x Ga y In z N, where x + y + z = 1. Among them, the value range of x is 0.7 to 1.0, the value range of y is 0 to 0.2, and the value range of z is 0 to 0.1. The bandgap of Al x Ga y In z N is 5.0 to 6.2 eV, and carriers can also be effectively confined within GaN.

[0066] In some embodiments, as Figure 3 shown, the display chip further includes a second passivation layer 322, and the second passivation layer 322 is disposed on the first passivation layer 321. In some embodiments, in order to achieve higher performance, the material of the second passivation layer 322 is one or a combination of SiO2, Al2O3, and Si3N4.

[0067] Based on the passivation layer of the display chip as described above, it can be applied to light-emitting devices such as microLED display chips. Figure 7 The structural schematic diagram of a microLED display chip showing an embodiment of the present invention is as follows. Figure 7 As shown, the microLED display chip includes the passivation layer 702 as described above, and the passivation layer 702 is disposed on the light-emitting mesa 701 of the microLED display chip. Since the light-emitting mesa 701 includes Ga and N, therefore, using a material containing Al and N as the first passivation layer and directly covering the light-emitting mesa 701 can effectively reduce the interface defects between the light-emitting mesa 701 and the passivation layer. In some embodiments, a second passivation layer is further disposed on the first passivation layer.

[0068] The micro light-emitting diode chip includes a driving backplane (not shown in the figure) and a micro light-emitting diode structure. The micro light-emitting diode structure is formed in an array form in the micro light-emitting diode chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro light-emitting diode structure is in the micron range, for example, from 1 micron to 40 microns. Each micro light-emitting diode can form at least a part of the pixel element on the micro light-emitting diode chip. In some embodiments, the micro light-emitting diode array may include blue micro light-emitting diodes. In some embodiments, the micro light-emitting diode array may include green micro light-emitting diodes. In some embodiments, the pitch of the micro light-emitting diode array, that is, the minimum center-to-center distance between micro light-emitting diodes, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0069] In some embodiments, the driving backplane can be electrically connected to each micro light-emitting diode in the micro light-emitting diode array through separate metal interconnections. In some embodiments, each micro light-emitting diode can be individually electrically controlled by the driving backplane. In some embodiments, the driving backplane can be electrically connected to the electrodes of the micro light-emitting diode chip through metal interconnections.

[0070] As Figure 7 shown, in some embodiments, the light-emitting mesa 701 sequentially includes a first type semiconductor layer 711, a light-emitting layer 712, and a second type semiconductor layer 713 from bottom to top. That is to say, in the three-layer structure, the first type semiconductor layer 711 is closest to the driving backplane, the light-emitting layer 712 is located above the first type semiconductor layer 711 and is farther from the driving backplane, and the second type semiconductor layer 713 is located above the light-emitting layer 712 and is the farthest from the driving backplane.

[0071] In some embodiments, the area of the first-type semiconductor layer 711 is smaller than that of the second-type semiconductor layer 713, and thus the cross-section of the light-emitting mesa 701 is an inverted trapezoid or approximately an inverted trapezoid. In some embodiments, the bottom diameter of the light-emitting mesa 701 is 0.9 to 1.3 micrometers, the top diameter is 1.5 to 2.1 micrometers, and its height is 0.4 to 1.1 micrometers.

[0072] In some embodiments, the thickness of the first-type semiconductor layer 711 is 0.1 micrometer to 0.22 micrometers. The second-type semiconductor layer 713 includes a stepped portion 7131 and a base portion 7132, where the stepped portion 7131 is electrically connected to the light-emitting layer 712, and the base portion 7132 extends from the stepped portion 7131 to both sides of the light-emitting mesa 701. In the actual manufacturing process, a relatively thick second-type semiconductor material can be deposited first, and the light-emitting layer 712 and the first-type semiconductor layer 711 are sequentially deposited thereon. Subsequently, etching of each light-emitting mesa is performed, and a certain thickness of the second-type semiconductor material at the bottom is reserved without being etched through, and thus the base portion 7132 can be obtained. In some embodiments, the thickness of the stepped portion 7131 is 0.4 to 0.8 micrometers, and the thickness of the base portion 7132 is 0.1 to 0.8 micrometers. In some embodiments, the thickness of the first-type semiconductor layer 711 is smaller than that of the second-type semiconductor layer 713.

[0073] In some embodiments, the first-type semiconductor layer 711 has a semiconductor material of a first conductivity type and includes multiple semiconductor layers. The main matrix material of the first-type semiconductor layer 711 includes but is not limited to Ga, N, As, P, In, or Al. In addition, the first-type semiconductor layer 711 may include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second-type semiconductor layer 713 has a semiconductor material of a second conductivity type and includes multiple semiconductor layers. The main matrix material of the second-type semiconductor layer 713 may be but is not limited to being composed of materials such as Ga, N, As, P, In, or Al. In addition, the second-type semiconductor layer 713 may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type. In some embodiments, the light-emitting mesa 701 emits blue-green light, the first-type semiconductor layer 711 is an N-type GaN layer, an N-type AlGaN layer, or an N-type InGaN layer, and the second-type semiconductor layer 713 is a P-type GaN layer, a P-type AlGaN layer, or a P-type InGaN layer.

[0074] In some embodiments, the light-emitting layer 712 is formed by a plurality of stacked quantum well layers, particularly superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the light-emitting layer 712 includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm.

[0075] In some embodiments, the light-emitting layer 712 is a multi-quantum well (MQW). For blue-green light-emitting diodes, the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 712 further includes an electron blocking layer, which is disposed on a first side of the quantum well layer. The first side refers to the side along which electrons migrate out of the light-emitting layer 712.

[0076] As Figure 7 shown, in some embodiments, the microLED display chip further includes a bottom electrode 704, which is disposed on the bottom surface of the light-emitting mesa 701, electrically connected to the first-type semiconductor layer 711, and electrically connected to the pixel driving backplane below it. In some embodiments, the bottom electrode 704 is made of a metal material.

[0077] As Figure 7 shown, the passivation layer 702 includes a side surface portion 721 and an extension portion 722. The side surface portion 721 surrounds the side surface of the light-emitting mesa 701, that is, the side surfaces of the first-type semiconductor layer 711, the light-emitting layer 712, and the second-type semiconductor layer 713. The extension portion 722 extends from the side surface of the light-emitting mesa 701 to both sides of the light-emitting mesa 701 to cover the bottom surface of the base portion 7132 of the second-type semiconductor layer 713. The passivation layer 702 is used for electrical isolation between the bottom electrode 704 and the first-type semiconductor layer 711, the light-emitting layer 712, and the second-type semiconductor layer 713. In some embodiments, the passivation layer 702 also covers a partial bottom surface of the first-type semiconductor layer 711. Specifically, it is the edge portion of the bottom surface of the first-type semiconductor layer 711 and forms a protrusion. In some embodiments, there is an opening in the passivation layer 702 on the bottom surface of the first-type semiconductor layer 711, and the bottom electrode 704 is formed in the opening. As described above, the passivation layer 702 includes a first passivation layer and a second passivation layer. The first passivation layer directly covers the light-emitting mesa 701 and includes Al and N. For example, it is made of AlN or Al x Ga y In z N, and its thickness is 10 to 50 nanometers. The second passivation layer is disposed on the first passivation layer and is made of one or a combination of SiO2, Al2O3, and Si3N4.

[0078] As shown Figure 7 in the figure, the microLED display chip further includes a reflective layer 703. The reflective layer 703 is disposed on the surface of the passivation layer 702 and is electrically connected to the bottom electrode 704. In some embodiments, the reflective layer 703 may be a conductive material layer having one or more layers with a high refractive index, which can reflect the light emitted from the light-emitting region, improving the brightness and light efficiency of the micro light-emitting diode chip. For example, the reflective layer 703 may include one or more metal layers, such as Pt, Rh, Al, Au, and Ag, etc., or a stacked DBR layer of TiO2 / SiO2 layers, or any other layer with total reflection characteristics, such as a multi-layer omnidirectional reflector ODR or a combination thereof. In some embodiments, the refractive index of the reflective layer material should be not less than 90%. In addition, in some embodiments, the root mean square roughness of the inner surface of the reflective layer 703 is between 1 and 10 nanometers.

[0079] As shown Figure 7 in the figure, in some embodiments, the microLED display chip further includes a dielectric layer 705. The dielectric layer 705 is disposed between two adjacent light-emitting mesa surfaces, covering the bottom surface of the exposed passivation layer 702 and the outer surface of the reflective layer 703, but exposing the end portion of the bottom electrode 704. In some embodiments, the dielectric layer 705 is made of a light-transmissive insulating material, such as at least one of Al2O3, SiO2, SiON, and SiN materials, etc.

[0080] As shown Figure 7 in the figure, in some embodiments, the microLED display chip further includes a top electrode 706. The top electrode 706 is disposed on the top surface of the base of the second-type semiconductor layer 713, between two adjacent light-emitting mesa surfaces. In some embodiments, the cross-section of the electrode 706 is trapezoidal, and its height is 0.7 to 0.9 micrometers. In some embodiments, the distance between two adjacent electrodes 706 is equal to the pixel pitch. To further improve the light efficiency, in some embodiments, the electrode 706 is made of a conductive material with a high reflectivity, such as Ag, Au, or Al, etc., and the reflectivity of the conductive material to visible light should be not less than 40%.

[0081] To achieve current spreading and connect the second-type semiconductor layers 713 of each semiconductor light-emitting mesa in series, as Figure 7 shown in the figure, the microLED display chip further includes a current spreading layer 707. In some embodiments, the current spreading layer 707 is disposed at the bottom of the top electrode 706. Specifically, the current spreading layer 707 covers the entire top surface of the base layer 7132, and the top electrode 706 is disposed on the current spreading layer 707 and is located between two light-emitting mesa surfaces 701. In some embodiments, the current spreading layer 707 is a transparent conductive layer ITO.

[0082] In some embodiments, the microLED display chip further includes a microlens array composed of a plurality of microlenses 708. The microlenses 708 are arranged corresponding to the light-emitting mesa 701, and the horizontal profile of the microlenses 708 is larger than the maximum horizontal profile of the light-emitting mesa 701. The microlenses 708 are mainly used to converge and / or collimate light. For example, by adjusting parameters such as the thickness and curvature of the microlenses 708, the focal point of the microlenses 708 can be located in the light-emitting mesa 701. In an embodiment of the present invention, the microlens 708 includes an upper curvature portion 781 and a lower spacer portion 782. It should be understood that in some embodiments, the microlens 708 may not include the lower spacer portion. The lower spacer portion 782 covers the top electrode 706, and its height is determined based on the curvature radius, spherical height, etc. of the upper curvature portion 781. In some embodiments, the curvature radius of the upper curvature portion 781 is 1.5 to 2.2 micrometers, and the spherical height is 1.2 to 2 micrometers. Preferably, the upper curvature portion 781 can be, for example, hemispherical or approximately bullet-shaped. In some embodiments, the microlens 708 is made of an insulating material with a light transmittance of not less than 95%, such as SiO 2或 Al2O 3或 SiON or SiN, etc. In some embodiments, the microlens 708 can be formed by multiple depositions. During the formation of the microlens, first, a SiO2 film layer needs to be deposited, and then ion etching is performed.

[0083] Figure 8 The structural schematic diagram of a light-emitting device showing still another embodiment of the present invention is as follows. As Figure 8 shown, the light-emitting device includes the micro light-emitting diode chip as described above, but there are certain differences from the Figure 7 light-emitting device shown.

[0084] As Figure 8 shown, in some embodiments, the micro light-emitting diode structure includes a driving backplane 110, a lower electrode layer 120, a conductive layer 130, a light-emitting mesa 140, an upper electrode layer 150, a passivation layer 160, a microlens 170, and an electrode 180.

[0085] In some embodiments, the lower electrode layer 120 may be a metal bonding composite layer. The light-emitting mesa 140 may be bonded to the surface of the driving backplane 110 through the lower electrode layer 120, and the bonding may be completed by means such as eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding. In some embodiments, the lower electrode layer 120 may be disposed on the driving backplane 110. In another embodiment, the lower electrode layer 120 grows on the driving backplane 110. In some embodiments, the thickness of the lower electrode layer 120 is from 0.1 micrometer to 3 micrometers. In a preferred embodiment, the thickness of the lower electrode layer 120 is 0.3 μm. In some embodiments, the material of the lower electrode layer 120 is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, Ag, and Sn. The lower electrode layer 120 may include an ohmic contact layer and a metal bonding layer. In some cases, the lower electrode layer 120 includes two metal layers. One of the two metal layers is deposited on a layer above the metal bonding layer within the LED. The corresponding bonding metal layer is deposited on the driving backplane 110. For example, the lower electrode layer 120 may be an Au-Au bond, an Au-Sn bond, an Au-In bond, a Ti-Ti bond, a Cu-Cu bond, or a combination of the above. For example, if an Au-Au bond is selected, each of the two Au layers requires a Cr layer as an adhesion layer and a Pt layer as an anti-diffusion layer. The Pt layer is located between the Au layer and the Cr layer. The Cr and Pt layers are located on the top and bottom of the two bonded Au layers. In some embodiments, when the thicknesses of the two Au layers are substantially the same, at high pressure and high temperature, the Au on the two layers diffuses into each other to bond the two layers together.

[0086] In some embodiments, the lower electrode layer 120 may also be used as a mirror to reflect the light emitted from the light-emitting mesa 140 above.

[0087] In some embodiments, the conductive layer 130 is formed on the bottom surface of the light-emitting mesa 140 for forming an electrical connection between the light-emitting mesa 140 and the lower electrode layer 120. In some embodiments, the conductive layer 130 may be a conductive transparent layer that is transparent to the light emitted from the light-emitting mesa 140 to improve conductivity and light transmittance. In some embodiments, the upper electrode layer 150 is formed on the top surface of the light-emitting mesa 140, and the upper electrode layer 150 is electrically connected to a current spreading structure or a top electrode (not shown).

[0088] In some embodiments, the conductive layer 130, the upper electrode layer 150, and their connecting components may be one or more combinations of, for example, graphene, indium tin oxide (ITO), antimony doped zinc oxide (AZO), fluorine doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0089] The light-emitting mesa 140 includes a first-type semiconductor layer 141, a second-type semiconductor layer 143, and a light-emitting layer 142 therebetween. The first-type semiconductor layer 141 is electrically connected to the conductive layer 130. The second-type semiconductor layer 143 is electrically connected to the upper electrode layer 150. The difference between the light-emitting mesa and the light-emitting mesa in the embodiment shown is that the area of the first-type semiconductor layer 141 is larger than the area of the second-type semiconductor layer 143, and thus the cross-section of the light-emitting mesa 140 is a regular trapezoid or approximately a regular trapezoid. That is, there is an inclination angle between the side wall of the light-emitting mesa 140 and the bottom of the light-emitting mesa, and this inclination angle is less than or equal to 90°. In some embodiments, the range of the inclination angle of the side wall of the light-emitting mesa is: 45° to 90°. In some embodiments, the bottom lateral dimension of the light-emitting mesa 140 exceeds 2 micrometers. In some embodiments, the top lateral dimension of the light-emitting mesa 140 does not exceed 1.5 micrometers. In some embodiments, the lateral dimension of the lower electrode layer 120 is larger than the bottom lateral dimension of the light-emitting mesa 140. Figure 7 As shown in the embodiment, the difference between the light-emitting mesa is that the area of the first-type semiconductor layer 141 is larger than the area of the second-type semiconductor layer 143, and thus the cross-section of the light-emitting mesa 140 is a regular trapezoid or approximately a regular trapezoid. That is, there is an inclination angle between the side wall of the light-emitting mesa 140 and the bottom of the light-emitting mesa, and this inclination angle is less than or equal to 90°. In some embodiments, the range of the inclination angle of the side wall of the light-emitting mesa is: 45° to 90°. In some embodiments, the bottom lateral dimension of the light-emitting mesa 140 exceeds 2 micrometers. In some embodiments, the top lateral dimension of the light-emitting mesa 140 does not exceed 1.5 micrometers. In some embodiments, the lateral dimension of the lower electrode layer 120 is larger than the bottom lateral dimension of the light-emitting mesa 140.

[0090] In some embodiments, the electrode polarity of the conductive layer 130 is determined by the first-type semiconductor layer 141, and the electrode polarity of the upper electrode layer 150 is determined by the second-type semiconductor layer 143. The electrode polarity of the conductive layer 130 is opposite to the electrode polarity of the upper electrode layer 150. The conductive layer 130 can be, for example, a P electrode or an anode electrode, and the upper electrode layer 150 is an electrode with a polarity opposite to that of the conductive layer 130, such as an N electrode or a cathode electrode, and vice versa.

[0091] In some embodiments, the passivation layer 160 is the same as the previous passivation layer, which coats the side surfaces of the lower electrode layer 120, the conductive layer 130, and the light-emitting mesa 140. In some embodiments, the passivation layer 160 may also cover a part of the side surface of the upper electrode layer 150, and a part of the top surface of the upper electrode layer 150 is exposed to form an electrical connection with the top electrode. In other embodiments of the present invention, the passivation layer 160 does not cover the top surface and the side surface of the upper electrode layer 150, so that the upper electrode layers 150 of adjacent LED structures can be connected to each other to form a common cathode or anode. In some embodiments, the passivation layer 160 coats the side surfaces of the lower electrode layer 120, the conductive layer 130, the first-type semiconductor layer 141, and the light-emitting layer 142, as well as a part of the side surface of the second-type semiconductor layer 143.

[0092] In some embodiments, the electrode 180 is disposed on the surface of the upper electrode layer 150 and is located between two light-emitting mesas. In some embodiments, the electrode 180 is an annular reflective electrode, which is formed by magnetron sputtering or evaporation, and its material can be, for example, Al or an Al alloy metal for the sidewall reflective mirror surface, and the electrode stack metal can be metal materials such as Ni, Al, Ti, Ni, Pt, Au, etc. In some embodiments, the electrodes are connected to each other.

[0093] The passivation layer as described above and the light-emitting device using the same can be applied to display panels, display systems, and near-eye display devices. Among them, the display panel includes, for example, a light-emitting diode display panel, a micro light-emitting diode display panel, etc., and the display system includes, for example, a light-emitting diode display system, a micro light-emitting diode display system, etc.

[0094] Figure 9 FIG. 10 and FIG. 11 respectively show a flow schematic diagram and a process schematic diagram of a method for preparing a passivation layer of a display chip. In some embodiments, the first passivation layer is formed by atomic layer deposition. Specifically, a method for preparing a passivation layer of a display chip includes:

[0095] First, in step 901, as Figure 11a shown, a semiconductor substrate having a light-emitting layer is provided, where the light-emitting layer contains Ga and N, and can be, for example, GaN; and

[0096] Next, in step 902: A material containing nitrogen and aluminum is deposited on the sidewall of the light-emitting layer to form a passivation layer. In some embodiments, as Figure 10 shown, step 902 includes:

[0097] First, in step 921, as Figure 11b shown, a gas containing an aluminum source, such as trimethylaluminum, etc., is introduced into the semiconductor substrate to adsorb it on the sidewall of the light-emitting layer. In some embodiments, a gas containing an aluminum source and a carrier gas are specifically introduced, where the carrier gas can be, for example, nitrogen, argon, etc.;

[0098] Next, in step 922, as Figure 11c shown, an inert gas is introduced into the semiconductor substrate to flush away the excess trimethylaluminum;

[0099] Next, in step 923, as Figure 11d shown, a gas containing a nitrogen source is introduced into the semiconductor to form a nitrogen-containing and aluminum-containing material. For example, if the gas containing a nitrogen source is NH3, it can react with trimethylaluminum to form AlN. In some embodiments, by-products such as methane are also produced during this process; and

[0100] Finally, in step 924, as Figure 11e shown, the inert gas is introduced into the semiconductor substrate again to flush away the by-products and the excess gas containing the nitrogen source.

[0101] In some embodiments, steps 921 to 924 are repeated several times to gradually increase the thickness of the passivation layer.

[0102] It should be understood that in some other embodiments, other thin film preparation processes such as physical vapor deposition, chemical vapor deposition, etc. can also be used to form the first passivation layer, and the formation process of the second passivation layer can be the same as or different from that of the first passivation layer.

[0103] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It will be apparent to those skilled in the relevant art that various combinations, modifications, and changes can be made to them without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined only by the appended claims and their equivalents.

Claims

1. A passivation layer of a display chip, the display chip having a light-emitting layer; characterized in that, The passivation layer includes: A first passivation layer located on the sidewalls of the light-emitting layer; the material of the first passivation layer is a material containing nitrogen and aluminum.

2. The passivation layer of the display chip according to claim 1, wherein: The first passivation layer at least coats the sidewall surfaces of the light-emitting layer.

3. The passivation layer of the display chip according to claim 2, wherein The first passivation layer has a cup shape.

4. The passivation layer of the display chip according to claim 2, wherein, The first passivation layer is a continuous thin film layer with cup-shaped protrusions.

5. The passivation layer of the display chip according to claim 1, wherein: The material of the first passivation layer is Al x Ga y In z N, where x + y + z = 1.

6. The passivation layer of the display chip according to claim 5, wherein: The value range of x is from 0.7 to 1.0, the value range of y is from 0 to 0.2, and the value range of z is from 0 to 0.

1.

7. The passivation layer of the display chip according to claim 1, wherein: The material used for the first passivation layer is AlN.

8. The passivation layer of the display chip according to claim 1, wherein: The thickness range of the first passivation layer is from 10 to 50 nm.

9. The passivation layer of the display chip according to claim 1, wherein: It further includes a second passivation layer, and the second passivation layer is disposed on the first passivation layer.

10. The passivation layer of the display chip according to claim 9, wherein: The material of the second passivation layer is one or a combination of SiO2, Al2O3, and Si3N4.

11. The passivation layer of the display chip according to claim 1, wherein: The light-emitting layer includes a multi-layer stacked quantum well light-emitting layer.

12. The passivation layer of the display chip according to claim 11, characterized in that, The light-emitting layer contains gallium and nitrogen.

13. A microLED display chip, characterized in that: It includes the passivation layer of the display chip according to any one of claims 1 to 11.

14. The display chip according to claim 13, wherein It further includes: A microLED light-emitting mesa array; wherein, each microLED light-emitting mesa includes: A first-type semiconductor layer; The light-emitting layer located on the first-type semiconductor layer; A second-type semiconductor layer located on the light-emitting layer.

15. The display chip according to claim 14, wherein The passivation layer at least coats the sidewall surfaces of the first-type semiconductor layer, the light-emitting layer, and the second-type semiconductor layer.

16. The display chip according to claim 14, wherein: It further includes: A top electrode located above the second-type semiconductor layer and electrically connected to the second-type semiconductor layer; A bottom electrode located below the first-type semiconductor layer and electrically connected to the first-type semiconductor layer.

17. The display chip according to claim 16, wherein, It further includes: A pixel driving backplane located below the bottom electrode and electrically connected to the bottom electrode.

18. A microLED display device, characterized in that: It includes the passivation layer of the display chip according to any one of claims 1 to 11.

19. A method for preparing a passivation layer of a display chip according to any one of claims 1 to 11, characterized in that, It includes: Step 01: Provide a semiconductor substrate having a light-emitting layer; Step 02: Deposit a material containing nitrogen and aluminum on the sidewalls of the light-emitting layer.

20. The method for preparing a passivation layer according to claim 19, wherein, The step 02 includes: Step 201: Introduce a gas containing an aluminum source into the semiconductor substrate; Step 202: Introduce an inert gas into the semiconductor substrate; Step 203: Introduce a gas containing a nitrogen source into the semiconductor to form a material containing nitrogen and aluminum.

21. The method for preparing a passivation layer according to claim 20, wherein, The step 02 further includes: repeating steps 201 to 203 several times.

22. The method for preparing a passivation layer according to claim 20, wherein, The gas containing an aluminum source in step 201 is trimethylaluminum; the gas containing a nitrogen source in step 203 is NH3.

23. The method for preparing a passivation layer according to claim 20, wherein By-products are also formed in the step 203, and after the step 02, the method further includes: removing the by-products.

24. The method for preparing a passivation layer according to claim 23, wherein The by-product of the step 203 is methane.

25. The method for preparing a passivation layer according to claim 20, wherein In the step 201, the gas containing an aluminum source is adsorbed on the semiconductor substrate.

26. The method for preparing a passivation layer according to claim 20, wherein The semiconductor substrate is a substrate made of a material containing nitrogen and gallium.

27. The method for preparing a passivation layer according to claim 20, wherein, In the step 201, a gas containing an aluminum source and a carrier gas are specifically introduced.

28. The method for preparing a passivation layer according to claim 27, wherein In the step 201, the carrier gas is nitrogen or argon.

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