Electronic device
By specifically configuring the conductor patterns of inductors and capacitors in the multi-layer conductor layer, the thickness problem caused by the increase of the conductor layer is solved, and appropriate inductance and capacitance characteristics are achieved in a limited area, improving the reliability and characteristic performance of the LC filter device.
Patent Information
- Application Number
- CN202380078294.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-03-24
- Filing Date
- 2023-12-06
- Publication Date
- 2025-07-04
AI Technical Summary
In the conventional LC filter devices, the increase in the conductor layer causes the product thickness to increase, and sufficient characteristics are difficult to achieve when an inductor and capacitor are formed on the same conductor layer.
In the electronic devices of multiple conductor layers, the conductor patterns of the inductor and capacitor are arranged in such a way that partially overlap and partially do not overlap in the lamination direction by specifically configuring the conductor patterns, so as to form appropriate inductors and capacitors.
Appropriate inductor and capacitor characteristics are achieved in a limited area, suppressing the overall number of layers while improving product reliability and characteristic performance.
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Figure CN120266232A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to an electronic device including an inductor and a capacitor. Background Art
[0002] A chip-type LC filter device integrating an inductor and a capacitor is disclosed in Patent Document 1.
[0003] Prior Art Documents
[0004] Patent Documents
[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2018-125514 Summary of the Invention
[0006] (I) Technical Problem to be Solved
[0007] In the LC filter device disclosed in Patent Document 1, the conductor pattern forming the inductor and the conductor pattern forming the capacitor are formed on different conductor layers. In such a structure, if the number of conductor layers increases, the thickness (height) of the product increases. On the other hand, if the conductor pattern forming the inductor and the conductor pattern forming the capacitor are formed on the same conductor layer, sufficient characteristics (inductance or capacitance) may not be obtained depending on the size (area) of the mounting area.
[0008] In the present disclosure, a technique is described in which, in an electronic device having a plurality of conductor layers, the conductor patterns forming an inductor and a capacitor are arranged in such a way as to achieve appropriate characteristics.
[0009] (II) Technical Solution
[0010] An electronic device according to one aspect of the present disclosure includes: a first conductor layer including a first lower electrode pattern and a first inductor pattern; a first upper electrode pattern covering the first lower electrode pattern via a dielectric film; a first insulating layer covering the first conductor layer and the first upper electrode pattern; and a second conductor layer provided on the first insulating layer and including a second inductor pattern, the second inductor pattern being connected to the first inductor pattern via a first through hole provided in the first insulating layer. In a plan view observed from the stacking direction, the first upper electrode pattern includes a first region and a second region, the first region overlapping the second inductor pattern, and the second region not overlapping either the first core region or the second inductor pattern, where the first core region is surrounded by the first inductor pattern and the second inductor pattern.
[0011] (III) Advantageous Effects
[0012] According to the present disclosure, the following technology is provided: in an electronic device having a plurality of conductor layers, the conductor patterns constituting inductors and capacitors are arranged in a manner that achieves appropriate characteristics. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 FIG. is a schematic perspective view showing the appearance of an electronic device (LC filter device 100) according to an embodiment of the technology of the present disclosure.
[0014] Figure 2 FIG. is a schematic cross-sectional view of the LC filter device 100.
[0015] Figure 3 FIG. is an equivalent circuit diagram of the LC filter device 100.
[0016] Figure 4 FIG. is a schematic top view showing the pattern shapes of the conductor layers M1 and MM.
[0017] Figure 5 FIG. is a schematic top view showing the pattern shape of the conductor layer M2.
[0018] Figure 6 FIG. is a schematic top view showing the pattern shape of the conductor layer M3.
[0019] Figure 7 FIG. is a schematic top view showing the pattern shape of the conductor layer M4.
[0020] Figure 8 FIG. is a schematic top view showing the pattern shape of the conductor layer M5.
[0021] Figure 9 FIG. is a schematic top view showing the state in which the conductor layers M1, MM, M2 to M5 are overlapped. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0022] Hereinafter, embodiments of the technology of the present disclosure will be described in detail with reference to the accompanying drawings.
[0023] Figure 1 FIG. is a schematic perspective view showing the appearance of an electronic device (LC filter device) 100 according to an embodiment of the technology of the present disclosure. In addition, Figure 2 FIG. is a schematic cross-sectional view of the LC filter device 100.
[0024] Figure 1 The LC filter device 100 shown is a surface-mounted chip device, as Figure 1As shown in the figure, it includes: a substrate 10; an insulating layer 20, which is composed of an organic insulating material such as polyimide formed on the surface of the substrate 10; and a plurality of terminal electrodes, which are formed on the surface of the insulating layer 20. The terminal electrodes include signal terminals S1, S2 and ground terminals G1, G2. As Figure 2 shown, the surface of the substrate 10 is covered with a planarization layer 11, and a plurality of conductor layers M1 to M4, MM covered by the insulating layer 20 are provided on the planarization layer 11. The signal terminals S1, S2 and the ground terminals G1, G2 are formed on the uppermost conductor layer M5. The insulating layer 20 includes four insulating layers 21 to 24.
[0025] As the material of the substrate 10, any material can be used as long as it is chemically stable, thermally stable, generates less stress, and can maintain the smoothness of the surface. There is no particular limitation, and single-crystalline silicon, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO3 single crystal, surface silicon oxide, glass, quartz, ferrite, etc. can be used. As the planarization layer 11, alumina, silicon oxide, etc. can be used.
[0026] Figure 3 is the equivalent circuit diagram of the LC filter device 100 of the present embodiment.
[0027] As Figure 3 shown, the LC filter device 100 of the present embodiment has: a capacitor C1 and an inductor L1, which are connected in parallel between the signal terminal S1 and the internal node N; a capacitor C2 and an inductor L2, which are connected in parallel between the signal terminal S2 and the internal node N; a capacitor C3, which is connected between the signal terminal S1 and the ground terminals G1, G2; a capacitor C4, which is connected between the internal node N and the ground terminals G1, G2; and a capacitor C5, which is connected between the signal terminal S2 and the ground terminals G1, G2. With this circuit structure, the LC filter device 100 of the present embodiment functions as a low-pass filter.
[0028] Next, the structures of the conductor layers M1 to M5, MM included in the LC filter device 100 will be described. In addition, Figures 4 - 9 the A-A line shown in the figure represents Figure 2 the cross-sectional position. In addition, in Figures 4 - 9 the X direction and the Y direction are shown for easy explanation.
[0029] The conductor layer M1 is the lowermost conductor layer. As Figure 4As shown, it includes conductor patterns 31 to 36. The conductor pattern 31 includes: a connection pattern 31A that overlaps with the signal terminal S1 in a plan view observed from the stacking direction; a lower electrode pattern 31B; and an inductor pattern 31C. The lower electrode pattern 31B is connected to an end (edge) of the connection pattern 31A in the X direction, and one end of the inductor pattern 31C is connected to an edge of the connection pattern 31A in the Y direction. In a plan view observed from the stacking direction, the inductor pattern 31C is arranged to surround (wind) about 3 / 4 of a turn along the core region D2. In other words, the core region D2 is surrounded by the wound inductor pattern 31C.
[0030] The conductor pattern 32 includes: a connection pattern 32A that overlaps with the signal terminal S2 in a plan view observed from the stacking direction; a lower electrode pattern 32B; and an inductor pattern 32C. The lower electrode pattern 32B is connected to an edge of the connection pattern 32A in the X direction, and one end of the inductor pattern 32C is connected to an edge of the connection pattern 32A in the Y direction. In a plan view observed from the stacking direction, the inductor pattern 32C is arranged to surround (wind) about 1 / 2 of a turn along the core region D1. In other words, the core region D1 is surrounded by the wound inductor pattern 32C.
[0031] The conductor pattern 34 includes: a connection pattern 34A that overlaps with the ground terminal G1 in a plan view observed from the stacking direction; and a lower electrode pattern 34B. The lower electrode pattern 34B is connected to an edge of the connection pattern 34A in the X direction. In a plan view observed from the stacking direction, the conductor pattern 36 overlaps with the ground terminal G2.
[0032] The conductor pattern 33 is a lower electrode pattern arranged between the connection pattern 31A and the connection pattern 34A in the Y direction. The conductor pattern 35 is a lower electrode pattern arranged between the connection pattern 32A and the conductor pattern 36 in the Y direction. The connection patterns 31A, 32A, 34A, the conductor pattern 36, the other end of the inductor pattern 31C, and the other end of the inductor pattern 32C are connected to the conductor layer M2 on the upper layer (the layer on the terminal electrode side) in the stacking direction via conduction parts (vias) V31, V32, V34, V36, V2, and V1 respectively provided in the insulating layer 21.
[0033] As Figure 2 shown, the surface of the conductor layer M1 is covered with a dielectric film 12 made of, for example, silicon nitride, and a conductor layer MM is provided on the dielectric film 12. As Figure 4As shown, the conductor layer MM includes upper electrode patterns 41, 42, 43A, 43B, 44, 45A, and 45B. The upper electrode pattern 41 is disposed at a position overlapping with the lower electrode pattern 31B. The upper electrode pattern 42 is disposed at a position overlapping with the lower electrode pattern 32B. The upper electrode patterns 43A and 43B are disposed at a position overlapping with the lower electrode pattern 33. The upper electrode pattern 44 is disposed at a position overlapping with the lower electrode pattern 34B. The upper electrode patterns 45A and 45B are disposed at a position overlapping with the lower electrode pattern 35.
[0034] Thus, a capacitor C1 is formed by the lower electrode pattern 31B, the upper electrode pattern 41, and the dielectric film 12. A capacitor C2 is formed by the lower electrode pattern 32B, the upper electrode pattern 42, and the dielectric film 12. A capacitor C3 is formed by the lower electrode pattern 33, the upper electrode patterns 43A and 43B, and the dielectric film 12. A capacitor C4 is formed by the lower electrode pattern 34B, the upper electrode pattern 44, and the dielectric film 12. A capacitor C5 is formed by the lower electrode pattern 35, the upper electrode patterns 45A and 45B, and the dielectric film 12.
[0035] The area of the upper electrode pattern 42 is larger than that of the upper electrode pattern 41. Thus, the capacitance of the capacitor C2 is larger than that of the capacitor C1. The upper electrode patterns 41, 42, 43A, 43B, 44, 45A, and 45B are connected to the upper conductor layer M2 via through holes V41, V42, V43A, V43B, V44, V45A, and V45B respectively provided in the insulating layer 21.
[0036] The conductor layer M2 is located above the conductor layers M1 and MM in the stacking direction with the insulating layer 21 therebetween, as Figure 5As shown, it includes conductor patterns 51 to 59. The conductor pattern 51 is connected to the connection pattern 31A of the conductor layer M1 and the upper electrode pattern 43A via the through holes V31 and V43A provided in the insulating layer 21. The conductor pattern 52 is connected to the connection pattern 32A of the conductor layer M1 and the upper electrode pattern 45A via the through holes V32 and V45A provided in the insulating layer 21. The conductor pattern 54 is connected to the connection pattern 34A of the conductor layer M1 and the upper electrode pattern 43B via the through holes V34 and V43B provided in the insulating layer 21. The conductor pattern 56 is connected to the connection pattern 36 of the conductor layer M1 and the upper electrode pattern 45B of the conductor layer MM via the through holes V36 and V45B provided in the insulating layer 21. The conductor pattern 53 is connected to the upper electrode pattern 41 of the conductor layer MM via the through hole V41 provided in the insulating layer 21. The conductor pattern 55 is connected to the upper electrode pattern 42 of the conductor layer MM via the through hole V42 provided in the insulating layer 21. The conductor pattern 57 is an inductor pattern connected to the other end of the inductor pattern 31C of the conductor layer M1 via the through hole V2 provided in the insulating layer 21. The conductor pattern 58 is an inductor pattern connected to the other end of the inductor pattern 32C of the conductor layer M1 via the through hole V1 provided in the insulating layer 21. The conductor pattern 59 is connected to the upper electrode pattern 44 of the conductor layer MM via the through hole V44 provided in the insulating layer 21. The conductor patterns 51 to 58 are connected to the upper conductor layer M3 via the through holes V51 to V57 and V3 provided in the insulating layer 22 respectively. The conductor pattern 59 is connected to the upper conductor layer M3 via the through holes V59A and V59B provided in the insulating layer 22.
[0037] When viewed from above in the stacking direction, the conductor pattern 57, which is an inductor pattern, surrounds the core region D2 by about one turn. In other words, the core region D2 is surrounded by the conductor pattern 57. When viewed from above in the stacking direction, the conductor pattern 58, which is an inductor pattern, surrounds the core region D1 by about three-quarters of a turn. In other words, the core region D1 is surrounded by the conductor pattern 58.
[0038] In Figure 5 the positions overlapping with the lower electrode patterns 31B and 32B and the upper electrode patterns 41 and 42 are indicated by dashed lines. As Figure 5 shown, the edge of the lower electrode pattern 31B along the extending direction of the inductor pattern 57 ( Figure 5 the X direction in Figure 5The edge in the X direction (in ) overlaps with the inductor pattern 58, but the lower electrode pattern 32B is not disposed at a position overlapping with the core region D1. Similarly, the edge of the upper electrode pattern 42 along the extending direction of the inductor pattern 58 ( Figure 5 in the X direction) overlaps with the inductor pattern 58, but the upper electrode pattern 42 is not disposed at a position overlapping with the core region D1. In Figure 4 , the position overlapping with the outer peripheral edge of the inductor pattern 58 is indicated by a dashed line. As Figure 4 shown, in a plan view observed from the stacking direction, the upper electrode pattern 42 includes a first region 42A and a second region 42B. The first region 42A overlaps with the inductor pattern 58, and the second region 42B is located in an outer region on the opposite side of the core region D1 when observed from the inductor pattern 58. In a plan view observed from the stacking direction, the second region 42B does not overlap with either the inductor pattern 58 or the core region D1. Thus, by disposing a part of the upper electrode pattern 42 to overlap with the inductor pattern 58, both the area of the upper electrode pattern 42 and the area of the core region D1 can be appropriately ensured. In other words, the upper electrode pattern 42 and the core region D1 having appropriate sizes can be formed in a limited region according to the characteristics required for the inductor L2 and the capacitor C2.
[0039] The conductor layer M3 is located above the conductor layer M2 with the insulating layer 22 therebetween, and as Figure 6 shown, includes conductor patterns 61 to 68. The conductor patterns 61, 62, 64, 66 are connected to the connection patterns 51, 52, 54, 56 of the conductor layer M2 via through holes V51, V52, V54, V56 respectively provided in the insulating layer 22. The conductor patterns 63, 65 are connected to the conductor patterns 53, 55 of the conductor layer M2 via through holes V53, V55 respectively provided in the insulating layer 22. The conductor pattern 67 includes an inductor pattern 67A and a connection pattern 67B. The inductor pattern 67A is connected to the other end of the inductor pattern 57 of the conductor layer M2 via a through hole V57 provided in the insulating layer 22. The connection pattern 67B is connected to the conductor pattern 59 of the conductor layer M2 via through holes V59A, V59B provided in the insulating layer 22. The conductor pattern 68 is an inductor pattern connected to the other end of the inductor pattern 58 of the conductor layer M2 via a through hole V3 provided in the insulating layer 22.
[0040] In a plan view observed from the stacking direction, the inductor pattern 67A surrounds the core region D2 for about one turn. In other words, the core region D2 is surrounded by the inductor pattern 67A. In a plan view observed from the stacking direction, the conductor pattern 68 as an inductor pattern surrounds the core region D1 for about one turn. In other words, the core region D1 is surrounded by the inductor pattern 68.
[0041] In Figure 6The position overlapping with the lower electrode patterns 31B, 32B and the upper electrode patterns 41, 42 is indicated by a dashed line. As Figure 6 shown, the edge of the lower electrode pattern 31B along the extending direction of the inductor pattern 67A ( Figure 6 the X direction in ) approaches the outer peripheral edge of the inductor pattern 67A. In addition, the edge of the lower electrode pattern 31B may also be substantially consistent with the outer peripheral edge of the inductor pattern 67A. The upper electrode pattern 41 does not overlap with the inductor pattern 67A, and the entire upper electrode pattern 41 is located in the outer region on the side opposite to the core region D2 when viewed from the inductor pattern 67A. The edge of the lower electrode pattern 32B along the extending direction of the inductor pattern 68 ( Figure 6 the X direction in ) overlaps with the inductor pattern 68, but the lower electrode pattern 32B is not arranged at the position overlapping with the core region D1. Similarly, the edge of the upper electrode pattern 42 along the extending direction of the inductor pattern 68 overlaps with the inductor pattern 68, but the upper electrode pattern 42 is not arranged at the position overlapping with the core region D1. In Figure 4 the position overlapping with the outer peripheral edge of the inductor pattern 68 is indicated by a dashed line. The connection pattern 67B is connected to the upper conductor layer M4 through the through holes V67A, V67B provided in the insulating layer 23.
[0042] The conductor layer M4 is located above the conductor layer M3 with the insulating layer 23 in between, as Figure 7 shown, and includes conductor patterns 71 to 74, 76. The conductor patterns 71, 72, 74, 76 are connected to the connection patterns 61, 62, 64, 66 of the conductor layer M3 through the through holes V61, V62, V64, V66 provided in the insulating layer 23 respectively. The conductor pattern 73 includes connection patterns 73A to 73C and an inductor pattern 73D. The connection pattern 73A is connected to the connection pattern 67B of the conductor layer M3 through the through holes V67A, V67B provided in the insulating layer 23. The connection patterns 73B, 73C are connected to the conductor patterns 63, 65 of the conductor layer M3 through the through holes V63, V65 provided in the insulating layer 23 respectively. Thus, the upper electrode patterns 41, 42 are electrically connected through the connection pattern 73. When viewed from above in the stacking direction, the inductor pattern 73D surrounds the core region D1 by about 1 / 4 turn and is connected to the other end of the inductor pattern 68 of the conductor layer M3 through the through hole V68 provided in the insulating layer 23. The conductor patterns 71, 72, 74, 76 are connected to the conductor layer M5 through the through holes V71, V72, V74, V76 provided in the insulating layer 24 respectively.
[0043] The conductor layer M5 is located above the conductor layer M4 with the insulating layer 24 in between, as Figure 8As shown, it includes signal terminals S1, S2 and ground terminals G1, G2. The signal terminals S1, S2 are connected to conductor patterns 71, 72 of the conductor layer M4 via through holes V71, V72 respectively provided in the insulating layer 24. The ground terminals G1, G2 are connected to conductor patterns 74, 76 of the conductor layer M4 via through holes V74, V76 respectively provided in the insulating layer 24. Surface treatment for improving wettability with respect to solder may also be performed on the surfaces of the signal terminals S1, S2 and the ground terminals G1, G2.
[0044] With the above pattern structure, the inductor L1 is composed of inductor patterns 31C, 57, 67A, and the inductor L2 is composed of inductor patterns 32C, 58, 68, 73D. Moreover, one ends of the inductors L1, L2 are respectively connected to the signal terminals S1, S2, and the other ends of the inductors L1, L2 are electrically connected via the conductor pattern 73 forming the internal node N. The coil length of the inductor L2 is slightly longer than that of the inductor L1. Therefore, the inductance of the inductor L2 is slightly larger than that of the inductor L1. As described above, the capacitance of the capacitor C2 is larger than that of the capacitor C1. Thus, appropriate attenuation characteristics, insertion loss, return loss and other characteristics can be achieved according to the specifications required by the LC filter device 100.
[0045] When viewed from above in the stacking direction, the inductor patterns 31C, 57, 67A forming the inductor L1 surround along the common core region D2. In other words, the core region D2 is surrounded by the inductor patterns 31C, 57, 67A. When viewed from above in the stacking direction, the inductor patterns 32C, 58, 68, 73D forming the inductor L2 surround along the common core region D1. In other words, the core region D1 is surrounded by the inductor patterns 32C, 58, 68, 73D.
[0046] Here, the lower electrode pattern 32B and the upper electrode pattern 42 forming the capacitor C2 extend to the vicinity of the core region D1. As a result, a part of the lower electrode pattern 32B and a part of the upper electrode pattern 42 overlap with the upper inductor patterns 58, 68. With such a layout, by arranging a part of the inductor L2 and the lower electrode pattern 32B of the capacitor C2 on the same conductor layer M1, the number of layers of the entire electronic device can be suppressed while appropriately ensuring the inductance of the inductor L2 and the capacitance of the capacitor C2. In other words, by arranging a part of the conductor pattern forming the inductor to overlap with the capacitor electrode, an inductor and a capacitor with appropriate characteristics can be formed in a certain limited area (for example, height (thickness), mounting area).
[0047] Moreover, the lower electrode pattern 32B and the upper electrode pattern 42 do not overlap with the core region D1. Therefore, the lower electrode pattern 32B and the upper electrode pattern 42 are less likely to obstruct the magnetic flux generated by the inductor L2. The same applies to the inductor L1 and the capacitor C1. The lower electrode pattern 31B and the upper electrode pattern 41 do not overlap with the core region D2. Therefore, the lower electrode pattern 31B and the upper electrode pattern 41 are less likely to obstruct the magnetic flux generated by the inductor L1.
[0048] Furthermore, the lower electrode pattern 31B and the inductor pattern 31C are edge-connected to the connection pattern 31A such that their extending directions are different from each other by 90°. In Figure 4 the case of the specific example shown, the lower electrode pattern 31B is edge-connected to the edge on the terminal S2 side in the connection pattern 31A, and the inductor pattern 31C is edge-connected to the edge on the terminal G1 side in the connection pattern 31A. Thereby, the lower electrode pattern 31B and the inductor pattern 31C can be efficiently arranged within a limited area. Similarly, the lower electrode pattern 32B and the inductor pattern 32C are edge-connected to the connection pattern 32A such that their extending directions are different from each other by 90°. In Figure 4 the case of the specific example shown, the lower electrode pattern 32B is edge-connected to the edge on the terminal S1 side in the connection pattern 32A, and the inductor pattern 32C is edge-connected to the edge on the terminal G2 side in the connection pattern 32A. Thereby, the lower electrode pattern 32B and the inductor pattern 32C can be efficiently arranged within a limited area. In addition, as shown in Figure 9 the state where the conductor layers M1, MM, M2 to M5 are overlapped, conductor patterns constituting the inductors L1, L2, and capacitors C1 to C5 are not arranged at positions overlapping the signal terminals S1, S2 and the ground terminals G1, G2. Therefore, even when stress is applied to the signal terminals S1, S2, and the ground terminals G1, G2 from the outside, peeling, cracks, etc. are less likely to occur, and the reliability of the product can be improved.
[0049] As described above, the LC filter device 100 of the present embodiment is configured such that both the lower electrode pattern 32B of the capacitor C2 and the inductor pattern 32C of the inductor L2 are formed on the conductor layer M1 located at the lowermost layer, and the upper electrode pattern 42 provided on the conductor layer MM overlaps with the inductor pattern 58 of the inductor L2 provided on the conductor layer M2. Therefore, the overall number of layers can be suppressed, and the inductance of the inductor L2 and the capacitance of the capacitor C2 can be appropriately ensured.
[0050] As described above, embodiments of the technology of the present disclosure have been described. However, the technology of the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof, and of course, these are also included in the scope of the technology of the present disclosure.
[0051] For example, in the above-described embodiment, the lower electrode pattern 31B and the upper electrode pattern 41 constituting the capacitor C1 do not overlap with the inductor pattern 57 of the inductor L1. However, depending on the capacitance required for the capacitor C1, one or both of them may be arranged to overlap with the inductor pattern 57.
[0052] In addition, in the above-described embodiment, an LC filter device is illustrated, but the technology of the present disclosure is not limited thereto, and can also be applied to other devices including capacitors and inductors (for example, power dividers, distributors, couplers, etc.).
[0053] The technology of the present disclosure includes the following structural examples, but is not limited thereto.
[0054] An electronic device according to an aspect of the present disclosure includes: a first conductor layer including a first lower electrode pattern and a first inductor pattern; a first upper electrode pattern covering the first lower electrode pattern via a dielectric film; a first insulating layer covering the first conductor layer and the first upper electrode pattern; and a second conductor layer provided on the first insulating layer and including a second inductor pattern, the second inductor pattern being connected to the first inductor pattern via a first through hole provided in the first insulating layer. In a plan view observed from the stacking direction, the first upper electrode pattern includes a first region and a second region. The first region overlaps with the second inductor pattern, and the second region does not overlap with the first core region and the second inductor pattern, where the first core region is surrounded by the first inductor pattern and the second inductor pattern. Thus, the overall number of layers can be suppressed while sufficiently ensuring inductance and capacitance.
[0055] In the above-described electronic device, in a plan view observed from the stacking direction, the second region of the first upper electrode pattern may be located in an outer region of the first inductor pattern and the second inductor pattern on the side opposite to the first core region with respect to the first region. Thus, the second region of the first upper electrode pattern is less likely to interfere with the magnetic flux generated by the first inductor pattern and the second inductor pattern.
[0056] In the above-described electronic device, the edge of the first upper electrode pattern along the circumferential direction of the second inductor pattern may overlap with the second inductor pattern. Thus, the first upper electrode pattern is less likely to interfere with the magnetic flux generated by the first inductor pattern and the second inductor pattern.
[0057] In the above-described electronic device, the first upper electrode pattern may not be formed at a position overlapping with the first core region. Thus, the first upper electrode pattern is even less likely to interfere with the magnetic flux generated by the first inductor pattern and the second inductor pattern.
[0058] In the above-described electronic device, it is also possible that the first lower electrode pattern is not formed at a position overlapping with the first core region. Thus, the first lower electrode pattern is less likely to impede the magnetic flux generated by the first inductor pattern and the second inductor pattern.
[0059] The above-described electronic device may also include a first terminal electrode. The first conductor layer further includes a first connection pattern that overlaps with and is electrically connected to the first terminal electrode. The first lower electrode pattern and the first inductor pattern are connected via the first connection pattern. When viewed from above in the stacking direction, the first lower electrode pattern, the first inductor pattern, and the first connection pattern are formed at non-overlapping positions with each other. Thus, inductors and capacitors with appropriate characteristics can be formed in a limited area that does not overlap with the first terminal electrode, and peeling, cracks, etc. are less likely to occur even when stress is applied to the first terminal electrode from the outside.
[0060] The above-described electronic device may also include: a second insulating layer that covers the second conductor layer; and a third conductor layer that is provided on the second insulating layer and includes a third inductor pattern. The third inductor pattern is connected to the second inductor pattern via a third via provided in the second insulating layer. When viewed from above in the stacking direction, the third inductor pattern winds around the first core region. When viewed from above in the stacking direction, a part of the first upper electrode pattern overlaps with the third inductor pattern. Thus, a larger inductance can be obtained.
[0061] The above-described electronic device may also include a second terminal electrode. The first conductor layer further includes a second lower electrode pattern, a third inductor pattern, and a second connection pattern that is connected to the second terminal electrode. When viewed from above in the stacking direction, the second connection pattern is disposed at a position overlapping with the second terminal electrode. The second lower electrode pattern is covered by the second upper electrode pattern via a dielectric film. The second conductor layer further includes a fourth inductor pattern and a fourth connection pattern. The fourth inductor pattern is connected to the third inductor pattern via a second via provided in the first insulating layer. The fourth connection pattern overlaps with and is connected to the second terminal electrode. When viewed from above in the stacking direction, a second core region surrounded by the third inductor pattern and the fourth inductor pattern is formed. Thus, a low-pass filter including two resonators can be constituted.
[0062] The above-described electronic device may further include: a second insulating layer that covers the second conductor layer; and a third conductor layer that is provided on the second insulating layer and includes a fifth inductor pattern and a sixth inductor pattern. The fifth inductor pattern is connected to the second inductor pattern via a third through hole provided in the second insulating layer, and the sixth inductor pattern is connected to the fourth inductor pattern via a fourth through hole provided in the second insulating layer. In a plan view observed from the stacking direction, the fifth inductor pattern winds around the first core region. In a plan view observed from the stacking direction, a part of the first upper electrode pattern overlaps with the fifth inductor pattern. In a plan view observed from the stacking direction, the sixth inductor pattern winds around the second core region. Thereby, a larger inductance can be obtained.
[0063] The above-described electronic device may further include: a third insulating layer that covers the third conductor layer; and a fourth conductor layer that is provided on the third insulating layer and is formed with a fifth connection pattern. Via the fifth connection pattern, the fifth inductor pattern is electrically connected to the sixth inductor pattern, and the first upper electrode pattern is electrically connected to the second upper electrode pattern. Thereby, since the pattern for electrically connecting the two inductors and the capacitor is arranged on a conductor layer different from the conductor layer on which each inductor pattern is formed, a larger opening of each inductor pattern can be ensured.
[0064] In the above-described electronic device, it may also be that the inductance of the first inductor including the first inductor pattern and the second inductor pattern is greater than the inductance of the second inductor including the third inductor pattern and the fourth inductor pattern, and the first upper electrode pattern is larger than the second upper electrode pattern. Thereby, characteristics such as attenuation characteristics, insertion loss, and return loss can be improved.
[0065] This application claims the priority of Japanese Patent Application No. 2023-048118 filed on March 24, 2023, the entire disclosure of which is incorporated herein by reference.
[0066] Description of reference numerals:
[0067] 10: Substrate; 11: Planarization layer; 12: Dielectric film; 20 - 24: Insulating layer; 31 - 36: Conductor pattern; 31A, 32A, 34A: Connection pattern; 31B, 32B, 33, 34A, 34B, 35: Lower electrode pattern; 31C, 32C, 57, 58, 67A, 68, 73D: Inductor pattern; 41, 42, 43A, 43B, 44, 45A, 45B: Upper electrode pattern; 51 - 59: Conductor pattern; 61 - 68: Conductor pattern; 67B: Connection pattern; 71 - 74, 76: Conductor pattern; 73A - 73C: Connection pattern; 100: Electronic device (LC filter device); C1 - C5: Capacitor; D1, D2: Core region; G1, G2: Ground terminal; L1, L2: Inductor; M1 - M5, MM: Conductor layer; N: Internal node; S1, S2: Signal terminal; V1 - V3, V31, V32, V34, V36, V41, V42, V43A, V43B, V44, V45A, V45B, V51 - V57, V59A, V59B, V61 - V66, V67A, V67B, V68, V71, V72, V74, V76: Via hole.
Claims
1. An electronic device, comprising: A first conductor layer including a first lower electrode pattern and a first inductor pattern; A first upper electrode pattern covering the first lower electrode pattern via a dielectric film; A first insulating layer covering the first conductor layer and the first upper electrode pattern; And A second conductor layer disposed on the first insulating layer and including a second inductor pattern, the second inductor pattern being connected to the first inductor pattern via a first through hole provided in the first insulating layer, In a plan view observed from the stacking direction, the first upper electrode pattern includes a first region and a second region, the first region overlapping with the second inductor pattern, and the second region not overlapping with the first core region and the second inductor pattern, wherein the first core region is surrounded by the first inductor pattern and the second inductor pattern.
2. The electronic device according to claim 1, wherein In a plan view observed from the stacking direction, the second region of the first upper electrode pattern is located in an outer region of the first inductor pattern and the second inductor pattern on the side opposite to the first core region with respect to the first region.
3. The electronic device according to claim 2, wherein An edge of the first upper electrode pattern along the circumferential direction of the second inductor pattern overlaps with the second inductor pattern.
4. The electronic device according to claim 3, wherein The first upper electrode pattern is not formed at a position overlapping with the first core region.
5. The electronic device according to claim 4, wherein The first lower electrode pattern is not formed at a position overlapping with the first core region.
6. The electronic device according to claim 1, wherein A first terminal electrode is further provided, The first conductor layer further includes a first connection pattern, the first connection pattern overlapping with the first terminal electrode and being electrically connected to the first terminal electrode, The first lower electrode pattern and the first inductor pattern are connected via the first connection pattern, and in a plan view observed from the stacking direction, the first lower electrode pattern, the first inductor pattern, and the first connection pattern are formed at non-overlapping positions with each other.
7. The electronic device according to any one of claims 1 to 6, wherein Further provided are: A second insulating layer covering the second conductor layer; and A third conductor layer disposed on the second insulating layer and including a third inductor pattern, the third inductor pattern being connected to the second inductor pattern via a third through hole provided in the second insulating layer, In a plan view observed from the stacking direction, the third inductor pattern winds around the first core region, In a plan view observed from the stacking direction, a part of the first upper electrode pattern overlaps with the third inductor pattern.
8. The electronic device according to claim 6, wherein A second terminal electrode is further provided, The first conductor layer further includes a second lower electrode pattern, a third inductor pattern, and a second connection pattern electrically connected to the second terminal electrode. In a plan view observed from the stacking direction, the second connection pattern is disposed at a position overlapping the second terminal electrode. The second lower electrode pattern is covered by a second upper electrode pattern via a dielectric film. The second conductor layer further includes a fourth inductor pattern, and the fourth inductor pattern is connected to the third inductor pattern via a second through hole provided in the first insulating layer. In a plan view observed from the stacking direction, a second core region surrounded by the third inductor pattern and the fourth inductor pattern is formed.
9. The electronic device according to claim 8, wherein: further comprising: a second insulating layer covering the second conductor layer; and a third conductor layer disposed on the second insulating layer and including a fifth inductor pattern and a sixth inductor pattern, the fifth inductor pattern is connected to the second inductor pattern via a third through hole provided in the second insulating layer, the sixth inductor pattern is connected to the fourth inductor pattern via a fourth through hole provided in the second insulating layer, In a plan view observed from the stacking direction, the fifth inductor pattern winds along the first core region. In a plan view observed from the stacking direction, a part of the first upper electrode pattern overlaps the fifth inductor pattern. In a plan view observed from the stacking direction, the sixth inductor pattern winds along the second core region.
10. The electronic device according to claim 9, wherein: further comprising: a third insulating layer covering the third conductor layer; and a fourth conductor layer disposed on the third insulating layer and having a fifth connection pattern formed thereon, Via the fifth connection pattern, the fifth inductor pattern is electrically connected to the sixth inductor pattern, and the first upper electrode pattern is electrically connected to the second upper electrode pattern.
11. The electronic device according to claim 8, wherein: the inductance of a first inductor including the first inductor pattern and the second inductor pattern is greater than the inductance of a second inductor including the third inductor pattern and the fourth inductor pattern, the first upper electrode pattern is larger than the second upper electrode pattern.
Citation Information
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