Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor (100) is provided with: a capacitor body (1) in which a plurality of dielectric layers (2), a plurality of first internal electrodes (3), and a plurality of second internal electrodes (4) are laminated; a first via conductor (5) provided inside the capacitor body (1) and electrically connected to the plurality of first internal electrodes (3); a second via conductor (6) provided inside the capacitor body (1) and electrically connected to the plurality of second internal electrodes (4); a first external electrode (11) that is provided on at least one of a first main surface (1a) and a second main surface (1b), which face each other in the stacking direction, among the surfaces of the capacitor body (1), and that is connected to the first via conductor (5); a second external electrode (12) provided on at least one main surface of the capacitor body (1) and connected to the second via conductor (6); and a first metal layer (21) provided on a side surface of the capacitor body (1) and electrically connected to the first via conductor (5).

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor. Background Art

[0002] There are known multilayer capacitors in which the ESL (equivalent series inductance) is reduced by making the current flow path thicker, making the current flow path shorter, canceling out magnetic fields that generate currents with different polarities, and the like. In Patent Document 1, an example of a multilayer capacitor with reduced ESL is disclosed.

[0003] The multilayer capacitor disclosed in Patent Document 1 includes a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated. In the capacitor body, a plurality of first via conductors that are electrically connected to the plurality of first internal electrodes and extend to one main surface of the capacitor body, and a plurality of second via conductors that are electrically connected to the plurality of second internal electrodes and extend to one main surface of the capacitor body are provided. On one main surface of the capacitor body, a plurality of first external electrodes that are respectively electrically connected to the plurality of first via conductors, and a plurality of second external electrodes that are respectively electrically connected to the plurality of second via conductors are provided.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2006-135333 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] Here, when manufacturing the multilayer capacitor described in Patent Document 1 above, a method of forming the first external electrode and the second external electrode by plating treatment based on the rotary plating method can be considered. In the barrel plating method, which is an example of the rotary plating method, for example, a large number of capacitor bodies and a large number of conductive media are placed in a rotatable barrel, the barrel is rotated in a plating solution, and electricity is applied, whereby plating is formed in a plating formation region where the first via conductor and the second via conductor are exposed on the surface of the capacitor body. The conductive medium is, for example, a metal sphere. According to the rotary plating method, the first external electrode and the second external electrode can be formed on the surfaces of a large number of capacitor bodies by a single plating treatment, and thus a large number of multilayer capacitors can be formed at once.

[0009] However, the regions where the first via conductor and the second via conductor are exposed on the surface of the capacitor body are regions with a small area, and thus it is possible to manufacture a multilayer capacitor in which the conductive medium does not come into contact with the plating formation region during the plating treatment and no plating film is formed, or the plating film is not sufficiently formed.

[0010] The present invention is used to solve the above problems, and its object is to provide a multilayer ceramic capacitor capable of more reliably forming an external electrode using a rotary plating method.

[0011] Technical solution for solving the problem

[0012] The multilayer ceramic capacitor of the present invention is characterized by comprising:

[0013] A capacitor body, in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated;

[0014] A first via conductor, disposed inside the capacitor body and electrically connected to the plurality of first internal electrodes;

[0015] A second via conductor, disposed inside the capacitor body and electrically connected to the plurality of second internal electrodes;

[0016] A first external electrode, disposed on at least one of the first main surface and the second main surface that are opposite in the lamination direction of the dielectric layer, the first internal electrode, and the second internal electrode among the surfaces of the capacitor body, and connected to the first via conductor;

[0017] A second external electrode, disposed on the at least one main surface of the capacitor body and connected to the second via conductor; and

[0018] A first metal layer, disposed on the side surface that is a surface other than the first main surface and the second main surface of the capacitor body and electrically connected to the first via conductor.

[0019] The multilayer ceramic capacitor in another aspect of the present invention is characterized by comprising:

[0020] A capacitor body, in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated;

[0021] A first via conductor, disposed inside the capacitor body and electrically connected to the plurality of first internal electrodes;

[0022] A second via conductor, disposed inside the capacitor body and electrically connected to the plurality of second internal electrodes;

[0023] A first external electrode, disposed on at least one of the first main surface and the second main surface that are opposite in the lamination direction of the dielectric layer, the first internal electrode, and the second internal electrode among the surfaces of the capacitor body, and connected to the first via conductor;

[0024] The second external electrode is disposed on at least one main surface of the capacitor body and is connected to the second via conductor;

[0025] The first metal layer is disposed on a side surface that is a surface of the capacitor body other than the first main surface and the second main surface, and is electrically connected to the first via conductor; and

[0026] The second metal layer is disposed on the side surface of the capacitor body and is electrically connected to the second via conductor.

[0027] Advantages of the Invention

[0028] In the multilayer ceramic capacitor according to the present invention, since the first metal layer electrically connected to the first via conductor is disposed on the side surface of the capacitor body, the formation of the external electrode by spin plating can be performed more reliably. That is, during spin plating, plating can be performed in the plating formation region not only when the conductive medium abuts against the plating formation region where the first via conductor is exposed, but also when the conductive medium abuts against the first metal layer. Therefore, the first external electrode can be formed more reliably.

[0029] Furthermore, in the multilayer ceramic capacitor according to another aspect of the present invention, since the first metal layer electrically connected to the first via conductor and the second metal layer electrically connected to the second via conductor are disposed on the side surface of the capacitor body, the formation of the external electrode by spin plating can be performed more reliably. That is, during spin plating, plating can be performed in the plating formation region not only when the conductive medium abuts against the plating formation regions where the first via conductor and the second via conductor are exposed, but also when the conductive medium abuts against the first metal layer and the second metal layer. Therefore, the first external electrode and the second external electrode can be formed more reliably. Description of the Drawings

[0030] Figure 1 (a) is a top view schematically showing a multilayer ceramic capacitor according to a first embodiment of the present invention, Figure 1 and (b) is a bottom view schematically showing the multilayer ceramic capacitor according to the first embodiment.

[0031] Figure 2 is a side view when observing the multilayer ceramic capacitor shown Figure 1 in the direction of arrow Y1.

[0032] Figure 3 is a cross-sectional view schematically showing the structure when cutting the multilayer ceramic capacitor shown Figure 1 along line III-III.

[0033] Figure 4FIG. (a) is a top view schematically showing the first internal electrode. Figure 4 FIG. (b) is a top view schematically showing the second internal electrode.

[0034] Figure 5 FIGS. (a) to (d) are partial enlarged views schematically showing various examples of the positional relationship between the second metal layer and the second connection layer. Figure 5 FIGS. (e) to (h) are partial enlarged views schematically showing examples of the shape of the second connection layer corresponding to FIGS. (a) to (d) respectively. Figure 5 FIGS. (a) to (d) respectively.

[0035] Figure 6 is a side view schematically showing a state in which the multilayer ceramic capacitor in the first embodiment is mounted on a mounting substrate.

[0036] Figure 7 FIG. (a) is a top view schematically showing the first internal electrode in the case where the first connection layer and the second connection layer are provided in one layer respectively. Figure 7 FIG. (b) is a top view schematically showing the second internal electrode in the case where the first connection layer and the second connection layer are provided in one layer respectively.

[0037] Figure 8 FIG. (a) is a top view schematically showing the first internal electrode and the first connection layer in the case where the first connection layer is provided but the second connection layer is not provided in the layer where the first internal electrode is provided. Figure 8 FIG. (b) is a top view schematically showing the second internal electrode and the second connection layer in the case where the second connection layer is provided but the first connection layer is not provided in the layer where the second internal electrode is provided.

[0038] Figure 9 is a flowchart for explaining an example of a method for manufacturing a multilayer ceramic capacitor.

[0039] Figure 10 FIG. (a) is a top view schematically showing the multilayer ceramic capacitor in the second embodiment. Figure 10 FIG. (b) is a bottom view schematically showing the multilayer ceramic capacitor in the second embodiment.

[0040] Figure 11 is a side view when observing the multilayer ceramic capacitor shown in Figure 10 in the direction of arrow Y2.

[0041] Figure 12 FIG. (a) is a top view schematically showing the first internal electrode of the multilayer ceramic capacitor in the second embodiment. Figure 12 FIG. (b) is a top view schematically showing the second internal electrode.

[0042] Figure 13 (a) schematically shows a top view of a multilayer ceramic capacitor in the third embodiment, Figure 13 and (b) schematically shows a bottom view of the multilayer ceramic capacitor.

[0043] Figure 14 (a) schematically shows a top view of a first internal electrode of the multilayer ceramic capacitor in the third embodiment, Figure 14 and (b) schematically shows a top view of a second internal electrode.

[0044] Figure 15 (a) schematically shows a top view of a multilayer ceramic capacitor in the fourth embodiment, Figure 15 and (b) schematically shows a bottom view of the multilayer ceramic capacitor.

[0045] Figure 16 as viewed in the direction of arrow Y3 Figure 15 is a side view of the multilayer ceramic capacitor shown.

[0046] Figure 17 (a) schematically shows a top view of a first internal electrode of the multilayer ceramic capacitor in the fourth embodiment, Figure 17 and (b) schematically shows a top view of a second internal electrode.

[0047] Figure 18 is a modified example of the multilayer ceramic capacitor in the fourth embodiment, Figure 18 where (a) schematically shows a top view of the first internal electrode and the first connection layer in the case where the first connection layer is provided in the layer where the first internal electrode is provided but the second connection layer is not provided, Figure 18 and (b) schematically shows a top view of the second internal electrode and the second connection layer in the case where the second connection layer is provided in the layer where the second internal electrode is provided but the first connection layer is not provided.

[0048] Figure 19 is a top view of a multilayer ceramic capacitor schematically showing another configuration pattern of external electrodes in the case where the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is odd.

[0049] Figure 20 (a) and (b) respectively schematically show top views of a multilayer ceramic capacitor showing another configuration pattern of external electrodes in the case where the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd.

[0050] Figure 21Figs. (a) and (b) are top views of a multilayer ceramic capacitor schematically showing another configuration pattern of external electrodes when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is even. Detailed Description of the Invention

[0051] Embodiments of the present invention will be described below, and the features of the present invention will be specifically described.

[0052] <First Embodiment>

[0053] Figure 1 Fig. (a) is a top view schematically showing a multilayer ceramic capacitor 100 in the first embodiment of the present invention. Figure 1 Fig. (b) is a bottom view schematically showing the multilayer ceramic capacitor 100 in the first embodiment. Here, the first main surface 1a of the capacitor body 1 to be described later is referred to as the upper surface, and the second main surface 1b is referred to as the lower surface. Figure 2 It is a side view when observing Figure 1 the multilayer ceramic capacitor 100 shown in the direction of arrow Y1. Figure 3 Fig. is a schematic cross-sectional view showing the structure when cutting along line III-III Figure 1 the multilayer ceramic capacitor 100 shown.

[0054] The multilayer ceramic capacitor 100 includes a capacitor body 1, a first via conductor 5, a second via conductor 6, a first external electrode 11, a second external electrode 12, and a first metal layer 21. The multilayer ceramic capacitor 100 in the present embodiment further includes a second metal layer 22. In addition, the multilayer ceramic capacitor 100 in the present embodiment further includes a first connection layer 31 and a second connection layer 32.

[0055] As Figure 3 shown, the capacitor body 1 has a structure in which a plurality of dielectric layers 2, a plurality of first internal electrodes 3, and a plurality of second internal electrodes 4 are laminated. More specifically, the capacitor body 1 has a structure in which a plurality of first internal electrodes 3 and second internal electrodes 4 are alternately laminated with the dielectric layer 2 interposed therebetween.

[0056] The material of the dielectric layer 2 is arbitrary. For example, it includes a ceramic material mainly composed of BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3. Minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components in an amount less than the main component.

[0057] The shape of the capacitor body 1 is arbitrary. In the present embodiment, the capacitor body 1 has a shape that is generally a rectangular parallelepiped. The so-called shape that is generally a rectangular parallelepiped means, for example, a shape in which the corners and edges of the rectangular parallelepiped have rounded corners, or a shape in which there are irregularities on the surface of the rectangular parallelepiped. Although it is not a completely rectangular parallelepiped shape, it has six surfaces and is a shape that can be generally captured as a rectangular parallelepiped. Therefore, the capacitor body 1 includes a first main surface 1a, a second main surface 1b, a first side surface 1c, a second side surface 1d, a third side surface 1e, and a fourth side surface 1f.

[0058] The first main surface 1a and the second main surface 1b of the capacitor body 1 are surfaces that face each other in the stacking direction T of the dielectric layer 2, the first internal electrode 3, and the second internal electrode 4. The first side surface 1c to the fourth side surface 1f of the capacitor body 1 constitute four side surfaces among the surfaces of the capacitor body 1 that are other than the first main surface 1a and the second main surface 1b. The first side surface 1c faces the third side surface 1e, and the second side surface 1d faces the fourth side surface 1f. In the present embodiment, although the first side surface 1c to the fourth side surface 1f of the capacitor body 1 are orthogonal to the first main surface 1a and the second main surface 1b respectively, they may not be orthogonal.

[0059] The size of the capacitor body 1 is arbitrary. For example, the longitudinal dimension of the capacitor body 1 that is rectangular in plan view in the stacking direction T can be set to be 0.3 mm or more and 3.0 mm or less, the lateral dimension can be set to be 0.3 mm or more and 3.0 mm or less, and the dimension in the stacking direction T can be set to be 50 μm or more and 200 μm or less. The so-called dimension of the capacitor body 1 in the stacking direction T is the thickness of the capacitor body 1.

[0060] Figure 4 (a) is a plan view schematically showing the first internal electrode 3, Figure 4 (b) is a plan view schematically showing the second internal electrode 4. In Figure 4 (a) and (b), the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown together. In addition, in Figure 4 (a), the second connection layer 32 described later is shown together, and in Figure 4 (b), the first connection layer 31 described later is shown together.

[0061] As Figure 4 shown in (a) and (b), in the present embodiment, the shape of the dielectric layer 2 when observed in the stacking direction T is rectangular. The shape of the first internal electrode 3 when observed in the stacking direction T is not rectangular. Specifically, as Figure 4As shown in (a) thereof, the first internal electrode 3 has a shape obtained by removing a pair of corners from a rectangle. The shape of the removed corner portion is, for example, a rectangle. Further, the shape of the second internal electrode 4 when viewed in the stacking direction T is not a rectangle. Specifically, as Figure 4 shown in (b) thereof, the second internal electrode 4 has a shape obtained by removing a pair of corners from a rectangle. The shape of the removed corner portion is, for example, a rectangle. However, the shape of the first internal electrode 3 is not limited to Figure 4 the shape shown in (a) thereof, and the shape of the second internal electrode 4 is not limited to Figure 4 the shape shown in (b) thereof.

[0062] The materials of the first internal electrode 3 and the second internal electrode 4 are arbitrary. For example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals can be used. As a common material, the first internal electrode 3 and the second internal electrode 4 may also contain the same ceramic material as the dielectric ceramic contained in the dielectric layer 2. In this case, the proportion of the common material contained in the first internal electrode 3 and the second internal electrode 4 is, for example, 20 vol% or less.

[0063] The thicknesses of the first internal electrode 3 and the second internal electrode 4 are arbitrary. For example, they can be set to a level of 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode 3 and the second internal electrode 4 is arbitrary. For example, the total number of layers of the first internal electrode 3 and the second internal electrode 4 can be set to a level of 10 layers or more and 150 layers or less.

[0064] The multilayer ceramic capacitor 100 forms a capacitance by opposing the first internal electrode 3 and the second internal electrode 4 with the dielectric layer 2 interposed therebetween.

[0065] The first via conductor 5 and the second via conductor 6 are provided inside the capacitor body 1. In the present embodiment, as Figure 1 described, a plurality of first via conductors 5 and a plurality of second via conductors 6 are arranged in a matrix. More specifically, four via conductors including two first via conductors 5 and two second via conductors 6 are provided at positions corresponding to the four corners of the capacitor body 1 that is rectangular when viewed from above in the stacking direction T. However, the arrangement of the first via conductor 5 and the second via conductor 6 is not limited to the matrix arrangement. Further, the number of the first via conductors 5 and the number of the second via conductors 6 are not limited to two, and can be set to any number.

[0066] As Figure 3As shown, the first via conductor 5 is disposed inside the capacitor body 1 so as to extend in the stacking direction T from the first main surface 1a of the capacitor body 1 toward the second main surface 1b, and is electrically connected to a plurality of first internal electrodes 3. The first via conductor 5 is separated from the second internal electrode 4 and insulated from the second internal electrode 4.

[0067] As Figure 3 shown, the second via conductor 6 is disposed inside the capacitor body 1 so as to extend in the stacking direction T from the first main surface 1a of the capacitor body 1 toward the second main surface 1b, and is electrically connected to a plurality of second internal electrodes 4. The second via conductor 6 is separated from the first internal electrode 3 and insulated from the first internal electrode 3.

[0068] As Figure 3 shown, the first via conductor 5 and the second via conductor 6 are not exposed on the second main surface 1b of the capacitor body 1, but may be exposed.

[0069] The materials of the first via conductor 5 and the second via conductor 6 are arbitrary. For example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals can be used.

[0070] The shapes of the first via conductor 5 and the second via conductor 6 are arbitrary. For example, they are cylindrical. In this case, the diameters of the first via conductor 5 and the second via conductor 6 are, for example, on the order of 30 μm or more and 150 μm or less.

[0071] The first external electrode 11 is provided on at least one of the first main surface 1a and the second main surface 1b of the surfaces of the capacitor body 1 and is connected to the first via conductor 5. In the present embodiment, the first via conductor 5 is exposed on the first main surface 1a of the capacitor body 1, and the first external electrode 11 is provided on the first main surface 1a of the capacitor body 1. More specifically, the first external electrode 11 is provided at a position overlapping the first via conductor 5 in the stacking direction T. The number of the first external electrodes 11 is the same as the number of the first via conductors 5, and is two in the Figure 1 shown example. However, the number of the first external electrodes 11 is not limited to two. As described above, the first via conductor 5 is electrically connected to a plurality of first internal electrodes 3, so the first external electrode 11 is electrically connected to a plurality of first internal electrodes 3.

[0072] The second external electrode 12 is provided on at least one of the main surfaces of the capacitor body 1 and is connected to the second via conductor 6. In the present embodiment, the second via conductor 6 is exposed on the first main surface 1a of the capacitor body 1. Similarly to the first external electrode 11, the second external electrode 12 is provided on the first main surface 1a of the capacitor body 1. More specifically, the second external electrode 12 is provided at a position overlapping the second via conductor 6 in the stacking direction T. The number of the second external electrodes 12 is the same as the number of the second via conductors 6, and in the example shown in Figure 1 it is two. However, the number of the second external electrodes 12 is not limited to two. As described above, the second via conductor 6 is electrically connected to a plurality of second internal electrodes 4, and thus the second external electrode 12 is electrically connected to the plurality of second internal electrodes 4.

[0073] Alternatively, the structure may be such that the first via conductor 5 and the second via conductor 6 are respectively also exposed on the second main surface 1b of the capacitor body 1, and the first external electrode 11 and the second external electrode 12 are respectively also provided on the second main surface 1b.

[0074] The materials of the first external electrode 11 and the second external electrode 12 are arbitrary. In the present embodiment, the first external electrode 11 and the second external electrode 12 are plating electrodes formed by plating treatment using a rotary plating method. Examples of the material constituting the plating electrode include Cu, Ni, Sn, etc. The plating electrode may be composed of a single layer or multiple layers.

[0075] The first metal layer 21 is provided on the side surface among the surfaces of the capacitor body 1 and is electrically connected to the first via conductor 5. In the present embodiment, as shown in Figure 1 the first metal layer 21 is provided at the corner positions of the capacitor body 1 that span from the first side surface 1c to the second side surface 1d and from the third side surface 1e to the fourth side surface 1f. However, the position where the first metal layer 21 is provided is not limited to the positions shown in Figure 1 the figure.

[0076] The second metal layer 22 is provided on the side surface among the surfaces of the capacitor body 1 and is electrically connected to the second via conductor 6. In the present embodiment, as shown in Figure 1 the second metal layer 22 is provided at the corner positions of the capacitor body 1 that span from the second side surface 1d to the third side surface 1e and from the fourth side surface 1f to the first side surface 1c. However, the position where the second metal layer 22 is provided is not limited to the positions shown in Figure 1 the figure.

[0077] The materials of the first metal layer 21 and the second metal layer 22 are arbitrary. In the present embodiment, the first metal layer 21 and the second metal layer 22 are plating layers formed by plating treatment using a rotary plating method. Examples of the material constituting the plating layer include Cu, Ni, Sn, etc. The plating layer may be composed of a single layer or multiple layers.

[0078] In the multilayer ceramic capacitor 100 in the present embodiment, a first connection layer 31 for electrically connecting the first via conductor 5 and the first metal layer 21, and a second connection layer 32 for electrically connecting the second via conductor 6 and the second metal layer 22 are provided inside the capacitor body 1. The first connection layer 31 and the second connection layer 32 have a planar shape extending in a direction orthogonal to the stacking direction T.

[0079] In the present embodiment, as shown in Figure 4 FIG. (b), the first connection layer 31 is provided in the same layer as the second internal electrode 4. The first connection layer 31 may be provided in all of the layers where the second internal electrode 4 is provided, or may be provided only in a part of the layers. As shown in Figure 4 FIG. (a), the second connection layer 32 is provided in the same layer as the first internal electrode 3. The second connection layer 32 may be provided in all of the layers where the first internal electrode 3 is provided, or may be provided only in a part of the layers.

[0080] As shown in Figure 4 FIG. (b), the first connection layer 31 is in contact with the first via conductor 5, but is separated from the second internal electrode 4. As shown in Figure 4 FIG. (a), the second connection layer 32 is in contact with the second via conductor 6, but is separated from the first internal electrode 3.

[0081] The shapes of the first connection layer 31 and the second connection layer 32 are arbitrary. In the present embodiment, as shown in Figure 4 FIG. (b), the first connection layer 31 has a quarter - circle shape. Further, as shown in Figure 4 FIG. (a), the second connection layer 32 has a quarter - circle shape.

[0082] The materials of the conductive first connection layer 31 and the second connection layer 32 are arbitrary. For example, the same materials as those of the first internal electrode 3 and the second internal electrode 4 can be used.

[0083] In the manufacturing process of the multilayer ceramic capacitor 100, the first connection layer 31 and the second connection layer 32 are exposed on the side surface of the capacitor body 1 before the first metal layer 21 and the second metal layer 22 are provided. The first metal layer 21 is provided in a manner that covers the first connection layer 31 exposed on the side surface of the capacitor body 1. In addition, the second metal layer 22 is provided in a manner that covers the second connection layer 32 exposed on the side surface of the capacitor body 1.

[0084] The shape of the first metal layer 21 can be changed by changing the shape of the portion of the first connection layer 31 that is exposed on the side surface of the capacitor body 1. Similarly, the shape of the second metal layer 22 can be changed by changing the shape of the portion of the second connection layer 32 that is exposed on the side surface of the capacitor body 1.

[0085] Figure 5 (a) schematically shows Figures 1 - 3 a partially enlarged view of the positional relationship between the second metal layer 22 and the second connection layer 32 of the multilayer ceramic capacitor 100 shown in Figure 5 (b), (c), and (d) schematically show Figure 5 partially enlarged views of the positional relationships between the second metal layer 22 and the second connection layer 32 having shapes different from that of (a). In addition, Figure 5 (e) to (h) schematically show Figure 5 partially enlarged views of an example of the shape of the second connection layer 32 corresponding to (a) to (d). In Figure 5 (e) to (h), a part of the dielectric layer 2, the first internal electrode 3, and the second via conductor 6 is also shown.

[0086] Figure 5 Compared with the structure shown in (b) of Figure 5 (a), the area of the second metal layer 22 is small. As can be seen by comparing Figure 5 (e) of Figure 5 (f), by reducing the area of the portion of the second connection layer 32 that is exposed on the side surface of the capacitor body 1, the area of the second metal layer 22 can be reduced. Although not shown in the figure, the same applies to the first metal layer 21 and the first connection layer 31.

[0087] In Figure 5 the structure shown in (c), two second metal layers 22 are provided on one side surface of the capacitor body 1. The two second metal layers 22 are provided at separated positions. In Figure 5In (c), a state is shown where two second metal layers 22 are provided on the first side surface 1c of the capacitor body 1. However, the structure where two second metal layers 22 are provided can also be similarly set on the second side surface 1d, the third side surface 1e, and the fourth side surface 1f. To achieve this structure, as shown in Figure 5 (g), the second connection layer 32 has a shape that exposes at two positions on one side surface of the capacitor body 1. Although the figure is omitted, the first metal layer 21 and the first connection layer 31 are the same. In addition, the number of the first metal layers 21 and the number of the second metal layers 22 provided on one side surface of the capacitor body 1 are not limited to two, and may be three or more.

[0088] In Figure 5 In the structure shown in (d), the second metal layer 22 is provided only in the region on the first main surface 1a side of the side surfaces of the capacitor body 1 where the first external electrode 11 and the second external electrode 12 are provided. That is, when the side surface of the capacitor body 1 is divided into a region on the first main surface 1a side and a region on the second main surface 1b side, the second metal layer 22 is provided only in the region on the first main surface 1a side. In this case, the second connection layer 32 only needs to be provided in the layer on the first main surface 1a side in the stacking direction T. In addition, as shown in Figure 5 (h), the shape of the second connection layer 32 can be set to the same shape as the shape of the second connection layer 32 shown in Figure 5 (b).

[0089] As described later, when the multilayer ceramic capacitor 100 in the present embodiment is mounted on a mounting substrate, the first metal layer 21 and the second metal layer 22 can also be joined to the land electrodes of the mounting substrate via solder. According to the structure shown in Figure 5 (d), in the region where welding is not performed during the mounting of the multilayer ceramic capacitor 100, the first metal layer 21 and the second metal layer 22 are not provided, so the structure can be simplified and the manufacturing cost can be reduced.

[0090] According to the multilayer ceramic capacitor 100 in the present embodiment, the first metal layer 21 electrically connected to the first via conductor 5 and the second metal layer 22 electrically connected to the second via conductor 6 are provided on the side surface of the capacitor body 1, so that the formation of the external electrodes by rotary plating can be performed more reliably. As described later, during rotary plating, plating can be performed in the plating formation region not only when the conductive medium abuts against the plating formation region where the first via conductor 5 and the second via conductor 6 are exposed on the surface of the capacitor body 1, but also when the conductive medium abuts against the first metal layer 21 and the second metal layer 22. Therefore, the first external electrode 11 and the second external electrode 12 can be formed more reliably.

[0091] In addition, in the multilayer ceramic capacitor 100 according to the present embodiment, when mounting on a mounting substrate, not only the first external electrode 11 and the second external electrode 12 but also the first metal layer 21 and the second metal layer 22 are joined to the land electrode of the mounting substrate, thereby enabling stable mounting.

[0092] Figure 6 FIG. 4 is a side view schematically showing a state in which the multilayer ceramic capacitor 100 according to the present embodiment is mounted on a mounting substrate 200. The first external electrode 11 and the second external electrode 12 of the multilayer ceramic capacitor 100 are respectively joined to the land electrodes 210 of the mounting substrate 200 via solder 220. In addition, the first metal layer 21 and the second metal layer 22 provided on the side surface of the capacitor body 1 are respectively joined to the land electrodes 210 of the mounting substrate 200 via solder 220. In addition to the first external electrode 11 and the second external electrode 12, the first metal layer 21 and the second metal layer 22 are also joined to the land electrodes 210 of the mounting substrate 200, so that more stable mounting can be performed.

[0093] In addition, the first metal layer 21 and the second metal layer 22 are joined to the land electrodes 210 of the mounting substrate 200 via solder 220, whereby it is also possible to visually confirm whether the multilayer ceramic capacitor 100 is mounted.

[0094] (Modification 1 of the First Embodiment)

[0095] As shown in FIGS. 5(a) and 5(b), the first connection layer 31 and the second connection layer 32 are alternately provided in different layers, but it is also possible to adopt a structure in which the first connection layer 31 and the second connection layer 32 are provided in the same layer. Figure 4 In FIGS. 5(a) and 5(b), a top view of the first internal electrode 3 in the case where the first connection layer 31 and the second connection layer 32 are provided in the same layer is schematically shown, and a top view of the second internal electrode 4 is schematically shown in FIG. 5(b). In FIGS. 5(a) and 5(b), the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connection layer 31, and the second connection layer 32 are also shown together.

[0096] In Figure 7 As shown in FIG. 5(a), in the layer where the first internal electrode 3 is provided, the first connection layer 31 is provided together with the second connection layer 32. The first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not directly in contact with the first internal electrode 3. Figure 7 In FIG. 5(b), a top view of the second internal electrode 4 is schematically shown. In FIGS. 5(a) and 5(b), the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connection layer 31, and the second connection layer 32 are also shown together. Figure 7 In FIGS. 5(a) and 5(b), the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connection layer 31, and the second connection layer 32 are also shown together.

[0097] As Figure 7 As shown in FIG. 5(a), in the layer where the first internal electrode 3 is provided, the first connection layer 31 is provided together with the second connection layer 32. The first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not directly in contact with the first internal electrode 3.

[0098] AsFigure 7 As shown in FIG. (b), in the layer where the second internal electrode 4 is provided, the second connection layer 32 is provided together with the first connection layer 31. The second connection layer 32 is connected to the second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connection layer 32 is not directly connected to the second internal electrode 4.

[0099] In this structural example, compared with the structural examples shown in FIGS. (a) and (b) of Figure 4 the number of the first connection layers 31 that connect the first via conductor 5 and the first metal layer 21, and the number of the second connection layers 32 that connect the second via conductor 6 and the second metal layer 22 are increased. Therefore, the electrical connection between the first via conductor 5 and the first metal layer 21 via the first connection layer 31 and the electrical connection between the second via conductor 6 and the second metal layer 22 via the second connection layer 32 become more reliable, and when the first external electrode 11 and the second external electrode 12 are formed by spin coating, they can be formed more reliably.

[0100] In addition, since the first connection layer 31 is not directly connected to the first internal electrode 3, it is possible to suppress the intrusion of the plating solution from the outside to the inside during manufacturing, and to suppress the intrusion of moisture and the like from the outside to the inside of the finished product. That is, in the structure where the first connection layer 31 is directly connected to the first internal electrode 3, the plating solution, moisture, etc. are likely to intrude from the outside of the capacitor body 1 along the first connection layer 31 and the first internal electrode 3 to the inside, but by separating the first connection layer 31 from the first internal electrode 3, it is possible to suppress the intrusion of the plating solution, moisture, etc. to the inside. Similarly, since the second connection layer 32 is not directly connected to the second internal electrode 4, it is possible to suppress the intrusion of the plating solution, moisture, etc. from the outside of the capacitor body 1 to the inside.

[0101] In addition, when comparing the structure shown in FIGS. (a) and (b) of Figure 4 with the structure shown in FIGS. (a) and (b) of Figure 7 in one layer, the internal electrode and the connection layer are completely separated. Therefore, according to the structure shown in FIGS. (a) and (b) of Figure 4 it is possible to more effectively suppress the intrusion of the plating solution, moisture, etc. from the outside of the capacitor body 1 to the inside.

[0102] (Modification 2 of the first embodiment)

[0103] In the structure shown in FIGS. (a) and (b) of Figure 4 the second connection layer 32 is provided in the layer where the first internal electrode 3 is provided, and the first connection layer 31 is provided in the layer where the second internal electrode 4 is provided, but it can also be set to the following structure, that is, the first connection layer 31 is provided in the layer where the first internal electrode 3 is provided, and the second connection layer 32 is provided in the layer where the second internal electrode 4 is provided. InFigure 8 FIG. (a) schematically shows a top view of the first internal electrode 3 and the first connection layer 31 in this case. In Figure 8 FIG. (b) schematically shows a top view of the second internal electrode 4 and the second connection layer 32. In Figure 8 In FIGS. (a) and (b), the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown together.

[0104] As Figure 8 shown in FIG. (a), the first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not directly in contact with the first internal electrode 3. As Figure 8 shown in FIG. (a), the second connection layer 32 is not provided in the layer where the first internal electrode 3 is provided.

[0105] As Figure 8 shown in FIG. (b), the second connection layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connection layer 32 is not directly in contact with the second internal electrode 4. As Figure 8 shown in FIG. (b), the first connection layer 31 is not provided in the layer where the second internal electrode 4 is provided.

[0106] According to Figure 8 the structures shown in FIGS. (a) and (b), compared with the structures shown in FIGS. (a) and (b) of Figure 7 , the number of the first connection layer 31 and the second connection layer 32 can be reduced to about half. Therefore, when manufacturing, it is possible to suppress the invasion of the plating solution from the outside to the inside, and it is possible to suppress the invasion of moisture and the like from the outside of the finished product to the inside. That is, at the positions where the first connection layer 31 and the second connection layer 32 are exposed among the side surfaces of the capacitor body 1, although the plating solution and moisture are likely to invade the inside, since the number of the first connection layer 31 and the second connection layer 32 is small, the invasion of the plating solution, moisture, etc. into the inside can be suppressed. This is the same in the structures shown in FIGS. (a) and (b) of Figure 4 .

[0107] (Method for manufacturing a multilayer ceramic capacitor)

[0108] Refer to Figure 9 the flowchart shown to explain an example of the method for manufacturing the above-described multilayer ceramic capacitor 100.

[0109] In Figure 9 step S1, a ceramic green sheet, a conductive paste for an internal electrode, and a conductive paste for a connection layer are respectively prepared. The ceramic green sheet can be a known ceramic green sheet. For example, it can be obtained by coating a ceramic slurry containing a ceramic powder, a resin component, and a solvent on a substrate and drying it.

[0110] The conductive paste for internal electrodes is a conductive paste used to form the first internal electrode 3 and the second internal electrode 4, and a known conductive paste can be used. The conductive paste for internal electrodes contains, for example, particles including metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au or their precursors and a solvent. In the conductive paste for internal electrodes, a resin component serving as a dispersant and an adhesive may be further contained.

[0111] The conductive paste for connection layers is a conductive paste used to form the first connection layer 31 and the second connection layer 32. For example, the same conductive paste as that for internal electrodes can be used. However, a conductive paste different from that for internal electrodes can also be used as the conductive paste for connection layers.

[0112] In step S2 following step S1, the conductive paste for internal electrodes and the conductive paste for connection layers are coated on the prepared green ceramic sheet by methods such as printing. The conductive paste for internal electrodes is coated at positions where the first internal electrode 3 and the second internal electrode 4 are to be formed. The conductive paste for connection layers is coated at positions where the first connection layer 31 and the second connection layer 32 are to be formed. Here, electrode patterns and connection layer patterns for manufacturing a plurality of multilayer ceramic capacitors 100 at one time are formed.

[0113] In step S3 following step S2, a plurality of green ceramic sheets coated with the conductive paste for internal electrodes and the conductive paste for connection layers are laminated to fabricate a mother laminate. When fabricating the mother laminate, green ceramic sheets without electrode patterns and connection layer patterns may be arranged on the outer sides in the lamination direction. Here, after a plurality of green ceramic sheets are laminated, pressing is performed in the lamination direction to fabricate the mother laminate. The pressing method is arbitrary. For example, rigid pressing, isostatic pressing, etc. can be used.

[0114] In step S4 following step S3, a plurality of through holes extending in the lamination direction are formed in the mother laminate, and a conductive paste for via conductors is filled in the formed plurality of through holes. The through holes can be formed by any method. For example, they are formed by laser. The conductive paste for via conductors is a conductive paste used to form the first via conductor 5 and the second via conductor 6. For example, it contains particles including metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au or their precursors and a solvent. In the conductive paste for via conductors, a resin component serving as a dispersant and an adhesive may be further contained.

[0115] In step S5 following step S4, the mother laminate is cut to be singulated into a plurality of unburned small pieces. The cutting of the mother laminate can be performed, for example, by methods such as press cutting, cutting, and laser cutting.

[0116] In step S6 following step S5, the unfired small pieces are fired to fabricate the capacitor body 1. The first via conductor 5 and the second via conductor 6 are exposed on the first main surface 1a of the fabricated capacitor body 1, and the first connection layer 31 and the second connection layer 32 are exposed on the side surface.

[0117] In step S7 following step S6, the first external electrode 11 and the second external electrode 12 are formed on the surface of the capacitor body 1. Here, the first external electrode 11 and the second external electrode 12 are formed by plating treatment using a barrel plating method which is an example of a rotational plating method. Specifically, a plurality of capacitor bodies 1 and a plurality of conductive media are placed in a rotatable barrel, the barrel is rotated in a plating solution, and an electric current is applied, whereby plating is performed on the plating formation region where the first via conductor 5 and the second via conductor 6 are exposed among the first main surfaces 1a of the capacitor bodies 1. The conductive media are, for example, metal spheres. By forming a plating film on the plating formation region, the first external electrode 11 and the second external electrode 12 as plating electrodes are formed.

[0118] Furthermore, by plating treatment using the rotational plating method, a plating film is formed on the region where the first connection layer 31 and the second connection layer 32 are exposed among the side surfaces of the capacitor body 1, thereby forming the first metal layer 21 and the second metal layer 22 as plating layers.

[0119] Regarding the plating film in the plating formation region, it is formed not only when the conductive media come into contact with and are energized with the first via conductor 5 and the second via conductor 6 exposed on the first main surface 1a of the capacitor body 1, but also when the conductive media come into contact with and are energized with the first connection layer 31 and the second connection layer 32 exposed on the side surface of the capacitor body 1, and when the conductive media come into contact with and are energized with the first metal layer 21 and the second metal layer 22 formed on the side surface of the capacitor body 1 by plating treatment. Therefore, by plating treatment using the rotational plating method, the first external electrode 11 and the second external electrode 12 can be formed more reliably.

[0120] As described above, in the multilayer ceramic capacitor 100 in the present embodiment, the first metal layer 21 and the second metal layer 22 are provided at positions straddling two side surfaces of the capacitor body 1. Therefore, compared with a structure in which the first metal layer 21 and the second metal layer 22 are provided only on one side surface of the capacitor body 1, the opportunity for the conductive media to contact the first metal layer 21 and the second metal layer 22 increases during rotational plating, and thus the formation of the first external electrode 11 and the second external electrode 12 can be performed more reliably.

[0121] By the above manufacturing method, the multilayer ceramic capacitor 100 can be obtained.

[0122] <Second Embodiment>

[0123] In the multilayer ceramic capacitor 100 of the first embodiment, the number of the first external electrodes 11 and the second external electrodes 12 is two each, but as described above, it is not limited to two.

[0124] Figure 10 FIG. (a) schematically shows a top view of the multilayer ceramic capacitor 100A in the second embodiment. Figure 10 FIG. (b) schematically shows a bottom view of the multilayer ceramic capacitor 100A. Figure 11 It is a side view when observing the multilayer ceramic capacitor 100A shown Figure 10 in the direction of arrow Y2.

[0125] In the multilayer ceramic capacitor 100A of the second embodiment, six first external electrodes 11 and six second external electrodes 12 are respectively provided. A total of 12 external electrodes including the first external electrodes 11 and the second external electrodes 12 are arranged in a matrix. Here, four external electrodes are arranged in the row direction (the horizontal direction of the figure), and three external electrodes are arranged in the column direction (the vertical direction of the figure), but the number of external electrodes in the row direction is not limited to four, and the number of external electrodes in the column direction is not limited to three.

[0126] As Figure 10 shown in FIG. (a), the first external electrodes 11 and the second external electrodes 12 are alternately arranged in the row direction, and only the first external electrodes 11 or only the second external electrodes 12 are arranged in the column direction. However, the arrangement pattern of the first external electrodes 11 and the second external electrodes 12 is not limited to Figure 10 the arrangement pattern shown in FIG. (a).

[0127] Figure 12 FIG. (a) schematically shows a top view of the first internal electrode 3. Figure 12 FIG. (b) schematically shows a top view of the second internal electrode 4. In Figure 12 FIGS. (a) and (b), the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown together. In addition, in Figure 12 FIG. (a), the first connection layer 31 is shown together, and in Figure 12 FIG. (b), the second connection layer 32 is shown together.

[0128] In the first internal electrode 3, a plurality of first through holes 3a for inserting the second via conductor 6 are formed. In the second internal electrode 4, a plurality of second through holes 4a for inserting the first via conductor 5 are formed.

[0129] As shown in Figure 12 in (b) thereof, the first via conductor 5 provided at a position overlapping with the second internal electrode 4 in the stacking direction T is inserted through the second through hole 4a formed in the second internal electrode 4 and is insulated from the second internal electrode 4. Further, as shown in Figure 12 in (a) thereof, the second via conductor 6 provided at a position overlapping with the first internal electrode 3 in the stacking direction T is inserted through the first through hole 3a formed in the first internal electrode 3 and is insulated from the first internal electrode 3.

[0130] As shown in Figure 12 in (a) thereof, the first connection layer 31 is provided on the layer where the first internal electrode 3 is provided. The first connection layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not in direct contact with the first internal electrode 3. As shown in Figure 12 in (a) thereof, the second connection layer 32 is not provided on the layer where the first internal electrode 3 is provided.

[0131] As shown in Figure 12 in (b) thereof, the second connection layer 32 is provided on the layer where the second internal electrode 4 is provided. The second connection layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connection layer 32 is not in direct contact with the second internal electrode 4. As shown in Figure 12 in (b) thereof, the first connection layer 31 is not provided on the layer where the second internal electrode 4 is provided.

[0132] Similar to the multilayer ceramic capacitor 100 in the first embodiment, the multilayer ceramic capacitor 100A in the present embodiment also has a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 provided on the side surface of the capacitor body 1, so that the formation of the first external electrode 11 and the second external electrode 12 by rotary plating can be performed more reliably.

[0133] <Third Embodiment>

[0134] In the multilayer ceramic capacitor 100 in the above-described first embodiment and the multilayer ceramic capacitor 100A in the second embodiment, the first metal layer 21 and the second metal layer 22 are provided on the side surface of the capacitor body 1, but it is also possible to adopt a structure in which only the first metal layer 21 is provided.

[0135] Figure 13 In (a) thereof, a top view schematically showing the multilayer ceramic capacitor 100B in the third embodiment is shown, Figure 13 In (b) thereof, a bottom view schematically showing the multilayer ceramic capacitor 100B in the third embodiment is shown.

[0136] In the multilayer ceramic capacitor 100B of the third embodiment, five first external electrodes 11 and four second external electrodes 12 are provided. A total of nine external electrodes including the first external electrodes 11 and the second external electrodes 12 are arranged in a matrix. Here, three external electrodes are arranged in the row direction and three external electrodes are arranged in the column direction, but the number of external electrodes in the row direction is not limited to three, and the number of external electrodes in the column direction is not limited to three.

[0137] In the present embodiment, the first external electrodes 11 are provided at the positions of the four corners and the central position among the nine arrangement positions of three rows and three columns, and the second external electrodes 12 are provided at the other positions.

[0138] The multilayer ceramic capacitor 100B in the present embodiment includes a first metal layer 21 provided on the side surface of the capacitor body 1, but does not include a second metal layer. In the present embodiment, the first metal layer 21 is provided at four positions, namely, the corner positions where the capacitor body 1 crosses from the first side surface 1c to the second side surface 1d, the corner positions where the capacitor body 1 crosses from the second side surface 1d to the third side surface 1e, the corner positions where the capacitor body 1 crosses from the third side surface 1e to the fourth side surface 1f, and the corner positions where the capacitor body 1 crosses from the fourth side surface 1f to the first side surface 1c. However, the positions where the first metal layer 21 is provided are not limited to the above positions, and the number of the first metal layers 21 is not limited to four.

[0139] Figure 14 (a) is a top view schematically showing the first internal electrode 3, Figure 14 (b) is a top view schematically showing the second internal electrode 4. In Figure 14 (a) and (b), the dielectric layer 2, the first via conductor 5, the second via conductor 6, and the first connection layer 31 are also shown together.

[0140] In the first internal electrode 3, a plurality of first through holes 3a for inserting the second via conductor 6 are formed. In the second internal electrode 4, a second through hole 4a for inserting the first via conductor 5 is formed.

[0141] As Figure 14 (b) shows, the first via conductor 5 provided at a position overlapping the second internal electrode 4 in the stacking direction T is inserted into the second through hole 4a formed in the second internal electrode 4 and is insulated from the second internal electrode 4. In addition, as Figure 14 (a) shows, the second via conductor 6 provided at a position overlapping the first internal electrode 3 in the stacking direction T is inserted into the first through hole 3a formed in the first internal electrode 3 and is insulated from the first internal electrode 3.

[0142] As shown Figure 14 in FIGS. (a) and (b), the first connection layer 31 is provided in the layer provided with the first internal electrode 3 and the layer provided with the second internal electrode 4, respectively. The first connection layer 31 is provided at the positions of the four corners of the dielectric layer 2 that is rectangular when viewed in the stacking direction T. The first connection layer 31 is connected to the first via conductor 5 at the closest position and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not directly connected to the first internal electrode 3.

[0143] According to the multilayer ceramic capacitor 100B in the present embodiment, since the first metal layer 21 electrically connected to the first via conductor 5 is provided on the side surface of the capacitor body 1, the formation of the first external electrode 11 by spin plating can be performed more reliably.

[0144] <Fourth Embodiment>

[0145] As described above, in the multilayer ceramic capacitor 100B in the third embodiment, a total of nine external electrodes are arranged in a matrix, and only the first metal layer 21 is provided on the side surface of the capacitor body 1.

[0146] In contrast, in the multilayer ceramic capacitor 100C in the fourth embodiment, a total of nine external electrodes are arranged in a matrix, and the first metal layer 21 and the second metal layer 22 are provided on the side surface of the capacitor body 1.

[0147] Figure 15 FIG. (a) schematically shows a top view of the multilayer ceramic capacitor 100C in the fourth embodiment. Figure 15 FIG. (b) schematically shows a bottom view of the multilayer ceramic capacitor 100C. Figure 16 It is a side view when observing the multilayer ceramic capacitor 100C shown Figure 15 in the direction of arrow Y3.

[0148] Similar to the multilayer ceramic capacitor 100B in the third embodiment, in the multilayer ceramic capacitor 100C in the fourth embodiment, five first external electrodes 11 and four second external electrodes 12 are also provided. As Figure 15 shown in FIG. (a), the arrangement positions of the plurality of first external electrodes 11 and the plurality of second external electrodes 12 are the same as those of the multilayer ceramic capacitor 100B in the third embodiment.

[0149] The arrangement position of the first metal layer 21 is also the same as that of the multilayer ceramic capacitor 100B in the third embodiment. That is, the first metal layer 21 is provided at the positions of four parts at the corners of the capacitor body 1 straddling two side surfaces.

[0150] In the present embodiment, the second metal layer 22 is disposed at a position between two first metal layers 21 on the first side surface 1c, the second side surface 1d, the third side surface 1e, and the fourth side surface 1f of the capacitor body 1. That is, as Figure 16 shown, the second metal layer 22 disposed on the first side surface 1c of the capacitor body 1 is located between two first metal layers 21 disposed on the first side surface 1c. Similarly, the second metal layer 22 disposed on the second side surface 1d of the capacitor body 1 is located between two first metal layers 21 disposed on the second side surface 1d. The second metal layer 22 disposed on the third side surface 1e of the capacitor body 1 is located between two first metal layers 21 disposed on the third side surface 1e. The second metal layer 22 disposed on the fourth side surface 1f of the capacitor body 1 is located between two first metal layers 21 disposed on the fourth side surface 1f.

[0151] Figure 17 (a) of Figure 17 is a top view schematically showing the first internal electrode 3, Figure 17 (b) of Figure 17 is a top view schematically showing the second internal electrode 4. In Figure 17 (a) and (b) of , the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connection layer 31, and the second connection layer 32 are also shown together.

[0152] In the first internal electrode 3, a plurality of first through holes 3a for inserting the second via conductor 6 are formed. In the second internal electrode 4, a second through hole 4a for inserting the first via conductor 5 is formed.

[0153] As Figure 17 (b) of Figure 17 shows, the first via conductor 5 disposed at a position overlapping the second internal electrode 4 in the stacking direction T is inserted through the second through hole 4a formed in the second internal electrode 4 and is insulated from the second internal electrode 4. In addition, as Figure 17 (a) of shows, the second via conductor 6 disposed at a position overlapping the first internal electrode 3 in the stacking direction T is inserted through the first through hole 3a formed in the first internal electrode 3 and is insulated from the first internal electrode 3.

[0154] As Figure 17 (a) and (b) of show, the first connection layer 31 and the second connection layer 32 are respectively disposed on the layer provided with the first internal electrode 3 and the layer provided with the second internal electrode 4. The first connection layer 31 is disposed at the positions of the four corners of the dielectric layer 2 which is rectangular when viewed in the stacking direction T. The first connection layer 31 is in contact with the first via conductor 5 at the closest position and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not directly in contact with the first internal electrode 3.

[0155] As Figure 17As shown in FIGS. (a) and (b), the second connection layer 32 is respectively disposed at the central positions of the four side edges of the dielectric layer 2 which is rectangular when viewed in the stacking direction T. The second connection layer 32 is connected to the second via conductor 6 at the closest position, and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connection layer 32 is not directly connected to the second internal electrode 4.

[0156] Similar to the stacked ceramic capacitor 100 in the first embodiment, the stacked ceramic capacitor 100C in the fourth embodiment also has a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 provided on the side surface of the capacitor body 1. Therefore, the formation of the first external electrode 11 and the second external electrode 12 by rotary plating can be performed more reliably.

[0157] (Modification of the fourth embodiment)

[0158] In Figure 17 the structure shown in FIGS. (a) and (b), the first connection layer 31 and the second connection layer 32 are respectively provided in the layer provided with the first internal electrode 3 and the layer provided with the second internal electrode 4. However, it can also be configured such that the first connection layer 31 is provided in the layer provided with the first internal electrode 3 and the second connection layer 32 is provided in the layer provided with the second internal electrode 4. In Figure 18 FIG. (a) schematically shows a top view of the first internal electrode 3 and the first connection layer 31 in this case. In Figure 18 FIG. (b) schematically shows a top view of the second internal electrode 4 and the second connection layer 32. In Figure 18 FIGS. (a) and (b), the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown together. In addition, the number and arrangement positions of the first via conductor 5 and the second via conductor 6 are the same as those of the first via conductor 5 and the second via conductor 6 shown in Figure 17 .

[0159] As Figure 18 shown in FIG. (a), the first connection layer 31 is connected to the first via conductor 5 at the closest position, and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connection layer 31 is not directly connected to the first internal electrode 3. The arrangement position of the first connection layer 31 when viewed in the stacking direction T is the same as the arrangement position shown in Figure 17 FIG. (a). As Figure 18 shown in FIG. (a), the second connection layer 32 is not provided in the layer provided with the first internal electrode 3.

[0160] As Figure 18As shown in FIG. (b), the second connection layer 32 is connected to the second via conductor 6 at the closest position, and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connection layer 32 is not directly connected to the second internal electrode 4. The arranged position of the second connection layer 32 when observed in the stacking direction T is the same as Figure 17 the arranged position shown in FIG. (b). As Figure 18 shown in FIG. (b), the first connection layer 31 is not provided in the layer where the second internal electrode 4 is provided.

[0161] According to Figure 18 the structures shown in FIGS. (a) and (b), compared with Figure 17 the structures shown in FIGS. (a) and (b), the number of the first connection layer 31 and the second connection layer 32 can be reduced to about half. Therefore, when manufacturing, it is possible to suppress the intrusion of the plating solution from the outside to the inside, and it is possible to suppress the intrusion of moisture and the like from the outside to the inside of the finished product. That is, at the positions where the first connection layer 31 and the second connection layer 32 are exposed among the side surfaces of the capacitor body 1, although the plating solution and moisture are likely to intrude into the inside, since the number of the first connection layer 31 and the second connection layer 32 is small, the intrusion of the plating solution, moisture and the like into the inside can be suppressed.

[0162] The present invention is not limited to the above-described embodiments, and various applications and modifications can be made within the scope of the present invention. For example, the characteristic structures described in each of the embodiments and their modification examples can be appropriately combined.

[0163] The arranged pattern of the plurality of external electrodes arranged in a matrix shape is not limited to the arranged patterns of the above-described embodiments and modification examples. For example, when the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is odd, it can also be set to Figure 19 the arranged pattern shown. In Figure 19 the arranged pattern shown, external electrodes of the same type are arranged in the row direction, and the first external electrode 11 and the second external electrode 12 are alternately arranged in the column direction. However, it is also possible to alternately arrange the first external electrode 11 and the second external electrode 12 in the row direction and arrange external electrodes of the same type in the column direction. In Figure 19 the arranged pattern shown, similar to Figure 13 the arranged pattern shown, the external electrodes provided on the side surface of the capacitor body 1 are only the first external electrode 11.

[0164] When the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd, it can also be set to Figure 20 the arranged patterns shown in FIGS. (a) and (b). In Figure 20In the configuration mode shown in (a), the first external electrode 11 and the second external electrode 12 are alternately arranged in the row direction, and the first external electrode 11 and the second external electrode 12 are also alternately arranged in the column direction. In Figure 20 In the configuration mode shown in (b), external electrodes of the same type are arranged in the row direction, and the first external electrode 11 and the second external electrode 12 are alternately arranged in the column direction. In Figure 20 In the configuration mode shown in (a), the first metal layer 21 and the second metal layer 22 are provided on the side surface of the capacitor body 1. In Figure 20 In the configuration mode shown in (b), only the first metal layer 21 is provided on the side surface of the capacitor body 1. In addition, when the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is even, the external electrodes can also be arranged in the same configuration mode as when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd.

[0165] When the number of external electrodes is more than two rows and two columns, and the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is even, it can be set to Figure 21 the configuration modes shown in (a) and (b). In Figure 21 In the configuration mode shown in (a), the first external electrode 11 and the second external electrode 12 are alternately arranged in the row direction, and the first external electrode 11 and the second external electrode 12 are also alternately arranged in the column direction. In Figure 21 In the configuration mode shown in (b), external electrodes of the same type are arranged in the row direction, and the first external electrode 11 and the second external electrode 12 are alternately arranged in the column direction. However, it is also possible to alternately arrange the first external electrode 11 and the second external electrode 12 in the row direction and arrange external electrodes of the same type in the column direction. In Figure 21 In the configuration modes shown in (a) and (b), the first metal layer 21 and the second metal layer 22 are respectively provided on the side surface of the capacitor body 1.

[0166] When mounting the multilayer ceramic capacitor 100 on the mounting substrate, the structure can also be set such that the first metal layer 21 and the second metal layer 22 are not joined to the land electrodes of the mounting substrate. In this case, since the first metal layer 21 and the second metal layer 22 become unnecessary in practical use as a finished product, it is also possible to cover the first metal layer 21 and the second metal layer 22 with resin or the like.

[0167] In the multilayer ceramic capacitor according to each of the above-described embodiments and its modified examples, a first connection layer 31 is provided inside the capacitor body 1 to electrically connect the first via conductor 5 and the first metal layer 21. However, it is also possible not to provide the first connection layer 31 and to electrically connect the first via conductor 5 and the first metal layer 21 through the first internal electrode 3. In this case, it is only necessary to form the first internal electrode 3 into a shape that extends to the side surface of the capacitor body 1. Similarly, in a multilayer ceramic capacitor including a second metal layer 22, it is also possible not to provide the second connection layer 32 and to electrically connect the second via conductor 6 and the second metal layer 22 through the second internal electrode 4.

[0168] The multilayer ceramic capacitor in the present application is as follows.

[0169] <1>. A multilayer ceramic capacitor, comprising:

[0170] A capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated;

[0171] A first via conductor provided inside the capacitor body and electrically connected to the plurality of first internal electrodes;

[0172] A second via conductor provided inside the capacitor body and electrically connected to the plurality of second internal electrodes;

[0173] A first external electrode provided on at least one of a first main surface and a second main surface of the capacitor body that are opposite to each other in a lamination direction of the dielectric layer, the first internal electrode, and the second internal electrode, and connected to the first via conductor;

[0174] A second external electrode provided on the at least one main surface of the capacitor body and connected to the second via conductor; and

[0175] A first metal layer provided on a side surface of the capacitor body that is a surface other than the first main surface and the second main surface, and electrically connected to the first via conductor.

[0176] <2>. The multilayer ceramic capacitor according to <1>, characterized in that

[0177] The multilayer ceramic capacitor further comprises: a first connection layer provided inside the capacitor body to electrically connect the first via conductor and the first metal layer.

[0178] <3>. A multilayer ceramic capacitor, comprising:

[0179] A capacitor body, in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated;

[0180] A first via conductor, disposed inside the capacitor body and electrically connected to the plurality of first internal electrodes;

[0181] A second via conductor, disposed inside the capacitor body and electrically connected to the plurality of second internal electrodes;

[0182] A first external electrode, disposed on at least one of a first main surface and a second main surface that are opposite to each other in a lamination direction of the dielectric layer, the first internal electrode, and the second internal electrode among surfaces of the capacitor body, and connected to the first via conductor;

[0183] A second external electrode, disposed on the at least one main surface of the capacitor body and connected to the second via conductor;

[0184] A first metal layer, disposed on a side surface that is a surface other than the first main surface and the second main surface of the capacitor body, and electrically connected to the first via conductor; and

[0185] A second metal layer, disposed on the side surface of the capacitor body and electrically connected to the second via conductor.

[0186] <4>. The multilayer ceramic capacitor according to <3>, wherein

[0187] The multilayer ceramic capacitor further includes:

[0188] A first connection layer, disposed inside the capacitor body and electrically connecting the first via conductor and the first metal layer; and

[0189] A second connection layer, disposed inside the capacitor body and electrically connecting the second via conductor and the second metal layer.

[0190] <5>. The multilayer ceramic capacitor according to <3> or <4>, wherein

[0191] The first metal layer and the second metal layer are respectively disposed at positions of corners of the capacitor body that straddle two of the side surfaces.

[0192] <6>. The multilayer ceramic capacitor according to any one of <3> to <5>, wherein

[0193] There are four side surfaces of the capacitor body,

[0194] One of the first metal layer and the second metal layer is disposed at four positions at the corners of the capacitor body straddling two of the side surfaces, and the other metal layer is disposed at positions between the two one metal layers on each of the four side surfaces.

[0195] <7>. The multilayer ceramic capacitor according to <4>, characterized in that

[0196] The first connection layer is disposed on the layer provided with the second internal electrode.

[0197] The second connection layer is disposed on the layer provided with the first internal electrode.

[0198] <8>. The multilayer ceramic capacitor according to <4>, characterized in that

[0199] The first connection layer and the second connection layer are respectively disposed on the layer provided with the first internal electrode and the layer provided with the second internal electrode.

[0200] <9>. The multilayer ceramic capacitor according to <4>, characterized in that

[0201] The first connection layer is disposed on the layer provided with the first internal electrode.

[0202] The second connection layer is disposed on the layer provided with the second internal electrode.

[0203] <10>. The multilayer ceramic capacitor according to <8> or <9>, characterized in that

[0204] The first connection layer is in contact with the first via conductor but not in contact with the first internal electrode.

[0205] The second connection layer is in contact with the second via conductor but not in contact with the second internal electrode.

[0206] <11>. The multilayer ceramic capacitor according to any one of <1> to <10>, characterized in that

[0207] The first metal layer is a plating layer.

[0208] The first external electrode and the second external electrode are plating electrodes.

[0209] Description of reference numerals

[0210] 1: Capacitor body;

[0211] 2: Dielectric layer;

[0212] 3: First internal electrode;

[0213] 3a: First through-hole;

[0214] 4: Second internal electrode;

[0215] 4a: Second through-hole;

[0216] 5: First via conductor;

[0217] 6: Second via conductor;

[0218] 11: First external electrode;

[0219] 12: Second external electrode;

[0220] 21: First metal layer;

[0221] 22: Second metal layer;

[0222] 31: First connection layer;

[0223] 32: Second connection layer;

[0224] 100, 100A, 100B, 100C: Multilayer ceramic capacitor;

[0225] 200: Connection substrate;

[0226] 210: Pad electrode;

[0227] 220: Solder.

Claims

1. A multilayer ceramic capacitor, characterized in that, Comprising: A capacitor body having a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes laminated thereon; A first via conductor disposed inside the capacitor body and electrically connected to the plurality of first internal electrodes; A second via conductor disposed inside the capacitor body and electrically connected to the plurality of second internal electrodes; A first external electrode disposed on at least one of a first main surface and a second main surface that are opposite to each other in a lamination direction of the dielectric layer, the first internal electrode, and the second internal electrode among surfaces of the capacitor body, and connected to the first via conductor; A second external electrode disposed on the at least one main surface of the capacitor body and connected to the second via conductor; And A first metal layer disposed on a side surface that is a surface other than the first main surface and the second main surface among surfaces of the capacitor body and electrically connected to the first via conductor.

2. The multilayer ceramic capacitor according to claim 1, wherein The multilayer ceramic capacitor further comprises: a first connection layer disposed inside the capacitor body for electrically connecting the first via conductor and the first metal layer.

3. A multilayer ceramic capacitor, characterized in that, Comprising: A capacitor body having a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes laminated thereon; A first via conductor disposed inside the capacitor body and electrically connected to the plurality of first internal electrodes; A second via conductor disposed inside the capacitor body and electrically connected to the plurality of second internal electrodes; A first external electrode disposed on at least one of a first main surface and a second main surface that are opposite to each other in a lamination direction of the dielectric layer, the first internal electrode, and the second internal electrode among surfaces of the capacitor body, and connected to the first via conductor; A second external electrode disposed on the at least one main surface of the capacitor body and connected to the second via conductor; A first metal layer disposed on a side surface that is a surface other than the first main surface and the second main surface among surfaces of the capacitor body and electrically connected to the first via conductor; And A second metal layer disposed on the side surface of the capacitor body and electrically connected to the second via conductor.

4. The multilayer ceramic capacitor according to claim 3, wherein The multilayer ceramic capacitor further comprises: A first connection layer disposed inside the capacitor body for electrically connecting the first via conductor and the first metal layer; and A second connection layer disposed inside the capacitor body for electrically connecting the second via conductor and the second metal layer.

5. The multilayer ceramic capacitor according to claim 3 or 4, wherein The first metal layer and the second metal layer are respectively disposed at positions of corners of the capacitor body straddling two of the side surfaces.

6. The multilayer ceramic capacitor according to any one of claims 3 to 5, wherein There are four of the side surfaces of the capacitor body One of the first metal layer and the second metal layer is disposed at positions of four parts at corners of the capacitor body straddling two of the side surfaces, and the other metal layer is disposed at positions between the two one metal layers on each of the four side surfaces.

7. The multilayer ceramic capacitor according to claim 4, wherein the first connection layer is disposed in the layer where the second internal electrode is provided, the second connection layer is disposed in the layer where the first internal electrode is provided.

8. The multilayer ceramic capacitor according to claim 4, wherein the first connection layer and the second connection layer are respectively disposed in the layer where the first internal electrode is provided and the layer where the second internal electrode is provided.

9. The multilayer ceramic capacitor according to claim 4, wherein the first connection layer is disposed in the layer where the first internal electrode is provided, the second connection layer is disposed in the layer where the second internal electrode is provided.

10. The multilayer ceramic capacitor according to claim 8 or 9, wherein the first connection layer is in contact with the first via conductor but not in contact with the first internal electrode, the second connection layer is in contact with the second via conductor but not in contact with the second internal electrode.

11. The multilayer ceramic capacitor according to any one of claims 1 to 10, wherein the first metal layer is a plating layer, the first external electrode and the second external electrode are plating electrodes.

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